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diff --git a/arch/x86/kernel/smp_32.c b/arch/x86/kernel/smp_32.c
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1/*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * This code is released under the GNU General Public License version 2 or
8 * later.
9 */
10
11#include <linux/init.h>
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/spinlock.h>
16#include <linux/kernel_stat.h>
17#include <linux/mc146818rtc.h>
18#include <linux/cache.h>
19#include <linux/interrupt.h>
20#include <linux/cpu.h>
21#include <linux/module.h>
22
23#include <asm/mtrr.h>
24#include <asm/tlbflush.h>
25#include <asm/mmu_context.h>
26#include <mach_apic.h>
27#include <asm/proto.h>
28
29/*
30 * Some notes on x86 processor bugs affecting SMP operation:
31 *
32 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
33 * The Linux implications for SMP are handled as follows:
34 *
35 * Pentium III / [Xeon]
36 * None of the E1AP-E3AP errata are visible to the user.
37 *
38 * E1AP. see PII A1AP
39 * E2AP. see PII A2AP
40 * E3AP. see PII A3AP
41 *
42 * Pentium II / [Xeon]
43 * None of the A1AP-A3AP errata are visible to the user.
44 *
45 * A1AP. see PPro 1AP
46 * A2AP. see PPro 2AP
47 * A3AP. see PPro 7AP
48 *
49 * Pentium Pro
50 * None of 1AP-9AP errata are visible to the normal user,
51 * except occasional delivery of 'spurious interrupt' as trap #15.
52 * This is very rare and a non-problem.
53 *
54 * 1AP. Linux maps APIC as non-cacheable
55 * 2AP. worked around in hardware
56 * 3AP. fixed in C0 and above steppings microcode update.
57 * Linux does not use excessive STARTUP_IPIs.
58 * 4AP. worked around in hardware
59 * 5AP. symmetric IO mode (normal Linux operation) not affected.
60 * 'noapic' mode has vector 0xf filled out properly.
61 * 6AP. 'noapic' mode might be affected - fixed in later steppings
62 * 7AP. We do not assume writes to the LVT deassering IRQs
63 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
64 * 9AP. We do not use mixed mode
65 *
66 * Pentium
67 * There is a marginal case where REP MOVS on 100MHz SMP
68 * machines with B stepping processors can fail. XXX should provide
69 * an L1cache=Writethrough or L1cache=off option.
70 *
71 * B stepping CPUs may hang. There are hardware work arounds
72 * for this. We warn about it in case your board doesn't have the work
73 * arounds. Basically that's so I can tell anyone with a B stepping
74 * CPU and SMP problems "tough".
75 *
76 * Specific items [From Pentium Processor Specification Update]
77 *
78 * 1AP. Linux doesn't use remote read
79 * 2AP. Linux doesn't trust APIC errors
80 * 3AP. We work around this
81 * 4AP. Linux never generated 3 interrupts of the same priority
82 * to cause a lost local interrupt.
83 * 5AP. Remote read is never used
84 * 6AP. not affected - worked around in hardware
85 * 7AP. not affected - worked around in hardware
86 * 8AP. worked around in hardware - we get explicit CS errors if not
87 * 9AP. only 'noapic' mode affected. Might generate spurious
88 * interrupts, we log only the first one and count the
89 * rest silently.
90 * 10AP. not affected - worked around in hardware
91 * 11AP. Linux reads the APIC between writes to avoid this, as per
92 * the documentation. Make sure you preserve this as it affects
93 * the C stepping chips too.
94 * 12AP. not affected - worked around in hardware
95 * 13AP. not affected - worked around in hardware
96 * 14AP. we always deassert INIT during bootup
97 * 15AP. not affected - worked around in hardware
98 * 16AP. not affected - worked around in hardware
99 * 17AP. not affected - worked around in hardware
100 * 18AP. not affected - worked around in hardware
101 * 19AP. not affected - worked around in BIOS
102 *
103 * If this sounds worrying believe me these bugs are either ___RARE___,
104 * or are signal timing bugs worked around in hardware and there's
105 * about nothing of note with C stepping upwards.
106 */