1 files changed, 67 insertions, 385 deletions

diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 6dff1286ad8a..545440e471b2 100644
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -71,6 +71,7 @@
 #include <asm/topology.h>
 #include <asm/trampoline.h>
 #include <asm/pat.h>
+#include <asm/mmconfig.h>
 
 #include <mach_apic.h>
 #ifdef CONFIG_PARAVIRT
@@ -79,6 +80,8 @@
 #define ARCH_SETUP
 #endif
 
+#include "cpu/cpu.h"
+
 /*
  * Machine setup..
  */
@@ -95,8 +98,6 @@ int bootloader_type;
 
 unsigned long saved_video_mode;
 
-int force_mwait __cpuinitdata;
-
 /*
  * Early DMI memory
  */
@@ -118,7 +119,7 @@ EXPORT_SYMBOL_GPL(edid_info);
 
 extern int root_mountflags;
 
-char __initdata command_line[COMMAND_LINE_SIZE];
+static char __initdata command_line[COMMAND_LINE_SIZE];
 
 static struct resource standard_io_resources[] = {
         { .name = "dma1", .start = 0x00, .end = 0x1f,
@@ -164,6 +165,7 @@ static struct resource bss_resource = {
         .flags = IORESOURCE_RAM,
 };
 
+static void __init early_cpu_init(void);
 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 
 #ifdef CONFIG_PROC_VMCORE
@@ -293,18 +295,6 @@ static void __init parse_setup_data(void)
         }
 }
 
-#ifdef CONFIG_PCI_MMCONFIG
-extern void __cpuinit fam10h_check_enable_mmcfg(void);
-extern void __init check_enable_amd_mmconf_dmi(void);
-#else
-void __cpuinit fam10h_check_enable_mmcfg(void)
-{
-}
-void __init check_enable_amd_mmconf_dmi(void)
-{
-}
-#endif
-
 /*
  * setup_arch - architecture-specific boot-time initializations
  *
@@ -352,6 +342,7 @@ void __init setup_arch(char **cmdline_p)
         bss_resource.start = virt_to_phys(&__bss_start);
         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 
+        early_cpu_init();
         early_identify_cpu(&boot_cpu_data);
 
         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
@@ -537,7 +528,20 @@ void __init setup_arch(char **cmdline_p)
         check_enable_amd_mmconf_dmi();
 }
 
-static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
+struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
+
+static void __cpuinit default_init(struct cpuinfo_x86 *c)
+{
+        display_cacheinfo(c);
+}
+
+static struct cpu_dev __cpuinitdata default_cpu = {
+        .c_init = default_init,
+        .c_vendor = "Unknown",
+};
+static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
+
+int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 {
         unsigned int *v;
 
@@ -553,7 +557,7 @@ static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 }
 
 
-static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
+void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 {
         unsigned int n, dummy, eax, ebx, ecx, edx;
 
@@ -585,228 +589,6 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
         }
 }
 
-#ifdef CONFIG_NUMA
-static int __cpuinit nearby_node(int apicid)
-{
-        int i, node;
-
-        for (i = apicid - 1; i >= 0; i--) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
-                node = apicid_to_node[i];
-                if (node != NUMA_NO_NODE && node_online(node))
-                        return node;
-        }
-        return first_node(node_online_map); /* Shouldn't happen */
-}
-#endif
-
-/*
- * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
- * Assumes number of cores is a power of two.
- */
-static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits;
-#ifdef CONFIG_NUMA
-        int cpu = smp_processor_id();
-        int node = 0;
-        unsigned apicid = hard_smp_processor_id();
-#endif
-        bits = c->x86_coreid_bits;
-
-        /* Low order bits define the core id (index of core in socket) */
-        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
-        /* Convert the initial APIC ID into the socket ID */
-        c->phys_proc_id = c->initial_apicid >> bits;
-
-#ifdef CONFIG_NUMA
-        node = c->phys_proc_id;
-        if (apicid_to_node[apicid] != NUMA_NO_NODE)
-                node = apicid_to_node[apicid];
-        if (!node_online(node)) {
-                /* Two possibilities here:
-                   - The CPU is missing memory and no node was created.
-                   In that case try picking one from a nearby CPU
-                   - The APIC IDs differ from the HyperTransport node IDs
-                   which the K8 northbridge parsing fills in.
-                   Assume they are all increased by a constant offset,
-                   but in the same order as the HT nodeids.
-                   If that doesn't result in a usable node fall back to the
-                   path for the previous case.  */
-
-                int ht_nodeid = c->initial_apicid;
-
-                if (ht_nodeid >= 0 &&
-                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
-                        node = apicid_to_node[ht_nodeid];
-                /* Pick a nearby node */
-                if (!node_online(node))
-                        node = nearby_node(apicid);
-        }
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-#endif
-}
-
-static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_SMP
-        unsigned bits, ecx;
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level < 0x80000008)
-                return;
-
-        ecx = cpuid_ecx(0x80000008);
-
-        c->x86_max_cores = (ecx & 0xff) + 1;
-
-        /* CPU telling us the core id bits shift? */
-        bits = (ecx >> 12) & 0xF;
-
-        /* Otherwise recompute */
-        if (bits == 0) {
-                while ((1 << bits) < c->x86_max_cores)
-                        bits++;
-        }
-
-        c->x86_coreid_bits = bits;
-
-#endif
-}
-
-#define ENABLE_C1E_MASK         0x18000000
-#define CPUID_PROCESSOR_SIGNATURE       1
-#define CPUID_XFAM              0x0ff00000
-#define CPUID_XFAM_K8           0x00000000
-#define CPUID_XFAM_10H          0x00100000
-#define CPUID_XFAM_11H          0x00200000
-#define CPUID_XMOD              0x000f0000
-#define CPUID_XMOD_REV_F        0x00040000
-
-/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
-{
-        u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-
-        switch (eax & CPUID_XFAM) {
-        case CPUID_XFAM_K8:
-                if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                        break;
-        case CPUID_XFAM_10H:
-        case CPUID_XFAM_11H:
-                rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
-                if (lo & ENABLE_C1E_MASK)
-                        return 1;
-                break;
-        default:
-                /* err on the side of caution */
-                return 1;
-        }
-        return 0;
-}
-
-static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
-{
-        early_init_amd_mc(c);
-
-        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
-        if (c->x86_power & (1<<8))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-}
-
-static void __cpuinit init_amd(struct cpuinfo_x86 *c)
-{
-        unsigned level;
-
-#ifdef CONFIG_SMP
-        unsigned long value;
-
-        /*
-         * Disable TLB flush filter by setting HWCR.FFDIS on K8
-         * bit 6 of msr C001_0015
-         *
-         * Errata 63 for SH-B3 steppings
-         * Errata 122 for all steppings (F+ have it disabled by default)
-         */
-        if (c->x86 == 15) {
-                rdmsrl(MSR_K8_HWCR, value);
-                value |= 1 << 6;
-                wrmsrl(MSR_K8_HWCR, value);
-        }
-#endif
-
-        /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
-           3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
-        clear_cpu_cap(c, 0*32+31);
-
-        /* On C+ stepping K8 rep microcode works well for copy/memset */
-        level = cpuid_eax(1);
-        if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
-                             level >= 0x0f58))
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        if (c->x86 == 0x10 || c->x86 == 0x11)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-
-        /* Enable workaround for FXSAVE leak */
-        if (c->x86 >= 6)
-                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
-
-        level = get_model_name(c);
-        if (!level) {
-                switch (c->x86) {
-                case 15:
-                        /* Should distinguish Models here, but this is only
-                           a fallback anyways. */
-                        strcpy(c->x86_model_id, "Hammer");
-                        break;
-                }
-        }
-        display_cacheinfo(c);
-
-        /* Multi core CPU? */
-        if (c->extended_cpuid_level >= 0x80000008)
-                amd_detect_cmp(c);
-
-        if (c->extended_cpuid_level >= 0x80000006 &&
-                (cpuid_edx(0x80000006) & 0xf000))
-                num_cache_leaves = 4;
-        else
-                num_cache_leaves = 3;
-
-        if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
-                set_cpu_cap(c, X86_FEATURE_K8);
-
-        /* MFENCE stops RDTSC speculation */
-        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
-
-        if (c->x86 == 0x10)
-                fam10h_check_enable_mmcfg();
-
-        if (amd_apic_timer_broken())
-                disable_apic_timer = 1;
-
-        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
-                unsigned long long tseg;
-
-                /*
-                 * Split up direct mapping around the TSEG SMM area.
-                 * Don't do it for gbpages because there seems very little
-                 * benefit in doing so.
-                 */
-                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
-                (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
-                        set_memory_4k((unsigned long)__va(tseg), 1);
-        }
-}
-
 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
@@ -857,135 +639,59 @@ out:
 #endif
 }
 
-/*
- * find out the number of processor cores on the die
- */
-static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
-{
-        unsigned int eax, t;
-
-        if (c->cpuid_level < 4)
-                return 1;
-
-        cpuid_count(4, 0, &eax, &t, &t, &t);
-
-        if (eax & 0x1f)
-                return ((eax >> 26) + 1);
-        else
-                return 1;
-}
-
-static void __cpuinit srat_detect_node(void)
-{
-#ifdef CONFIG_NUMA
-        unsigned node;
-        int cpu = smp_processor_id();
-        int apicid = hard_smp_processor_id();
-
-        /* Don't do the funky fallback heuristics the AMD version employs
-           for now. */
-        node = apicid_to_node[apicid];
-        if (node == NUMA_NO_NODE || !node_online(node))
-                node = first_node(node_online_map);
-        numa_set_node(cpu, node);
-
-        printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
-#endif
-}
-
-static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
-{
-        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-            (c->x86 == 0x6 && c->x86_model >= 0x0e))
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-}
-
-static void __cpuinit init_intel(struct cpuinfo_x86 *c)
+static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 {
-        /* Cache sizes */
-        unsigned n;
-
-        init_intel_cacheinfo(c);
-        if (c->cpuid_level > 9) {
-                unsigned eax = cpuid_eax(10);
-                /* Check for version and the number of counters */
-                if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
-                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
+        char *v = c->x86_vendor_id;
+        int i;
+        static int printed;
+
+        for (i = 0; i < X86_VENDOR_NUM; i++) {
+                if (cpu_devs[i]) {
+                        if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
+                            (cpu_devs[i]->c_ident[1] &&
+                            !strcmp(v, cpu_devs[i]->c_ident[1]))) {
+                                c->x86_vendor = i;
+                                this_cpu = cpu_devs[i];
+                                return;
+                        }
+                }
         }
-
-        if (cpu_has_ds) {
-                unsigned int l1, l2;
-                rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
-                if (!(l1 & (1<<11)))
-                        set_cpu_cap(c, X86_FEATURE_BTS);
-                if (!(l1 & (1<<12)))
-                        set_cpu_cap(c, X86_FEATURE_PEBS);
+        if (!printed) {
+                printed++;
+                printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
+                printk(KERN_ERR "CPU: Your system may be unstable.\n");
         }
-
-
-        if (cpu_has_bts)
-                ds_init_intel(c);
-
-        n = c->extended_cpuid_level;
-        if (n >= 0x80000008) {
-                unsigned eax = cpuid_eax(0x80000008);
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-                /* CPUID workaround for Intel 0F34 CPU */
-                if (c->x86_vendor == X86_VENDOR_INTEL &&
-                    c->x86 == 0xF && c->x86_model == 0x3 &&
-                    c->x86_mask == 0x4)
-                        c->x86_phys_bits = 36;
-        }
-
-        if (c->x86 == 15)
-                c->x86_cache_alignment = c->x86_clflush_size * 2;
-        if (c->x86 == 6)
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
-        c->x86_max_cores = intel_num_cpu_cores(c);
-
-        srat_detect_node();
-}
-
-static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
-{
-        if (c->x86 == 0x6 && c->x86_model >= 0xf)
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+        c->x86_vendor = X86_VENDOR_UNKNOWN;
 }
 
-static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
+static void __init early_cpu_support_print(void)
 {
-        /* Cache sizes */
-        unsigned n;
+        int i,j;
+        struct cpu_dev *cpu_devx;
 
-        n = c->extended_cpuid_level;
-        if (n >= 0x80000008) {
-                unsigned eax = cpuid_eax(0x80000008);
-                c->x86_virt_bits = (eax >> 8) & 0xff;
-                c->x86_phys_bits = eax & 0xff;
-        }
-
-        if (c->x86 == 0x6 && c->x86_model >= 0xf) {
-                c->x86_cache_alignment = c->x86_clflush_size * 2;
-                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        printk("KERNEL supported cpus:\n");
+        for (i = 0; i < X86_VENDOR_NUM; i++) {
+                cpu_devx = cpu_devs[i];
+                if (!cpu_devx)
+                        continue;
+                for (j = 0; j < 2; j++) {
+                        if (!cpu_devx->c_ident[j])
+                                continue;
+                        printk("  %s %s\n", cpu_devx->c_vendor,
+                                cpu_devx->c_ident[j]);
+                }
         }
-        set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 }
 
-static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
+static void __init early_cpu_init(void)
 {
-        char *v = c->x86_vendor_id;
+        struct cpu_vendor_dev *cvdev;
 
-        if (!strcmp(v, "AuthenticAMD"))
-                c->x86_vendor = X86_VENDOR_AMD;
-        else if (!strcmp(v, "GenuineIntel"))
-                c->x86_vendor = X86_VENDOR_INTEL;
-        else if (!strcmp(v, "CentaurHauls"))
-                c->x86_vendor = X86_VENDOR_CENTAUR;
-        else
-                c->x86_vendor = X86_VENDOR_UNKNOWN;
+        for (cvdev = __x86cpuvendor_start ;
+             cvdev < __x86cpuvendor_end   ;
+             cvdev++)
+                cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
+        early_cpu_support_print();
 }
 
 /* Do some early cpuid on the boot CPU to get some parameter that are
@@ -1066,17 +772,9 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
         if (c->extended_cpuid_level >= 0x80000007)
                 c->x86_power = cpuid_edx(0x80000007);
 
-        switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                early_init_amd(c);
-                break;
-        case X86_VENDOR_INTEL:
-                early_init_intel(c);
-                break;
-        case X86_VENDOR_CENTAUR:
-                early_init_centaur(c);
-                break;
-        }
+        if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
+            cpu_devs[c->x86_vendor]->c_early_init)
+                cpu_devs[c->x86_vendor]->c_early_init(c);
 
         validate_pat_support(c);
 }
@@ -1104,24 +802,8 @@ void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
          * At the end of this section, c->x86_capability better
          * indicate the features this CPU genuinely supports!
          */
-        switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                init_amd(c);
-                break;
-
-        case X86_VENDOR_INTEL:
-                init_intel(c);
-                break;
-
-        case X86_VENDOR_CENTAUR:
-                init_centaur(c);
-                break;
-
-        case X86_VENDOR_UNKNOWN:
-        default:
-                display_cacheinfo(c);
-                break;
-        }
+        if (this_cpu->c_init)
+                this_cpu->c_init(c);
 
         detect_ht(c);