diff options
Diffstat (limited to 'arch/x86/kernel/process.c')
| -rw-r--r-- | arch/x86/kernel/process.c | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 02d678065d7d..28ad9f4d8b94 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c | |||
| @@ -526,21 +526,37 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) | |||
| 526 | } | 526 | } |
| 527 | 527 | ||
| 528 | /* | 528 | /* |
| 529 | * Check for AMD CPUs, which have potentially C1E support | 529 | * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e. |
| 530 | * For more information see | ||
| 531 | * - Erratum #400 for NPT family 0xf and family 0x10 CPUs | ||
| 532 | * - Erratum #365 for family 0x11 (not affected because C1e not in use) | ||
| 530 | */ | 533 | */ |
| 531 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) | 534 | static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) |
| 532 | { | 535 | { |
| 536 | u64 val; | ||
| 533 | if (c->x86_vendor != X86_VENDOR_AMD) | 537 | if (c->x86_vendor != X86_VENDOR_AMD) |
| 534 | return 0; | 538 | goto no_c1e_idle; |
| 535 | |||
| 536 | if (c->x86 < 0x0F) | ||
| 537 | return 0; | ||
| 538 | 539 | ||
| 539 | /* Family 0x0f models < rev F do not have C1E */ | 540 | /* Family 0x0f models < rev F do not have C1E */ |
| 540 | if (c->x86 == 0x0f && c->x86_model < 0x40) | 541 | if (c->x86 == 0x0F && c->x86_model >= 0x40) |
| 541 | return 0; | 542 | return 1; |
| 542 | 543 | ||
| 543 | return 1; | 544 | if (c->x86 == 0x10) { |
| 545 | /* | ||
| 546 | * check OSVW bit for CPUs that are not affected | ||
| 547 | * by erratum #400 | ||
| 548 | */ | ||
| 549 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val); | ||
| 550 | if (val >= 2) { | ||
| 551 | rdmsrl(MSR_AMD64_OSVW_STATUS, val); | ||
| 552 | if (!(val & BIT(1))) | ||
| 553 | goto no_c1e_idle; | ||
| 554 | } | ||
| 555 | return 1; | ||
| 556 | } | ||
| 557 | |||
| 558 | no_c1e_idle: | ||
| 559 | return 0; | ||
| 544 | } | 560 | } |
| 545 | 561 | ||
| 546 | static cpumask_var_t c1e_mask; | 562 | static cpumask_var_t c1e_mask; |
| @@ -607,7 +623,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |||
| 607 | { | 623 | { |
| 608 | #ifdef CONFIG_SMP | 624 | #ifdef CONFIG_SMP |
| 609 | if (pm_idle == poll_idle && smp_num_siblings > 1) { | 625 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
| 610 | printk(KERN_WARNING "WARNING: polling idle and HT enabled," | 626 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
| 611 | " performance may degrade.\n"); | 627 | " performance may degrade.\n"); |
| 612 | } | 628 | } |
| 613 | #endif | 629 | #endif |
