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-rw-r--r--arch/x86/kernel/pci-gart_64.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 9739d5682093..508ef470b27f 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -45,15 +45,6 @@ static unsigned long iommu_pages; /* .. and in pages */
45 45
46static u32 *iommu_gatt_base; /* Remapping table */ 46static u32 *iommu_gatt_base; /* Remapping table */
47 47
48/*
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
54 */
55int iommu_fullflush = 1;
56
57/* Allocation bitmap for the remapping area: */ 48/* Allocation bitmap for the remapping area: */
58static DEFINE_SPINLOCK(iommu_bitmap_lock); 49static DEFINE_SPINLOCK(iommu_bitmap_lock);
59/* Guarded by iommu_bitmap_lock: */ 50/* Guarded by iommu_bitmap_lock: */
@@ -901,10 +892,6 @@ void __init gart_parse_options(char *p)
901#endif 892#endif
902 if (isdigit(*p) && get_option(&p, &arg)) 893 if (isdigit(*p) && get_option(&p, &arg))
903 iommu_size = arg; 894 iommu_size = arg;
904 if (!strncmp(p, "fullflush", 8))
905 iommu_fullflush = 1;
906 if (!strncmp(p, "nofullflush", 11))
907 iommu_fullflush = 0;
908 if (!strncmp(p, "noagp", 5)) 895 if (!strncmp(p, "noagp", 5))
909 no_agp = 1; 896 no_agp = 1;
910 if (!strncmp(p, "noaperture", 10)) 897 if (!strncmp(p, "noaperture", 10))