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-rw-r--r--arch/x86/kernel/pci-gart_64.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 65f6acb025c8..faf3229f8fb3 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -749,6 +749,15 @@ void __init gart_iommu_init(void)
749 */ 749 */
750 set_memory_np((unsigned long)__va(iommu_bus_base), 750 set_memory_np((unsigned long)__va(iommu_bus_base),
751 iommu_size >> PAGE_SHIFT); 751 iommu_size >> PAGE_SHIFT);
752 /*
753 * Tricky. The GART table remaps the physical memory range,
754 * so the CPU wont notice potential aliases and if the memory
755 * is remapped to UC later on, we might surprise the PCI devices
756 * with a stray writeout of a cacheline. So play it sure and
757 * do an explicit, full-scale wbinvd() _after_ having marked all
758 * the pages as Not-Present:
759 */
760 wbinvd();
752 761
753 /* 762 /*
754 * Try to workaround a bug (thanks to BenH) 763 * Try to workaround a bug (thanks to BenH)