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-rw-r--r--arch/x86/kernel/pci-dma.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 0a1408abcc62..d2f2c0158dc1 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -16,6 +16,15 @@ EXPORT_SYMBOL(dma_ops);
16 16
17static int iommu_sac_force __read_mostly; 17static int iommu_sac_force __read_mostly;
18 18
19/*
20 * If this is disabled the IOMMU will use an optimized flushing strategy
21 * of only flushing when an mapping is reused. With it true the GART is
22 * flushed for every mapping. Problem is that doing the lazy flush seems
23 * to trigger bugs with some popular PCI cards, in particular 3ware (but
24 * has been also also seen with Qlogic at least).
25 */
26int iommu_fullflush;
27
19#ifdef CONFIG_IOMMU_DEBUG 28#ifdef CONFIG_IOMMU_DEBUG
20int panic_on_overflow __read_mostly = 1; 29int panic_on_overflow __read_mostly = 1;
21int force_iommu __read_mostly = 1; 30int force_iommu __read_mostly = 1;
@@ -171,6 +180,10 @@ static __init int iommu_setup(char *p)
171 } 180 }
172 if (!strncmp(p, "nomerge", 7)) 181 if (!strncmp(p, "nomerge", 7))
173 iommu_merge = 0; 182 iommu_merge = 0;
183 if (!strncmp(p, "fullflush", 8))
184 iommu_fullflush = 1;
185 if (!strncmp(p, "nofullflush", 11))
186 iommu_fullflush = 0;
174 if (!strncmp(p, "forcesac", 8)) 187 if (!strncmp(p, "forcesac", 8))
175 iommu_sac_force = 1; 188 iommu_sac_force = 1;
176 if (!strncmp(p, "allowdac", 8)) 189 if (!strncmp(p, "allowdac", 8))