diff options
Diffstat (limited to 'arch/x86/kernel/irqinit_64.c')
| -rw-r--r-- | arch/x86/kernel/irqinit_64.c | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c index ff0235391285..8670b3ce626e 100644 --- a/arch/x86/kernel/irqinit_64.c +++ b/arch/x86/kernel/irqinit_64.c | |||
| @@ -24,41 +24,6 @@ | |||
| 24 | #include <asm/i8259.h> | 24 | #include <asm/i8259.h> |
| 25 | 25 | ||
| 26 | /* | 26 | /* |
| 27 | * Common place to define all x86 IRQ vectors | ||
| 28 | * | ||
| 29 | * This builds up the IRQ handler stubs using some ugly macros in irq.h | ||
| 30 | * | ||
| 31 | * These macros create the low-level assembly IRQ routines that save | ||
| 32 | * register context and call do_IRQ(). do_IRQ() then does all the | ||
| 33 | * operations that are needed to keep the AT (or SMP IOAPIC) | ||
| 34 | * interrupt-controller happy. | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define IRQ_NAME2(nr) nr##_interrupt(void) | ||
| 38 | #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) | ||
| 39 | |||
| 40 | /* | ||
| 41 | * SMP has a few special interrupts for IPI messages | ||
| 42 | */ | ||
| 43 | |||
| 44 | #define BUILD_IRQ(nr) \ | ||
| 45 | asmlinkage void IRQ_NAME(nr); \ | ||
| 46 | asm("\n.text\n.p2align\n" \ | ||
| 47 | "IRQ" #nr "_interrupt:\n\t" \ | ||
| 48 | "push $~(" #nr ") ; " \ | ||
| 49 | "jmp common_interrupt\n" \ | ||
| 50 | ".previous"); | ||
| 51 | |||
| 52 | #define BI(x,y) \ | ||
| 53 | BUILD_IRQ(x##y) | ||
| 54 | |||
| 55 | #define BUILD_16_IRQS(x) \ | ||
| 56 | BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ | ||
| 57 | BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ | ||
| 58 | BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ | ||
| 59 | BI(x,c) BI(x,d) BI(x,e) BI(x,f) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: | 27 | * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: |
| 63 | * (these are usually mapped to vectors 0x30-0x3f) | 28 | * (these are usually mapped to vectors 0x30-0x3f) |
| 64 | */ | 29 | */ |
| @@ -73,37 +38,6 @@ | |||
| 73 | * | 38 | * |
| 74 | * (these are usually mapped into the 0x30-0xff vector range) | 39 | * (these are usually mapped into the 0x30-0xff vector range) |
| 75 | */ | 40 | */ |
| 76 | BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) | ||
| 77 | BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) | ||
| 78 | BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) | ||
| 79 | BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf) | ||
| 80 | |||
| 81 | #undef BUILD_16_IRQS | ||
| 82 | #undef BI | ||
| 83 | |||
| 84 | |||
| 85 | #define IRQ(x,y) \ | ||
| 86 | IRQ##x##y##_interrupt | ||
| 87 | |||
| 88 | #define IRQLIST_16(x) \ | ||
| 89 | IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ | ||
| 90 | IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ | ||
| 91 | IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ | ||
| 92 | IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) | ||
| 93 | |||
| 94 | /* for the irq vectors */ | ||
| 95 | static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = { | ||
| 96 | IRQLIST_16(0x2), IRQLIST_16(0x3), | ||
| 97 | IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), | ||
| 98 | IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), | ||
| 99 | IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf) | ||
| 100 | }; | ||
| 101 | |||
| 102 | #undef IRQ | ||
| 103 | #undef IRQLIST_16 | ||
| 104 | |||
| 105 | |||
| 106 | |||
| 107 | 41 | ||
| 108 | /* | 42 | /* |
| 109 | * IRQ2 is cascade interrupt to second interrupt controller | 43 | * IRQ2 is cascade interrupt to second interrupt controller |
