diff options
Diffstat (limited to 'arch/x86/kernel/hpet.c')
-rw-r--r-- | arch/x86/kernel/hpet.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 3f0019e0a229..81408b93f887 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c | |||
@@ -236,6 +236,10 @@ static void hpet_stop_counter(void) | |||
236 | unsigned long cfg = hpet_readl(HPET_CFG); | 236 | unsigned long cfg = hpet_readl(HPET_CFG); |
237 | cfg &= ~HPET_CFG_ENABLE; | 237 | cfg &= ~HPET_CFG_ENABLE; |
238 | hpet_writel(cfg, HPET_CFG); | 238 | hpet_writel(cfg, HPET_CFG); |
239 | } | ||
240 | |||
241 | static void hpet_reset_counter(void) | ||
242 | { | ||
239 | hpet_writel(0, HPET_COUNTER); | 243 | hpet_writel(0, HPET_COUNTER); |
240 | hpet_writel(0, HPET_COUNTER + 4); | 244 | hpet_writel(0, HPET_COUNTER + 4); |
241 | } | 245 | } |
@@ -250,6 +254,7 @@ static void hpet_start_counter(void) | |||
250 | static void hpet_restart_counter(void) | 254 | static void hpet_restart_counter(void) |
251 | { | 255 | { |
252 | hpet_stop_counter(); | 256 | hpet_stop_counter(); |
257 | hpet_reset_counter(); | ||
253 | hpet_start_counter(); | 258 | hpet_start_counter(); |
254 | } | 259 | } |
255 | 260 | ||
@@ -309,7 +314,7 @@ static int hpet_setup_msi_irq(unsigned int irq); | |||
309 | static void hpet_set_mode(enum clock_event_mode mode, | 314 | static void hpet_set_mode(enum clock_event_mode mode, |
310 | struct clock_event_device *evt, int timer) | 315 | struct clock_event_device *evt, int timer) |
311 | { | 316 | { |
312 | unsigned long cfg; | 317 | unsigned long cfg, cmp, now; |
313 | uint64_t delta; | 318 | uint64_t delta; |
314 | 319 | ||
315 | switch (mode) { | 320 | switch (mode) { |
@@ -317,12 +322,23 @@ static void hpet_set_mode(enum clock_event_mode mode, | |||
317 | hpet_stop_counter(); | 322 | hpet_stop_counter(); |
318 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; | 323 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
319 | delta >>= evt->shift; | 324 | delta >>= evt->shift; |
325 | now = hpet_readl(HPET_COUNTER); | ||
326 | cmp = now + (unsigned long) delta; | ||
320 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | 327 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
321 | /* Make sure we use edge triggered interrupts */ | 328 | /* Make sure we use edge triggered interrupts */ |
322 | cfg &= ~HPET_TN_LEVEL; | 329 | cfg &= ~HPET_TN_LEVEL; |
323 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | 330 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
324 | HPET_TN_SETVAL | HPET_TN_32BIT; | 331 | HPET_TN_SETVAL | HPET_TN_32BIT; |
325 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | 332 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
333 | hpet_writel(cmp, HPET_Tn_CMP(timer)); | ||
334 | udelay(1); | ||
335 | /* | ||
336 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | ||
337 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | ||
338 | * bit is automatically cleared after the first write. | ||
339 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | ||
340 | * Publication # 24674) | ||
341 | */ | ||
326 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); | 342 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
327 | hpet_start_counter(); | 343 | hpet_start_counter(); |
328 | hpet_print_config(); | 344 | hpet_print_config(); |