7 files changed, 55 insertions, 23 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index eeee23ff75ef..68317c80de7f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -598,7 +598,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 {
         struct mce m;
         int i;
-        unsigned long *v;
 
         this_cpu_inc(mce_poll_count);
 
@@ -618,8 +617,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 if (!(m.status & MCI_STATUS_VAL))
                         continue;
 
-                v = &get_cpu_var(mce_polled_error);
-                set_bit(0, v);
+                this_cpu_write(mce_polled_error, 1);
                 /*
                  * Uncorrected or signalled events are handled by the exception
                  * handler when it is enabled, so don't process those here.
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 3bdb95ae8c43..9a316b21df8b 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -42,7 +42,7 @@ static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  * cmci_discover_lock protects against parallel discovery attempts
  * which could race against each other.
  */
-static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
+static DEFINE_SPINLOCK(cmci_discover_lock);
 
 #define CMCI_THRESHOLD          1
 #define CMCI_POLL_INTERVAL      (30 * HZ)
@@ -144,14 +144,14 @@ static void cmci_storm_disable_banks(void)
         int bank;
         u64 val;
 
-        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        spin_lock_irqsave(&cmci_discover_lock, flags);
         owned = __get_cpu_var(mce_banks_owned);
         for_each_set_bit(bank, owned, MAX_NR_BANKS) {
                 rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
                 val &= ~MCI_CTL2_CMCI_EN;
                 wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
         }
-        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+        spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
 static bool cmci_storm_detect(void)
@@ -211,7 +211,7 @@ static void cmci_discover(int banks)
         int i;
         int bios_wrong_thresh = 0;
 
-        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        spin_lock_irqsave(&cmci_discover_lock, flags);
         for (i = 0; i < banks; i++) {
                 u64 val;
                 int bios_zero_thresh = 0;
@@ -266,7 +266,7 @@ static void cmci_discover(int banks)
                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
                 }
         }
-        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+        spin_unlock_irqrestore(&cmci_discover_lock, flags);
         if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
                 pr_info_once(
                         "bios_cmci_threshold: Some banks do not have valid thresholds set\n");
@@ -316,10 +316,10 @@ void cmci_clear(void)
 
         if (!cmci_supported(&banks))
                 return;
-        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        spin_lock_irqsave(&cmci_discover_lock, flags);
         for (i = 0; i < banks; i++)
                 __cmci_disable_bank(i);
-        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+        spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
 static void cmci_rediscover_work_func(void *arg)
@@ -360,9 +360,9 @@ void cmci_disable_bank(int bank)
         if (!cmci_supported(&banks))
                 return;
 
-        raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+        spin_lock_irqsave(&cmci_discover_lock, flags);
         __cmci_disable_bank(bank);
-        raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+        spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
 static void intel_init_cmci(void)
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index d921b7ee6595..36a1bb6d1ee0 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -429,14 +429,14 @@ static inline void __smp_thermal_interrupt(void)
         smp_thermal_vector();
 }
 
-asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
+asmlinkage __visible void smp_thermal_interrupt(struct pt_regs *regs)
 {
         entering_irq();
         __smp_thermal_interrupt();
         exiting_ack_irq();
 }
 
-asmlinkage void smp_trace_thermal_interrupt(struct pt_regs *regs)
+asmlinkage __visible void smp_trace_thermal_interrupt(struct pt_regs *regs)
 {
         entering_irq();
         trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
diff --git a/arch/x86/kernel/cpu/mcheck/threshold.c b/arch/x86/kernel/cpu/mcheck/threshold.c
index fe6b1c86645b..7245980186ee 100644
--- a/arch/x86/kernel/cpu/mcheck/threshold.c
+++ b/arch/x86/kernel/cpu/mcheck/threshold.c
@@ -24,14 +24,14 @@ static inline void __smp_threshold_interrupt(void)
         mce_threshold_vector();
 }
 
-asmlinkage void smp_threshold_interrupt(void)
+asmlinkage __visible void smp_threshold_interrupt(void)
 {
         entering_irq();
         __smp_threshold_interrupt();
         exiting_ack_irq();
 }
 
-asmlinkage void smp_trace_threshold_interrupt(void)
+asmlinkage __visible void smp_trace_threshold_interrupt(void)
 {
         entering_irq();
         trace_threshold_apic_entry(THRESHOLD_APIC_VECTOR);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index aa333d966886..adb02aa62af5 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -169,7 +169,6 @@ static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 {
         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-        FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
         EVENT_CONSTRAINT_END
 };
diff --git a/arch/x86/kernel/cpu/perf_event_intel_rapl.c b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
index 059218ed5208..619f7699487a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_rapl.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_rapl.c
@@ -59,7 +59,7 @@
 #define INTEL_RAPL_PKG          0x2     /* pseudo-encoding */
 #define RAPL_IDX_RAM_NRG_STAT   2       /* DRAM */
 #define INTEL_RAPL_RAM          0x3     /* pseudo-encoding */
-#define RAPL_IDX_PP1_NRG_STAT   3       /* DRAM */
+#define RAPL_IDX_PP1_NRG_STAT   3       /* gpu */
 #define INTEL_RAPL_PP1          0x4     /* pseudo-encoding */
 
 /* Clients have PP0, PKG */
@@ -72,6 +72,12 @@
                          1<<RAPL_IDX_PKG_NRG_STAT|\
                          1<<RAPL_IDX_RAM_NRG_STAT)
 
+/* Servers have PP0, PKG, RAM, PP1 */
+#define RAPL_IDX_HSW    (1<<RAPL_IDX_PP0_NRG_STAT|\
+                         1<<RAPL_IDX_PKG_NRG_STAT|\
+                         1<<RAPL_IDX_RAM_NRG_STAT|\
+                         1<<RAPL_IDX_PP1_NRG_STAT)
+
 /*
  * event code: LSB 8 bits, passed in attr->config
  * any other bit is reserved
@@ -425,6 +431,24 @@ static struct attribute *rapl_events_cln_attr[] = {
         NULL,
 };
 
+static struct attribute *rapl_events_hsw_attr[] = {
+        EVENT_PTR(rapl_cores),
+        EVENT_PTR(rapl_pkg),
+        EVENT_PTR(rapl_gpu),
+        EVENT_PTR(rapl_ram),
+
+        EVENT_PTR(rapl_cores_unit),
+        EVENT_PTR(rapl_pkg_unit),
+        EVENT_PTR(rapl_gpu_unit),
+        EVENT_PTR(rapl_ram_unit),
+
+        EVENT_PTR(rapl_cores_scale),
+        EVENT_PTR(rapl_pkg_scale),
+        EVENT_PTR(rapl_gpu_scale),
+        EVENT_PTR(rapl_ram_scale),
+        NULL,
+};
+
 static struct attribute_group rapl_pmu_events_group = {
         .name = "events",
         .attrs = NULL, /* patched at runtime */
@@ -511,6 +535,7 @@ static int rapl_cpu_prepare(int cpu)
         struct rapl_pmu *pmu = per_cpu(rapl_pmu, cpu);
         int phys_id = topology_physical_package_id(cpu);
         u64 ms;
+        u64 msr_rapl_power_unit_bits;
 
         if (pmu)
                 return 0;
@@ -518,6 +543,10 @@ static int rapl_cpu_prepare(int cpu)
         if (phys_id < 0)
                 return -1;
 
+        /* protect rdmsrl() to handle virtualization */
+        if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits))
+                return -1;
+
         pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu));
         if (!pmu)
                 return -1;
@@ -531,8 +560,7 @@ static int rapl_cpu_prepare(int cpu)
          *
          * we cache in local PMU instance
          */
-        rdmsrl(MSR_RAPL_POWER_UNIT, pmu->hw_unit);
-        pmu->hw_unit = (pmu->hw_unit >> 8) & 0x1FULL;
+        pmu->hw_unit = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
         pmu->pmu = &rapl_pmu_class;
 
         /*
@@ -631,11 +659,14 @@ static int __init rapl_pmu_init(void)
         switch (boot_cpu_data.x86_model) {
         case 42: /* Sandy Bridge */
         case 58: /* Ivy Bridge */
-        case 60: /* Haswell */
-        case 69: /* Haswell-Celeron */
                 rapl_cntr_mask = RAPL_IDX_CLN;
                 rapl_pmu_events_group.attrs = rapl_events_cln_attr;
                 break;
+        case 60: /* Haswell */
+        case 69: /* Haswell-Celeron */
+                rapl_cntr_mask = RAPL_IDX_HSW;
+                rapl_pmu_events_group.attrs = rapl_events_hsw_attr;
+                break;
         case 45: /* Sandy Bridge-EP */
         case 62: /* IvyTown */
                 rapl_cntr_mask = RAPL_IDX_SRV;
@@ -650,7 +681,9 @@ static int __init rapl_pmu_init(void)
         cpu_notifier_register_begin();
 
         for_each_online_cpu(cpu) {
-                rapl_cpu_prepare(cpu);
+                ret = rapl_cpu_prepare(cpu);
+                if (ret)
+                        goto out;
                 rapl_cpu_init(cpu);
         }
 
@@ -673,6 +706,7 @@ static int __init rapl_pmu_init(void)
                 hweight32(rapl_cntr_mask),
                 ktime_to_ms(pmu->timer_interval));
 
+out:
         cpu_notifier_register_done();
 
         return 0;
diff --git a/arch/x86/kernel/cpu/rdrand.c b/arch/x86/kernel/cpu/rdrand.c
index 384df5105fbc..136ac74dee82 100644
--- a/arch/x86/kernel/cpu/rdrand.c
+++ b/arch/x86/kernel/cpu/rdrand.c
@@ -27,6 +27,7 @@
 static int __init x86_rdrand_setup(char *s)
 {
         setup_clear_cpu_cap(X86_FEATURE_RDRAND);
+        setup_clear_cpu_cap(X86_FEATURE_RDSEED);
         return 1;
 }
 __setup("nordrand", x86_rdrand_setup);