16 files changed, 195 insertions, 74 deletions

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 84a8220a6072..a6ef672adbba 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -56,9 +56,22 @@ void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
 
         switch (c->x86_vendor) {
         case X86_VENDOR_INTEL:
-                if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
+                /*
+                 * There is a known erratum on Pentium III and Core Solo
+                 * and Core Duo CPUs.
+                 * " Page with PAT set to WC while associated MTRR is UC
+                 *   may consolidate to UC "
+                 * Because of this erratum, it is better to stick with
+                 * setting WC in MTRR rather than using PAT on these CPUs.
+                 *
+                 * Enable PAT WC only on P4, Core 2 or later CPUs.
+                 */
+                if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
                         return;
-                break;
+
+                pat_disable("PAT WC disabled due to known CPU erratum.");
+                return;
+
         case X86_VENDOR_AMD:
         case X86_VENDOR_CENTAUR:
         case X86_VENDOR_TRANSMETA:
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index cae9cabc3031..18514ed26104 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -31,6 +31,11 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
                 if (c->x86_power & (1<<8))
                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
         }
+
+        /*  Set MTRR capability flag if appropriate */
+        if (c->x86_model == 13 || c->x86_model == 9 ||
+           (c->x86_model == 8 && c->x86_mask >= 8))
+                set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 }
 
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
@@ -166,10 +171,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                                                 mbytes);
                                 }
 
-                                /*  Set MTRR capability flag if appropriate */
-                                if (c->x86_model == 13 || c->x86_model == 9 ||
-                                   (c->x86_model == 8 && c->x86_mask >= 8))
-                                        set_cpu_cap(c, X86_FEATURE_K6_MTRR);
                                 break;
                         }
 
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c9b58a806e85..c8e315f1aa83 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -50,6 +50,8 @@ static double __initdata y = 3145727.0;
  */
 static void __init check_fpu(void)
 {
+        s32 fdiv_bug;
+
         if (!boot_cpu_data.hard_math) {
 #ifndef CONFIG_MATH_EMULATION
                 printk(KERN_EMERG "No coprocessor found and no math emulation present.\n");
@@ -74,8 +76,10 @@ static void __init check_fpu(void)
                 "fistpl %0\n\t"
                 "fwait\n\t"
                 "fninit"
-                : "=m" (*&boot_cpu_data.fdiv_bug)
+                : "=m" (*&fdiv_bug)
                 : "m" (*&x), "m" (*&y));
+
+        boot_cpu_data.fdiv_bug = fdiv_bug;
         if (boot_cpu_data.fdiv_bug)
                 printk("Hmm, FPU with FDIV bug.\n");
 }
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index e0f45edd6a55..a0534c04d38a 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -314,6 +314,16 @@ enum {
                 EAMD3D          = 1<<20,
 };
 
+static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
+{
+        switch (c->x86) {
+        case 5:
+                /* Emulate MTRRs using Centaur's MCR. */
+                set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
+                break;
+        }
+}
+
 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
 {
 
@@ -462,6 +472,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
         .c_vendor       = "Centaur",
         .c_ident        = { "CentaurHauls" },
+        .c_early_init   = early_init_centaur,
         .c_init         = init_centaur,
         .c_size_cache   = centaur_size_cache,
 };
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 80ab20d4fa39..8aab8517642e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -13,6 +13,7 @@
 #include <asm/mtrr.h>
 #include <asm/mce.h>
 #include <asm/pat.h>
+#include <asm/asm.h>
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
@@ -334,11 +335,40 @@ static void __init early_cpu_detect(void)
 
         get_cpu_vendor(c, 1);
 
+        early_get_cap(c);
+
         if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
             cpu_devs[c->x86_vendor]->c_early_init)
                 cpu_devs[c->x86_vendor]->c_early_init(c);
+}
 
-        early_get_cap(c);
+/*
+ * The NOPL instruction is supposed to exist on all CPUs with
+ * family >= 6, unfortunately, that's not true in practice because
+ * of early VIA chips and (more importantly) broken virtualizers that
+ * are not easy to detect.  Hence, probe for it based on first
+ * principles.
+ */
+static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
+{
+        const u32 nopl_signature = 0x888c53b1; /* Random number */
+        u32 has_nopl = nopl_signature;
+
+        clear_cpu_cap(c, X86_FEATURE_NOPL);
+        if (c->x86 >= 6) {
+                asm volatile("\n"
+                             "1:      .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
+                             "2:\n"
+                             "        .section .fixup,\"ax\"\n"
+                             "3:      xor %0,%0\n"
+                             "        jmp 2b\n"
+                             "        .previous\n"
+                             _ASM_EXTABLE(1b,3b)
+                             : "+a" (has_nopl));
+
+                if (has_nopl == nopl_signature)
+                        set_cpu_cap(c, X86_FEATURE_NOPL);
+        }
 }
 
 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
@@ -395,8 +425,8 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
                 }
 
                 init_scattered_cpuid_features(c);
+                detect_nopl(c);
         }
-
 }
 
 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/common_64.c b/arch/x86/kernel/cpu/common_64.c
index dd6e3f15017e..a11f5d4477cd 100644
--- a/arch/x86/kernel/cpu/common_64.c
+++ b/arch/x86/kernel/cpu/common_64.c
@@ -18,6 +18,7 @@
 #include <asm/mtrr.h>
 #include <asm/mce.h>
 #include <asm/pat.h>
+#include <asm/asm.h>
 #include <asm/numa.h>
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
@@ -215,6 +216,39 @@ static void __init early_cpu_support_print(void)
         }
 }
 
+/*
+ * The NOPL instruction is supposed to exist on all CPUs with
+ * family >= 6, unfortunately, that's not true in practice because
+ * of early VIA chips and (more importantly) broken virtualizers that
+ * are not easy to detect.  Hence, probe for it based on first
+ * principles.
+ *
+ * Note: no 64-bit chip is known to lack these, but put the code here
+ * for consistency with 32 bits, and to make it utterly trivial to
+ * diagnose the problem should it ever surface.
+ */
+static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
+{
+        const u32 nopl_signature = 0x888c53b1; /* Random number */
+        u32 has_nopl = nopl_signature;
+
+        clear_cpu_cap(c, X86_FEATURE_NOPL);
+        if (c->x86 >= 6) {
+                asm volatile("\n"
+                             "1:      .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
+                             "2:\n"
+                             "        .section .fixup,\"ax\"\n"
+                             "3:      xor %0,%0\n"
+                             "        jmp 2b\n"
+                             "        .previous\n"
+                             _ASM_EXTABLE(1b,3b)
+                             : "+a" (has_nopl));
+
+                if (has_nopl == nopl_signature)
+                        set_cpu_cap(c, X86_FEATURE_NOPL);
+        }
+}
+
 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 
 void __init early_cpu_init(void)
@@ -313,6 +347,8 @@ static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
                 c->x86_phys_bits = eax & 0xff;
         }
 
+        detect_nopl(c);
+
         if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
             cpu_devs[c->x86_vendor]->c_early_init)
                 cpu_devs[c->x86_vendor]->c_early_init(c);
@@ -493,17 +529,20 @@ void pda_init(int cpu)
                 /* others are initialized in smpboot.c */
                 pda->pcurrent = &init_task;
                 pda->irqstackptr = boot_cpu_stack;
+                pda->irqstackptr += IRQSTACKSIZE - 64;
         } else {
-                pda->irqstackptr = (char *)
-                        __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
-                if (!pda->irqstackptr)
-                        panic("cannot allocate irqstack for cpu %d", cpu);
+                if (!pda->irqstackptr) {
+                        pda->irqstackptr = (char *)
+                                __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
+                        if (!pda->irqstackptr)
+                                panic("cannot allocate irqstack for cpu %d",
+                                      cpu);
+                        pda->irqstackptr += IRQSTACKSIZE - 64;
+                }
 
                 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
                         pda->nodenumber = cpu_to_node(cpu);
         }
-
-        pda->irqstackptr += IRQSTACKSIZE-64;
 }
 
 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
@@ -601,19 +640,22 @@ void __cpuinit cpu_init(void)
         /*
          * set up and load the per-CPU TSS
          */
-        for (v = 0; v < N_EXCEPTION_STACKS; v++) {
+        if (!orig_ist->ist[0]) {
                 static const unsigned int order[N_EXCEPTION_STACKS] = {
-                        [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
-                        [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
+                  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
+                  [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
                 };
-                if (cpu) {
-                        estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
-                        if (!estacks)
-                                panic("Cannot allocate exception stack %ld %d\n",
-                                      v, cpu);
+                for (v = 0; v < N_EXCEPTION_STACKS; v++) {
+                        if (cpu) {
+                                estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
+                                if (!estacks)
+                                        panic("Cannot allocate exception "
+                                              "stack %ld %d\n", v, cpu);
+                        }
+                        estacks += PAGE_SIZE << order[v];
+                        orig_ist->ist[v] = t->x86_tss.ist[v] =
+                                        (unsigned long)estacks;
                 }
-                estacks += PAGE_SIZE << order[v];
-                orig_ist->ist[v] = t->x86_tss.ist[v] = (unsigned long)estacks;
         }
 
         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig
index cb7a5715596d..efae3b22a0ff 100644
--- a/arch/x86/kernel/cpu/cpufreq/Kconfig
+++ b/arch/x86/kernel/cpu/cpufreq/Kconfig
@@ -235,9 +235,9 @@ config X86_LONGHAUL
           If in doubt, say N.
 
 config X86_E_POWERSAVER
-        tristate "VIA C7 Enhanced PowerSaver (EXPERIMENTAL)"
+        tristate "VIA C7 Enhanced PowerSaver"
         select CPU_FREQ_TABLE
-        depends on X86_32 && EXPERIMENTAL
+        depends on X86_32
         help
           This adds the CPUFreq driver for VIA C7 processors.
 
diff --git a/arch/x86/kernel/cpu/cpufreq/elanfreq.c b/arch/x86/kernel/cpu/cpufreq/elanfreq.c
index 94619c22f563..e4a4bf870e94 100644
--- a/arch/x86/kernel/cpu/cpufreq/elanfreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/elanfreq.c
@@ -44,7 +44,7 @@ struct s_elan_multiplier {
  * It is important that the frequencies
  * are listed in ascending order here!
  */
-struct s_elan_multiplier elan_multiplier[] = {
+static struct s_elan_multiplier elan_multiplier[] = {
         {1000,  0x02,   0x18},
         {2000,  0x02,   0x10},
         {4000,  0x02,   0x08},
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index c45ca6d4dce1..84bb395038d8 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -66,7 +66,6 @@ static u32 find_freq_from_fid(u32 fid)
         return 800 + (fid * 100);
 }
 
-
 /* Return a frequency in KHz, given an input fid */
 static u32 find_khz_freq_from_fid(u32 fid)
 {
@@ -78,7 +77,6 @@ static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, u32 p
         return data[pstate].frequency;
 }
 
-
 /* Return the vco fid for an input fid
  *
  * Each "low" fid has corresponding "high" fid, and you can get to "low" fids
@@ -166,7 +164,6 @@ static void fidvid_msr_init(void)
         wrmsr(MSR_FIDVID_CTL, lo, hi);
 }
 
-
 /* write the new fid value along with the other control fields to the msr */
 static int write_new_fid(struct powernow_k8_data *data, u32 fid)
 {
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 3fd7a67bb06a..898a5a2002ed 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -15,13 +15,11 @@
 /*
  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  */
-static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
+static void __cpuinit __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
 {
         unsigned char ccr2, ccr3;
-        unsigned long flags;
 
         /* we test for DEVID by checking whether CCR3 is writable */
-        local_irq_save(flags);
         ccr3 = getCx86(CX86_CCR3);
         setCx86(CX86_CCR3, ccr3 ^ 0x80);
         getCx86(0xc0);   /* dummy to change bus */
@@ -44,9 +42,16 @@ static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
                 *dir0 = getCx86(CX86_DIR0);
                 *dir1 = getCx86(CX86_DIR1);
         }
-        local_irq_restore(flags);
 }
 
+static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        __do_cyrix_devid(dir0, dir1);
+        local_irq_restore(flags);
+}
 /*
  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
  * order to identify the Cyrix CPU model after we're out of setup.c
@@ -134,23 +139,6 @@ static void __cpuinit set_cx86_memwb(void)
         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
 }
 
-static void __cpuinit set_cx86_inc(void)
-{
-        unsigned char ccr3;
-
-        printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
-
-        ccr3 = getCx86(CX86_CCR3);
-        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
-        /* PCR1 -- Performance Control */
-        /* Incrementor on, whatever that is */
-        setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
-        /* PCR0 -- Performance Control */
-        /* Incrementor Margin 10 */
-        setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
-        setCx86(CX86_CCR3, ccr3);       /* disable MAPEN */
-}
-
 /*
  *      Configure later MediaGX and/or Geode processor.
  */
@@ -174,11 +162,28 @@ static void __cpuinit geode_configure(void)
 
         set_cx86_memwb();
         set_cx86_reorder();
-        set_cx86_inc();
 
         local_irq_restore(flags);
 }
 
+static void __cpuinit early_init_cyrix(struct cpuinfo_x86 *c)
+{
+        unsigned char dir0, dir0_msn, dir1 = 0;
+
+        __do_cyrix_devid(&dir0, &dir1);
+        dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
+
+        switch (dir0_msn) {
+        case 3: /* 6x86/6x86L */
+                /* Emulate MTRRs using Cyrix's ARRs. */
+                set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
+                break;
+        case 5: /* 6x86MX/M II */
+                /* Emulate MTRRs using Cyrix's ARRs. */
+                set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
+                break;
+        }
+}
 
 static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
 {
@@ -434,6 +439,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
 static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
         .c_vendor       = "Cyrix",
         .c_ident        = { "CyrixInstead" },
+        .c_early_init   = early_init_cyrix,
         .c_init         = init_cyrix,
         .c_identify     = cyrix_identify,
 };
diff --git a/arch/x86/kernel/cpu/feature_names.c b/arch/x86/kernel/cpu/feature_names.c
index e43ad4ad4cba..c9017799497c 100644
--- a/arch/x86/kernel/cpu/feature_names.c
+++ b/arch/x86/kernel/cpu/feature_names.c
@@ -39,7 +39,8 @@ const char * const x86_cap_flags[NCAPINTS*32] = {
         NULL, NULL, NULL, NULL,
         "constant_tsc", "up", NULL, "arch_perfmon",
         "pebs", "bts", NULL, NULL,
-        "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+        "rep_good", NULL, NULL, NULL,
+        "nopl", NULL, NULL, NULL,
         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 
         /* Intel-defined (#2) */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index 65a339678ece..726a5fcdf341 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -759,6 +759,7 @@ static struct sysdev_class mce_sysclass = {
 };
 
 DEFINE_PER_CPU(struct sys_device, device_mce);
+void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu) __cpuinitdata;
 
 /* Why are there no generic functions for this? */
 #define ACCESSOR(name, var, start) \
@@ -883,9 +884,13 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb,
         case CPU_ONLINE:
         case CPU_ONLINE_FROZEN:
                 mce_create_device(cpu);
+                if (threshold_cpu_callback)
+                        threshold_cpu_callback(action, cpu);
                 break;
         case CPU_DEAD:
         case CPU_DEAD_FROZEN:
+                if (threshold_cpu_callback)
+                        threshold_cpu_callback(action, cpu);
                 mce_remove_device(cpu);
                 break;
         }
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 88736cadbaa6..5eb390a4b2e9 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -628,6 +628,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
         deallocate_threshold_block(cpu, bank);
 
 free_out:
+        kobject_del(b->kobj);
         kobject_put(b->kobj);
         kfree(b);
         per_cpu(threshold_banks, cpu)[bank] = NULL;
@@ -645,14 +646,11 @@ static void threshold_remove_device(unsigned int cpu)
 }
 
 /* get notified when a cpu comes on/off */
-static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
-                                            unsigned long action, void *hcpu)
+static void __cpuinit amd_64_threshold_cpu_callback(unsigned long action,
+                                                     unsigned int cpu)
 {
-        /* cpu was unsigned int to begin with */
-        unsigned int cpu = (unsigned long)hcpu;
-
         if (cpu >= NR_CPUS)
-                goto out;
+                return;
 
         switch (action) {
         case CPU_ONLINE:
@@ -666,14 +664,8 @@ static int __cpuinit threshold_cpu_callback(struct notifier_block *nfb,
         default:
                 break;
         }
-      out:
-        return NOTIFY_OK;
 }
 
-static struct notifier_block threshold_cpu_notifier __cpuinitdata = {
-        .notifier_call = threshold_cpu_callback,
-};
-
 static __init int threshold_init_device(void)
 {
         unsigned lcpu = 0;
@@ -684,7 +676,7 @@ static __init int threshold_init_device(void)
                 if (err)
                         return err;
         }
-        register_hotcpu_notifier(&threshold_cpu_notifier);
+        threshold_cpu_callback = amd_64_threshold_cpu_callback;
         return 0;
 }
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 509bd3d9eacd..cb7d3b6a80eb 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -379,6 +379,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
                              unsigned long *size, mtrr_type *type)
 {
         unsigned int mask_lo, mask_hi, base_lo, base_hi;
+        unsigned int tmp, hi;
 
         rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
         if ((mask_lo & 0x800) == 0) {
@@ -392,8 +393,23 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 
         /* Work out the shifted address mask. */
-        mask_lo = size_or_mask | mask_hi << (32 - PAGE_SHIFT)
-            | mask_lo >> PAGE_SHIFT;
+        tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
+        mask_lo = size_or_mask | tmp;
+        /* Expand tmp with high bits to all 1s*/
+        hi = fls(tmp);
+        if (hi > 0) {
+                tmp |= ~((1<<(hi - 1)) - 1);
+
+                if (tmp != mask_lo) {
+                        static int once = 1;
+
+                        if (once) {
+                                printk(KERN_INFO "mtrr: your BIOS has set up an incorrect mask, fixing it up.\n");
+                                once = 0;
+                        }
+                        mask_lo = tmp;
+                }
+        }
 
         /* This works correctly if size is a power of two, i.e. a
            contiguous range. */
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 6f23969c8faf..b117d7f8a564 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -1496,11 +1496,8 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
 
         /* kvm/qemu doesn't have mtrr set right, don't trim them all */
         if (!highest_pfn) {
-                if (!kvm_para_available()) {
-                        printk(KERN_WARNING
+                WARN(!kvm_para_available(), KERN_WARNING
                                 "WARNING: strange, CPU MTRRs all blank?\n");
-                        WARN_ON(1);
-                }
                 return 0;
         }
 
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index de7439f82b92..05cc22dbd4ff 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -478,7 +478,13 @@ static int setup_p4_watchdog(unsigned nmi_hz)
                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
                 evntsel_msr = MSR_P4_CRU_ESCR0;
                 cccr_msr = MSR_P4_IQ_CCCR1;
-                cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
+
+                /* Pentium 4 D processors don't support P4_CCCR_OVF_PMI1 */
+                if (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask == 4)
+                        cccr_val = P4_CCCR_OVF_PMI0;
+                else
+                        cccr_val = P4_CCCR_OVF_PMI1;
+                cccr_val |= P4_CCCR_ESCR_SELECT(4);
         }
 
         evntsel = P4_ESCR_EVENT_SELECT(0x3F)