12 files changed, 22 insertions, 22 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 5f8af875f457..1ff88c7f45cf 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -266,7 +266,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_HT
         /*
          * On a AMD multi core setup the lower bits of the APIC id
-         * distingush the cores.
+         * distinguish the cores.
          */
         if (c->x86_max_cores > 1) {
                 int cpu = smp_processor_id();
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 473eac883c7b..9681fa15ddf0 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -53,7 +53,7 @@ static u32 __cpuinit ramtop(void)		/* 16388 */
                         continue;
                 /*
                  *      Don't MCR over reserved space. Ignore the ISA hole
-                 *      we frob around that catastrophy already
+                 *      we frob around that catastrophe already
                  */
                                         
                 if (e820.map[i].type == E820_RESERVED)
@@ -287,7 +287,7 @@ static void __cpuinit init_c3(struct cpuinfo_x86 *c)
                 c->x86_capability[5] = cpuid_edx(0xC0000001);
         }
 
-        /* Cyrix III family needs CX8 & PGE explicity enabled. */
+        /* Cyrix III family needs CX8 & PGE explicitly enabled. */
         if (c->x86_model >=6 && c->x86_model <= 9) {
                 rdmsr (MSR_VIA_FCR, lo, hi);
                 lo |= (1<<1 | 1<<7);
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d506201d397c..e2fcf2051bdb 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -207,7 +207,7 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
 
 static int __init x86_fxsr_setup(char * s)
 {
-        /* Tell all the other CPU's to not use it... */
+        /* Tell all the other CPUs to not use it... */
         disable_x86_fxsr = 1;
 
         /*
diff --git a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c b/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
index 32f0bda3fc95..f03e9153618e 100644
--- a/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/arch/x86/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@ -260,7 +260,7 @@ static int nforce2_target(struct cpufreq_policy *policy,
 
         freqs.old = nforce2_get(policy->cpu);
         freqs.new = target_fsb * fid * 100;
-        freqs.cpu = 0;          /* Only one CPU on nForce2 plattforms */
+        freqs.cpu = 0;          /* Only one CPU on nForce2 platforms */
 
         if (freqs.old == freqs.new)
                 return 0;
diff --git a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c b/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
index ed2bda127c44..2ed7db2fd257 100644
--- a/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/gx-suspmod.c
@@ -12,12 +12,12 @@
  *      of any nature resulting due to the use of this software. This
  *      software is provided AS-IS with no warranties.
  *
- * Theoritical note:
+ * Theoretical note:
  *
  *      (see Geode(tm) CS5530 manual (rev.4.1) page.56)
  *
  *      CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
- *      are based on Suspend Moduration.
+ *      are based on Suspend Modulation.
  *
  *      Suspend Modulation works by asserting and de-asserting the SUSP# pin
  *      to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
@@ -101,11 +101,11 @@
 
 /* SUSCFG bits */
 #define SUSMOD          (1<<0)  /* enable/disable suspend modulation */
-/* the belows support only with cs5530 (after rev.1.2)/cs5530A */
+/* the below is supported only with cs5530 (after rev.1.2)/cs5530A */
 #define SMISPDUP        (1<<1)  /* select how SMI re-enable suspend modulation: */
                                 /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
 #define SUSCFG          (1<<2)  /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
-/* the belows support only with cs5530A */
+/* the below is supported only with cs5530A */
 #define PWRSVE_ISA      (1<<3)  /* stop ISA clock  */
 #define PWRSVE          (1<<4)  /* active idle */
 
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
index 42405b4e34ed..eb9b62b0830c 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k6.c
@@ -1,6 +1,6 @@
 /*
  *  This file was based upon code in Powertweak Linux (http://powertweak.sf.net)
- *  (C) 2000-2003  Dave Jones, Arjan van de Ven, Janne Pänkälä, Dominik Brodowski.
+ *  (C) 2000-2003  Dave Jones, Arjan van de Ven, Janne Pänkälä, Dominik Brodowski.
  *
  *  Licensed under the terms of the GNU GPL License version 2.
  *
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index c06ac680c9ca..9c36a53676b7 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -168,7 +168,7 @@ static void count_off_irt(struct powernow_k8_data *data)
         return;
 }
 
-/* the voltage stabalization time */
+/* the voltage stabilization time */
 static void count_off_vst(struct powernow_k8_data *data)
 {
         udelay(data->vstable * VST_UNITS_20US);
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index b06c812208ca..7c4f6e0faed4 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -148,10 +148,10 @@ struct powernow_k8_data {
 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
 
 #define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
-#define VST_UNITS_20US 20   /* Voltage Stabalization Time is in units of 20us */
+#define VST_UNITS_20US 20   /* Voltage Stabilization Time is in units of 20us */
 
 /*
- * Most values of interest are enocoded in a single field of the _PSS
+ * Most values of interest are encoded in a single field of the _PSS
  * entries: the "control" value.
  */
 
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 122d2d75aa9f..88d66fb8411d 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -93,7 +93,7 @@ static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
 
                 local_irq_save(flags);
                 ccr3 = getCx86(CX86_CCR3);
-                setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
+                setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
                 ccr5 = getCx86(CX86_CCR5);
                 if (ccr5 & 2)
                         setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
@@ -115,9 +115,9 @@ static void __cpuinit set_cx86_reorder(void)
 
         printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
         ccr3 = getCx86(CX86_CCR3);
-        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
+        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
 
-        /* Load/Store Serialize to mem access disable (=reorder it)  */
+        /* Load/Store Serialize to mem access disable (=reorder it) */
         setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
         /* set load/store serialize from 1GB to 4GB */
         ccr3 |= 0xe0;
@@ -146,7 +146,7 @@ static void __cpuinit set_cx86_inc(void)
         printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
 
         ccr3 = getCx86(CX86_CCR3);
-        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
+        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
         /* PCR1 -- Performance Control */
         /* Incrementor on, whatever that is */
         setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
@@ -256,7 +256,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 u32 vendor, device;
                 /* It isn't really a PCI quirk directly, but the cure is the
                    same. The MediaGX has deep magic SMM stuff that handles the
-                   SB emulation. It thows away the fifo on disable_dma() which
+                   SB emulation. It throws away the fifo on disable_dma() which
                    is wrong and ruins the audio. 
 
                    Bug2: VSA1 has a wrap bug so that using maximum sized DMA 
diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c
index 2287d4863a8a..9964be3de2b7 100644
--- a/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ b/arch/x86/kernel/cpu/mtrr/cyrix.c
@@ -147,10 +147,10 @@ static void prepare_set(void)
         write_cr0(cr0);
         wbinvd();
 
-        /* Cyrix ARRs - everything else were excluded at the top */
+        /* Cyrix ARRs - everything else was excluded at the top */
         ccr3 = getCx86(CX86_CCR3);
 
-        /* Cyrix ARRs - everything else were excluded at the top */
+        /* Cyrix ARRs - everything else was excluded at the top */
         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
 
 }
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 56f64e34829f..992f08dfbb6c 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -182,7 +182,7 @@ static inline void k8_enable_fixed_iorrs(void)
 
 /**
  * Checks and updates an fixed-range MTRR if it differs from the value it
- * should have. If K8 extenstions are wanted, update the K8 SYSCFG MSR also.
+ * should have. If K8 extentions are wanted, update the K8 SYSCFG MSR also.
  * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information
  * \param msr MSR address of the MTTR which should be checked and updated
  * \param changed pointer which indicates whether the MTRR needed to be changed
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 5e4be30ff903..9abbdf7562c5 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -748,7 +748,7 @@ static int __init mtrr_init_finialize(void)
         if (use_intel())
                 mtrr_state_warn();
         else {
-                /* The CPUs haven't MTRR and seemes not support SMP. They have
+                /* The CPUs haven't MTRR and seem to not support SMP. They have
                  * specific drivers, we use a tricky method to support
                  * suspend/resume for them.
                  * TBD: is there any system with such CPU which supports