13 files changed, 233 insertions, 228 deletions

diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 2cf23634b6d9..6882a735d9c0 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -7,7 +7,7 @@
 #include <asm/pat.h>
 #include <asm/processor.h>
 
-#include <mach_apic.h>
+#include <asm/apic.h>
 
 struct cpuid_bit {
         u16 feature;
@@ -69,7 +69,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
  */
 void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
 {
-#ifdef CONFIG_X86_SMP
+#ifdef CONFIG_SMP
         unsigned int eax, ebx, ecx, edx, sub_index;
         unsigned int ht_mask_width, core_plus_mask_width;
         unsigned int core_select_mask, core_level_siblings;
@@ -116,22 +116,14 @@ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
 
         core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
 
-#ifdef CONFIG_X86_32
-        c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
+        c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, ht_mask_width)
                                                  & core_select_mask;
-        c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
+        c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, core_plus_mask_width);
         /*
          * Reinit the apicid, now that we have extended initial_apicid.
          */
-        c->apicid = phys_pkg_id(c->initial_apicid, 0);
-#else
-        c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
-        c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
-        /*
-         * Reinit the apicid, now that we have extended initial_apicid.
-         */
-        c->apicid = phys_pkg_id(0);
-#endif
+        c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
+
         c->x86_max_cores = (core_level_siblings / smp_num_siblings);
 
 
@@ -143,37 +135,3 @@ void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
         return;
 #endif
 }
-
-#ifdef CONFIG_X86_PAT
-void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
-{
-        if (!cpu_has_pat)
-                pat_disable("PAT not supported by CPU.");
-
-        switch (c->x86_vendor) {
-        case X86_VENDOR_INTEL:
-                /*
-                 * There is a known erratum on Pentium III and Core Solo
-                 * and Core Duo CPUs.
-                 * " Page with PAT set to WC while associated MTRR is UC
-                 *   may consolidate to UC "
-                 * Because of this erratum, it is better to stick with
-                 * setting WC in MTRR rather than using PAT on these CPUs.
-                 *
-                 * Enable PAT WC only on P4, Core 2 or later CPUs.
-                 */
-                if (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 15))
-                        return;
-
-                pat_disable("PAT WC disabled due to known CPU erratum.");
-                return;
-
-        case X86_VENDOR_AMD:
-        case X86_VENDOR_CENTAUR:
-        case X86_VENDOR_TRANSMETA:
-                return;
-        }
-
-        pat_disable("PAT disabled. Not yet verified on this CPU type.");
-}
-#endif
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 7c878f6aa919..25423a5b80ed 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -12,8 +12,6 @@
 # include <asm/cacheflush.h>
 #endif
 
-#include <mach_apic.h>
-
 #include "cpu.h"
 
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 83492b1f93b1..826d5c876278 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -21,14 +21,14 @@
 #include <asm/asm.h>
 #include <asm/numa.h>
 #include <asm/smp.h>
-#ifdef CONFIG_X86_LOCAL_APIC
-#include <asm/mpspec.h>
+#include <asm/cpu.h>
+#include <asm/cpumask.h>
 #include <asm/apic.h>
-#include <mach_apic.h>
-#include <asm/genapic.h>
+
+#ifdef CONFIG_X86_LOCAL_APIC
+#include <asm/uv/uv.h>
 #endif
 
-#include <asm/pda.h>
 #include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/desc.h>
@@ -37,6 +37,7 @@
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/hypervisor.h>
+#include <asm/stackprotector.h>
 
 #include "cpu.h"
 
@@ -50,6 +51,15 @@ cpumask_var_t cpu_initialized_mask;
 /* representing cpus for which sibling maps can be computed */
 cpumask_var_t cpu_sibling_setup_mask;
 
+/* correctly size the local cpu masks */
+void __init setup_cpu_local_masks(void)
+{
+        alloc_bootmem_cpumask_var(&cpu_initialized_mask);
+        alloc_bootmem_cpumask_var(&cpu_callin_mask);
+        alloc_bootmem_cpumask_var(&cpu_callout_mask);
+        alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
+}
+
 #else /* CONFIG_X86_32 */
 
 cpumask_t cpu_callin_map;
@@ -62,23 +72,23 @@ cpumask_t cpu_sibling_setup_map;
 
 static struct cpu_dev *this_cpu __cpuinitdata;
 
+DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 #ifdef CONFIG_X86_64
-/* We need valid kernel segments for data and code in long mode too
- * IRET will check the segment types  kkeil 2000/10/28
- * Also sysret mandates a special GDT layout
- */
-/* The TLS descriptors are currently at a different place compared to i386.
-   Hopefully nobody expects them at a fixed place (Wine?) */
-DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
+        /*
+         * We need valid kernel segments for data and code in long mode too
+         * IRET will check the segment types  kkeil 2000/10/28
+         * Also sysret mandates a special GDT layout
+         *
+         * The TLS descriptors are currently at a different place compared to i386.
+         * Hopefully nobody expects them at a fixed place (Wine?)
+         */
         [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
         [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
-} };
 #else
-DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
@@ -110,9 +120,10 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
         [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
 
         [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
-        [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
-} };
+        [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } },
+        GDT_STACK_CANARY_INIT
 #endif
+} };
 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 
 #ifdef CONFIG_X86_32
@@ -213,6 +224,49 @@ static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 #endif
 
 /*
+ * Some CPU features depend on higher CPUID levels, which may not always
+ * be available due to CPUID level capping or broken virtualization
+ * software.  Add those features to this table to auto-disable them.
+ */
+struct cpuid_dependent_feature {
+        u32 feature;
+        u32 level;
+};
+static const struct cpuid_dependent_feature __cpuinitconst
+cpuid_dependent_features[] = {
+        { X86_FEATURE_MWAIT,            0x00000005 },
+        { X86_FEATURE_DCA,              0x00000009 },
+        { X86_FEATURE_XSAVE,            0x0000000d },
+        { 0, 0 }
+};
+
+static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
+{
+        const struct cpuid_dependent_feature *df;
+        for (df = cpuid_dependent_features; df->feature; df++) {
+                /*
+                 * Note: cpuid_level is set to -1 if unavailable, but
+                 * extended_extended_level is set to 0 if unavailable
+                 * and the legitimate extended levels are all negative
+                 * when signed; hence the weird messing around with
+                 * signs here...
+                 */
+                if (cpu_has(c, df->feature) &&
+                    ((s32)df->level < 0 ?
+                     (u32)df->level > (u32)c->extended_cpuid_level :
+                     (s32)df->level > (s32)c->cpuid_level)) {
+                        clear_cpu_cap(c, df->feature);
+                        if (warn)
+                                printk(KERN_WARNING
+                                       "CPU: CPU feature %s disabled "
+                                       "due to lack of CPUID level 0x%x\n",
+                                       x86_cap_flags[df->feature],
+                                       df->level);
+                }
+        }
+}
+
+/*
  * Naming convention should be: <Name> [(<Codename>)]
  * This table only is used unless init_<vendor>() below doesn't set it;
  * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
@@ -242,18 +296,29 @@ static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
 
 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
 
+void load_percpu_segment(int cpu)
+{
+#ifdef CONFIG_X86_32
+        loadsegment(fs, __KERNEL_PERCPU);
+#else
+        loadsegment(gs, 0);
+        wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
+#endif
+        load_stack_canary_segment();
+}
+
 /* Current gdt points %fs at the "master" per-cpu area: after this,
  * it's on the real one. */
-void switch_to_new_gdt(void)
+void switch_to_new_gdt(int cpu)
 {
         struct desc_ptr gdt_descr;
 
-        gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
+        gdt_descr.address = (long)get_cpu_gdt_table(cpu);
         gdt_descr.size = GDT_SIZE - 1;
         load_gdt(&gdt_descr);
-#ifdef CONFIG_X86_32
-        asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
-#endif
+        /* Reload the per-cpu base */
+
+        load_percpu_segment(cpu);
 }
 
 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
@@ -383,11 +448,7 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
                 }
 
                 index_msb = get_count_order(smp_num_siblings);
-#ifdef CONFIG_X86_64
-                c->phys_proc_id = phys_pkg_id(index_msb);
-#else
-                c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
-#endif
+                c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
 
                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 
@@ -395,13 +456,8 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 
                 core_bits = get_count_order(c->x86_max_cores);
 
-#ifdef CONFIG_X86_64
-                c->cpu_core_id = phys_pkg_id(index_msb) &
+                c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
                                                ((1 << core_bits) - 1);
-#else
-                c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
-                                               ((1 << core_bits) - 1);
-#endif
         }
 
 out:
@@ -570,11 +626,10 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
         if (this_cpu->c_early_init)
                 this_cpu->c_early_init(c);
 
-        validate_pat_support(c);
-
 #ifdef CONFIG_SMP
         c->cpu_index = boot_cpu_id;
 #endif
+        filter_cpuid_features(c, false);
 }
 
 void __init early_cpu_init(void)
@@ -637,7 +692,7 @@ static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
 #ifdef CONFIG_X86_32
 # ifdef CONFIG_X86_HT
-                c->apicid = phys_pkg_id(c->initial_apicid, 0);
+                c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 # else
                 c->apicid = c->initial_apicid;
 # endif
@@ -684,7 +739,7 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                 this_cpu->c_identify(c);
 
 #ifdef CONFIG_X86_64
-        c->apicid = phys_pkg_id(0);
+        c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 #endif
 
         /*
@@ -708,6 +763,9 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
          * we do "generic changes."
          */
 
+        /* Filter out anything that depends on CPUID levels we don't have */
+        filter_cpuid_features(c, true);
+
         /* If the model name is still unset, do table lookup. */
         if (!c->x86_model_id[0]) {
                 char *p;
@@ -877,54 +935,22 @@ static __init int setup_disablecpuid(char *arg)
 __setup("clearcpuid=", setup_disablecpuid);
 
 #ifdef CONFIG_X86_64
-struct x8664_pda **_cpu_pda __read_mostly;
-EXPORT_SYMBOL(_cpu_pda);
-
 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 
-static char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
+DEFINE_PER_CPU_FIRST(union irq_stack_union,
+                     irq_stack_union) __aligned(PAGE_SIZE);
+DEFINE_PER_CPU(char *, irq_stack_ptr) =
+        init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
 
-void __cpuinit pda_init(int cpu)
-{
-        struct x8664_pda *pda = cpu_pda(cpu);
+DEFINE_PER_CPU(unsigned long, kernel_stack) =
+        (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
+EXPORT_PER_CPU_SYMBOL(kernel_stack);
 
-        /* Setup up data that may be needed in __get_free_pages early */
-        loadsegment(fs, 0);
-        loadsegment(gs, 0);
-        /* Memory clobbers used to order PDA accessed */
-        mb();
-        wrmsrl(MSR_GS_BASE, pda);
-        mb();
-
-        pda->cpunumber = cpu;
-        pda->irqcount = -1;
-        pda->kernelstack = (unsigned long)stack_thread_info() -
-                                 PDA_STACKOFFSET + THREAD_SIZE;
-        pda->active_mm = &init_mm;
-        pda->mmu_state = 0;
-
-        if (cpu == 0) {
-                /* others are initialized in smpboot.c */
-                pda->pcurrent = &init_task;
-                pda->irqstackptr = boot_cpu_stack;
-                pda->irqstackptr += IRQSTACKSIZE - 64;
-        } else {
-                if (!pda->irqstackptr) {
-                        pda->irqstackptr = (char *)
-                                __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
-                        if (!pda->irqstackptr)
-                                panic("cannot allocate irqstack for cpu %d",
-                                      cpu);
-                        pda->irqstackptr += IRQSTACKSIZE - 64;
-                }
+DEFINE_PER_CPU(unsigned int, irq_count) = -1;
 
-                if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
-                        pda->nodenumber = cpu_to_node(cpu);
-        }
-}
-
-static char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
-                                  DEBUG_STKSZ] __page_aligned_bss;
+static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
+        [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
+        __aligned(PAGE_SIZE);
 
 extern asmlinkage void ignore_sysret(void);
 
@@ -957,16 +983,21 @@ unsigned long kernel_eflags;
  */
 DEFINE_PER_CPU(struct orig_ist, orig_ist);
 
-#else
+#else   /* x86_64 */
 
-/* Make sure %fs is initialized properly in idle threads */
+#ifdef CONFIG_CC_STACKPROTECTOR
+DEFINE_PER_CPU(unsigned long, stack_canary);
+#endif
+
+/* Make sure %fs and %gs are initialized properly in idle threads */
 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
 {
         memset(regs, 0, sizeof(struct pt_regs));
         regs->fs = __KERNEL_PERCPU;
+        regs->gs = __KERNEL_STACK_CANARY;
         return regs;
 }
-#endif
+#endif  /* x86_64 */
 
 /*
  * cpu_init() initializes state that is per-CPU. Some data is already
@@ -982,15 +1013,14 @@ void __cpuinit cpu_init(void)
         struct tss_struct *t = &per_cpu(init_tss, cpu);
         struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
         unsigned long v;
-        char *estacks = NULL;
         struct task_struct *me;
         int i;
 
-        /* CPU 0 is initialised in head64.c */
-        if (cpu != 0)
-                pda_init(cpu);
-        else
-                estacks = boot_exception_stacks;
+#ifdef CONFIG_NUMA
+        if (cpu != 0 && percpu_read(node_number) == 0 &&
+            cpu_to_node(cpu) != NUMA_NO_NODE)
+                percpu_write(node_number, cpu_to_node(cpu));
+#endif
 
         me = current;
 
@@ -1006,7 +1036,9 @@ void __cpuinit cpu_init(void)
          * and set up the GDT descriptor:
          */
 
-        switch_to_new_gdt();
+        switch_to_new_gdt(cpu);
+        loadsegment(fs, 0);
+
         load_idt((const struct desc_ptr *)&idt_descr);
 
         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
@@ -1017,25 +1049,20 @@ void __cpuinit cpu_init(void)
         barrier();
 
         check_efer();
-        if (cpu != 0 && x2apic)
+        if (cpu != 0)
                 enable_x2apic();
 
         /*
          * set up and load the per-CPU TSS
          */
         if (!orig_ist->ist[0]) {
-                static const unsigned int order[N_EXCEPTION_STACKS] = {
-                  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
-                  [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
+                static const unsigned int sizes[N_EXCEPTION_STACKS] = {
+                  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ,
+                  [DEBUG_STACK - 1] = DEBUG_STKSZ
                 };
+                char *estacks = per_cpu(exception_stacks, cpu);
                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
-                        if (cpu) {
-                                estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
-                                if (!estacks)
-                                        panic("Cannot allocate exception "
-                                              "stack %ld %d\n", v, cpu);
-                        }
-                        estacks += PAGE_SIZE << order[v];
+                        estacks += sizes[v];
                         orig_ist->ist[v] = t->x86_tss.ist[v] =
                                         (unsigned long)estacks;
                 }
@@ -1069,22 +1096,19 @@ void __cpuinit cpu_init(void)
          */
         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
                 arch_kgdb_ops.correct_hw_break();
-        else {
+        else
 #endif
-        /*
-         * Clear all 6 debug registers:
-         */
-
-        set_debugreg(0UL, 0);
-        set_debugreg(0UL, 1);
-        set_debugreg(0UL, 2);
-        set_debugreg(0UL, 3);
-        set_debugreg(0UL, 6);
-        set_debugreg(0UL, 7);
-#ifdef CONFIG_KGDB
-        /* If the kgdb is connected no debug regs should be altered. */
+        {
+                /*
+                 * Clear all 6 debug registers:
+                 */
+                set_debugreg(0UL, 0);
+                set_debugreg(0UL, 1);
+                set_debugreg(0UL, 2);
+                set_debugreg(0UL, 3);
+                set_debugreg(0UL, 6);
+                set_debugreg(0UL, 7);
         }
-#endif
 
         fpu_init();
 
@@ -1114,7 +1138,7 @@ void __cpuinit cpu_init(void)
                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
         load_idt(&idt_descr);
-        switch_to_new_gdt();
+        switch_to_new_gdt(cpu);
 
         /*
          * Set up and load the per-CPU TSS and LDT
@@ -1135,9 +1159,6 @@ void __cpuinit cpu_init(void)
         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
 #endif
 
-        /* Clear %gs. */
-        asm volatile ("mov %0, %%gs" : : "r" (0));
-
         /* Clear all 6 debug registers: */
         set_debugreg(0, 0);
         set_debugreg(0, 1);
diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
index 3babe1f1e912..23da96e57b17 100644
--- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
+++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c
@@ -601,7 +601,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
         if (!data)
                 return -ENOMEM;
 
-        data->acpi_data = percpu_ptr(acpi_perf_data, cpu);
+        data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu);
         per_cpu(drv_data, cpu) = data;
 
         if (cpu_has(c, X86_FEATURE_CONSTANT_TSC))
diff --git a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c b/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
index 3f83ea12c47a..35a257dd4bb7 100644
--- a/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
+++ b/arch/x86/kernel/cpu/cpufreq/e_powersaver.c
@@ -204,12 +204,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
         }
         /* Enable Enhanced PowerSaver */
         rdmsrl(MSR_IA32_MISC_ENABLE, val);
-        if (!(val & 1 << 16)) {
-                val |= 1 << 16;
+        if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+                val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
                 wrmsrl(MSR_IA32_MISC_ENABLE, val);
                 /* Can be locked at 0 */
                 rdmsrl(MSR_IA32_MISC_ENABLE, val);
-                if (!(val & 1 << 16)) {
+                if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
                         printk(KERN_INFO "eps: Can't enable Enhanced PowerSaver\n");
                         return -ENODEV;
                 }
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index f08998278a3a..c9f1fdc02830 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -390,14 +390,14 @@ static int centrino_cpu_init(struct cpufreq_policy *policy)
            enable it if not. */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 
-        if (!(l & (1<<16))) {
-                l |= (1<<16);
+        if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+                l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 
                 /* check to see if it stuck */
                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-                if (!(l & (1<<16))) {
+                if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
                         printk(KERN_INFO PFX
                                 "couldn't enable Enhanced SpeedStep\n");
                         return -ENODEV;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5fff00c70de0..1a89a2b68d15 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -25,7 +25,6 @@
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/mpspec.h>
 #include <asm/apic.h>
-#include <mach_apic.h>
 #endif
 
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
@@ -69,6 +68,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                 sched_clock_stable = 1;
         }
 
+        /*
+         * There is a known erratum on Pentium III and Core Solo
+         * and Core Duo CPUs.
+         * " Page with PAT set to WC while associated MTRR is UC
+         *   may consolidate to UC "
+         * Because of this erratum, it is better to stick with
+         * setting WC in MTRR rather than using PAT on these CPUs.
+         *
+         * Enable PAT WC only on P4, Core 2 or later CPUs.
+         */
+        if (c->x86 == 6 && c->x86_model < 15)
+                clear_cpu_cap(c, X86_FEATURE_PAT);
 }
 
 #ifdef CONFIG_X86_32
@@ -141,10 +152,10 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
          */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
-                if ((lo & (1<<9)) == 0) {
+                if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-                        lo |= (1<<9);   /* Disable hw prefetching */
+                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
                 }
         }
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index da299eb85fc0..7293508d8f5c 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -147,7 +147,16 @@ struct _cpuid4_info {
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
         unsigned long can_disable;
-        cpumask_t shared_cpu_map;       /* future?: only cpus/node is needed */
+        DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
+};
+
+/* subset of above _cpuid4_info w/o shared_cpu_map */
+struct _cpuid4_info_regs {
+        union _cpuid4_leaf_eax eax;
+        union _cpuid4_leaf_ebx ebx;
+        union _cpuid4_leaf_ecx ecx;
+        unsigned long size;
+        unsigned long can_disable;
 };
 
 #ifdef CONFIG_PCI
@@ -278,7 +287,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 }
 
 static void __cpuinit
-amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
+amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
         if (index < 3)
                 return;
@@ -286,7 +295,8 @@ amd_check_l3_disable(int index, struct _cpuid4_info *this_leaf)
 }
 
 static int
-__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
+__cpuinit cpuid4_cache_lookup_regs(int index,
+                                   struct _cpuid4_info_regs *this_leaf)
 {
         union _cpuid4_leaf_eax  eax;
         union _cpuid4_leaf_ebx  ebx;
@@ -314,6 +324,15 @@ __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
         return 0;
 }
 
+static int
+__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
+{
+        struct _cpuid4_info_regs *leaf_regs =
+                (struct _cpuid4_info_regs *)this_leaf;
+
+        return cpuid4_cache_lookup_regs(index, leaf_regs);
+}
+
 static int __cpuinit find_num_cache_leaves(void)
 {
         unsigned int            eax, ebx, ecx, edx;
@@ -353,11 +372,10 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                  * parameters cpuid leaf to find the cache details
                  */
                 for (i = 0; i < num_cache_leaves; i++) {
-                        struct _cpuid4_info this_leaf;
-
+                        struct _cpuid4_info_regs this_leaf;
                         int retval;
 
-                        retval = cpuid4_cache_lookup(i, &this_leaf);
+                        retval = cpuid4_cache_lookup_regs(i, &this_leaf);
                         if (retval >= 0) {
                                 switch(this_leaf.eax.split.level) {
                                     case 1:
@@ -506,17 +524,20 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
         num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
 
         if (num_threads_sharing == 1)
-                cpu_set(cpu, this_leaf->shared_cpu_map);
+                cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
         else {
                 index_msb = get_count_order(num_threads_sharing);
 
                 for_each_online_cpu(i) {
                         if (cpu_data(i).apicid >> index_msb ==
                             c->apicid >> index_msb) {
-                                cpu_set(i, this_leaf->shared_cpu_map);
+                                cpumask_set_cpu(i,
+                                        to_cpumask(this_leaf->shared_cpu_map));
                                 if (i != cpu && per_cpu(cpuid4_info, i))  {
-                                        sibling_leaf = CPUID4_INFO_IDX(i, index);
-                                        cpu_set(cpu, sibling_leaf->shared_cpu_map);
+                                        sibling_leaf =
+                                                CPUID4_INFO_IDX(i, index);
+                                        cpumask_set_cpu(cpu, to_cpumask(
+                                                sibling_leaf->shared_cpu_map));
                                 }
                         }
                 }
@@ -528,9 +549,10 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
         int sibling;
 
         this_leaf = CPUID4_INFO_IDX(cpu, index);
-        for_each_cpu_mask_nr(sibling, this_leaf->shared_cpu_map) {
+        for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
                 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
-                cpu_clear(cpu, sibling_leaf->shared_cpu_map);
+                cpumask_clear_cpu(cpu,
+                                  to_cpumask(sibling_leaf->shared_cpu_map));
         }
 }
 #else
@@ -635,8 +657,9 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
         int n = 0;
 
         if (len > 1) {
-                cpumask_t *mask = &this_leaf->shared_cpu_map;
+                const struct cpumask *mask;
 
+                mask = to_cpumask(this_leaf->shared_cpu_map);
                 n = type?
                         cpulist_scnprintf(buf, len-2, mask) :
                         cpumask_scnprintf(buf, len-2, mask);
@@ -699,7 +722,8 @@ static struct pci_dev *get_k8_northbridge(int node)
 
 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf)
 {
-        int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+        const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+        int node = cpu_to_node(cpumask_first(mask));
         struct pci_dev *dev = NULL;
         ssize_t ret = 0;
         int i;
@@ -733,7 +757,8 @@ static ssize_t
 store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf,
                     size_t count)
 {
-        int node = cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
+        const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map);
+        int node = cpu_to_node(cpumask_first(mask));
         struct pci_dev *dev = NULL;
         unsigned int ret, index, val;
 
@@ -878,7 +903,7 @@ err_out:
         return -ENOMEM;
 }
 
-static cpumask_t cache_dev_map = CPU_MASK_NONE;
+static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
 
 /* Add/Remove cache interface for CPU device */
 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
@@ -918,7 +943,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
                 }
                 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
         }
-        cpu_set(cpu, cache_dev_map);
+        cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
 
         kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
         return 0;
@@ -931,9 +956,9 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
 
         if (per_cpu(cpuid4_info, cpu) == NULL)
                 return;
-        if (!cpu_isset(cpu, cache_dev_map))
+        if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
                 return;
-        cpu_clear(cpu, cache_dev_map);
+        cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
 
         for (i = 0; i < num_cache_leaves; i++)
                 kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index f2ee0ae29bd6..9817506dd469 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -67,7 +67,7 @@ static struct threshold_block threshold_defaults = {
 struct threshold_bank {
         struct kobject *kobj;
         struct threshold_block *blocks;
-        cpumask_t cpus;
+        cpumask_var_t cpus;
 };
 static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
 
@@ -481,7 +481,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 
 #ifdef CONFIG_SMP
         if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
-                i = first_cpu(per_cpu(cpu_core_map, cpu));
+                i = cpumask_first(&per_cpu(cpu_core_map, cpu));
 
                 /* first core not up yet */
                 if (cpu_data(i).cpu_core_id)
@@ -501,7 +501,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 if (err)
                         goto out;
 
-                b->cpus = per_cpu(cpu_core_map, cpu);
+                cpumask_copy(b->cpus, &per_cpu(cpu_core_map, cpu));
                 per_cpu(threshold_banks, cpu)[bank] = b;
                 goto out;
         }
@@ -512,15 +512,20 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 err = -ENOMEM;
                 goto out;
         }
+        if (!alloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
+                kfree(b);
+                err = -ENOMEM;
+                goto out;
+        }
 
         b->kobj = kobject_create_and_add(name, &per_cpu(device_mce, cpu).kobj);
         if (!b->kobj)
                 goto out_free;
 
 #ifndef CONFIG_SMP
-        b->cpus = CPU_MASK_ALL;
+        cpumask_setall(b->cpus);
 #else
-        b->cpus = per_cpu(cpu_core_map, cpu);
+        cpumask_copy(b->cpus, &per_cpu(cpu_core_map, cpu));
 #endif
 
         per_cpu(threshold_banks, cpu)[bank] = b;
@@ -529,7 +534,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
         if (err)
                 goto out_free;
 
-        for_each_cpu_mask_nr(i, b->cpus) {
+        for_each_cpu(i, b->cpus) {
                 if (i == cpu)
                         continue;
 
@@ -545,6 +550,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 
 out_free:
         per_cpu(threshold_banks, cpu)[bank] = NULL;
+        free_cpumask_var(b->cpus);
         kfree(b);
 out:
         return err;
@@ -619,7 +625,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
 #endif
 
         /* remove all sibling symlinks before unregistering */
-        for_each_cpu_mask_nr(i, b->cpus) {
+        for_each_cpu(i, b->cpus) {
                 if (i == cpu)
                         continue;
 
@@ -632,6 +638,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
 free_out:
         kobject_del(b->kobj);
         kobject_put(b->kobj);
+        free_cpumask_var(b->cpus);
         kfree(b);
         per_cpu(threshold_banks, cpu)[bank] = NULL;
 }
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index f44c36624360..aa5e287c98e0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -7,6 +7,7 @@
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <asm/processor.h>
+#include <asm/apic.h>
 #include <asm/msr.h>
 #include <asm/mce.h>
 #include <asm/hw_irq.h>
@@ -48,13 +49,13 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
          */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
-        if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {
+        if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG
                        "CPU%d: Thermal monitoring handled by SMI\n", cpu);
                 return;
         }
 
-        if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))
+        if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
                 tm2 = 1;
 
         if (h & APIC_VECTOR_MASK) {
@@ -72,7 +73,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
 
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index 9b60fce09f75..f53bdcbaf382 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -85,7 +85,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
          */
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
-        if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
+        if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
                                 cpu);
                 return; /* -EBUSY */
@@ -111,7 +111,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         vendor_thermal_interrupt = intel_thermal_interrupt;
 
         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
 
         l = apic_read(APIC_LVTTHMR);
         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 9abd48b22674..f6c70a164e32 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -19,7 +19,7 @@
 #include <linux/nmi.h>
 #include <linux/kprobes.h>
 
-#include <asm/apic.h>
+#include <asm/genapic.h>
 #include <asm/intel_arch_perfmon.h>
 
 struct nmi_watchdog_ctlblk {
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 01b1244ef1c0..d67e0e48bc2d 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -7,11 +7,10 @@
 /*
  *      Get CPU information for use by the procfs.
  */
-#ifdef CONFIG_X86_32
 static void show_cpuinfo_core(struct seq_file *m, struct cpuinfo_x86 *c,
                               unsigned int cpu)
 {
-#ifdef CONFIG_X86_HT
+#ifdef CONFIG_SMP
         if (c->x86_max_cores * smp_num_siblings > 1) {
                 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
                 seq_printf(m, "siblings\t: %d\n",
@@ -24,6 +23,7 @@ static void show_cpuinfo_core(struct seq_file *m, struct cpuinfo_x86 *c,
 #endif
 }
 
+#ifdef CONFIG_X86_32
 static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
 {
         /*
@@ -50,22 +50,6 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
                    c->wp_works_ok ? "yes" : "no");
 }
 #else
-static void show_cpuinfo_core(struct seq_file *m, struct cpuinfo_x86 *c,
-                              unsigned int cpu)
-{
-#ifdef CONFIG_SMP
-        if (c->x86_max_cores * smp_num_siblings > 1) {
-                seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
-                seq_printf(m, "siblings\t: %d\n",
-                           cpus_weight(per_cpu(cpu_core_map, cpu)));
-                seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
-                seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
-                seq_printf(m, "apicid\t\t: %d\n", c->apicid);
-                seq_printf(m, "initial apicid\t: %d\n", c->initial_apicid);
-        }
-#endif
-}
-
 static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
 {
         seq_printf(m,