diff options
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/p5.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/p5.c b/arch/x86/kernel/cpu/mcheck/p5.c index a18310aaae0c..bfa5817afdda 100644 --- a/arch/x86/kernel/cpu/mcheck/p5.c +++ b/arch/x86/kernel/cpu/mcheck/p5.c | |||
@@ -9,20 +9,20 @@ | |||
9 | #include <linux/interrupt.h> | 9 | #include <linux/interrupt.h> |
10 | #include <linux/smp.h> | 10 | #include <linux/smp.h> |
11 | 11 | ||
12 | #include <asm/processor.h> | 12 | #include <asm/processor.h> |
13 | #include <asm/system.h> | 13 | #include <asm/system.h> |
14 | #include <asm/msr.h> | 14 | #include <asm/msr.h> |
15 | 15 | ||
16 | #include "mce.h" | 16 | #include "mce.h" |
17 | 17 | ||
18 | /* Machine check handler for Pentium class Intel */ | 18 | /* Machine check handler for Pentium class Intel */ |
19 | static void pentium_machine_check(struct pt_regs * regs, long error_code) | 19 | static void pentium_machine_check(struct pt_regs *regs, long error_code) |
20 | { | 20 | { |
21 | u32 loaddr, hi, lotype; | 21 | u32 loaddr, hi, lotype; |
22 | rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); | 22 | rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); |
23 | rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); | 23 | rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); |
24 | printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype); | 24 | printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype); |
25 | if(lotype&(1<<5)) | 25 | if (lotype&(1<<5)) |
26 | printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id()); | 26 | printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id()); |
27 | add_taint(TAINT_MACHINE_CHECK); | 27 | add_taint(TAINT_MACHINE_CHECK); |
28 | } | 28 | } |
@@ -31,13 +31,13 @@ static void pentium_machine_check(struct pt_regs * regs, long error_code) | |||
31 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c) | 31 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c) |
32 | { | 32 | { |
33 | u32 l, h; | 33 | u32 l, h; |
34 | 34 | ||
35 | /*Check for MCE support */ | 35 | /*Check for MCE support */ |
36 | if( !cpu_has(c, X86_FEATURE_MCE) ) | 36 | if (!cpu_has(c, X86_FEATURE_MCE)) |
37 | return; | 37 | return; |
38 | 38 | ||
39 | /* Default P5 to off as its often misconnected */ | 39 | /* Default P5 to off as its often misconnected */ |
40 | if(mce_disabled != -1) | 40 | if (mce_disabled != -1) |
41 | return; | 41 | return; |
42 | machine_check_vector = pentium_machine_check; | 42 | machine_check_vector = pentium_machine_check; |
43 | wmb(); | 43 | wmb(); |
@@ -47,7 +47,7 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) | |||
47 | rdmsr(MSR_IA32_P5_MC_TYPE, l, h); | 47 | rdmsr(MSR_IA32_P5_MC_TYPE, l, h); |
48 | printk(KERN_INFO "Intel old style machine check architecture supported.\n"); | 48 | printk(KERN_INFO "Intel old style machine check architecture supported.\n"); |
49 | 49 | ||
50 | /* Enable MCE */ | 50 | /* Enable MCE */ |
51 | set_in_cr4(X86_CR4_MCE); | 51 | set_in_cr4(X86_CR4_MCE); |
52 | printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id()); | 52 | printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id()); |
53 | } | 53 | } |