3 files changed, 79 insertions, 71 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c
index e633c9c2b764..f390c9f66351 100644
--- a/arch/x86/kernel/cpu/mcheck/k7.c
+++ b/arch/x86/kernel/cpu/mcheck/k7.c
@@ -9,23 +9,23 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
-#include <asm/processor.h> 
+#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 
 #include "mce.h"
 
 /* Machine Check Handler For AMD Athlon/Duron */
-static void k7_machine_check(struct pt_regs * regs, long error_code)
+static void k7_machine_check(struct pt_regs *regs, long error_code)
 {
-        int recover=1;
+        int recover = 1;
         u32 alow, ahigh, high, low;
         u32 mcgstl, mcgsth;
         int i;
 
-        rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+        rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
         if (mcgstl & (1<<0))    /* Recoverable ? */
-                recover=0;
+                recover = 0;
 
         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                 smp_processor_id(), mcgsth, mcgstl);
@@ -60,12 +60,12 @@ static void k7_machine_check(struct pt_regs * regs, long error_code)
         }
 
         if (recover&2)
-                panic ("CPU context corrupt");
+                panic("CPU context corrupt");
         if (recover&1)
-                panic ("Unable to continue");
-        printk (KERN_EMERG "Attempting to continue.\n");
+                panic("Unable to continue");
+        printk(KERN_EMERG "Attempting to continue.\n");
         mcgstl &= ~(1<<2);
-        wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+        wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 }
 
 
@@ -81,25 +81,25 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)
         machine_check_vector = k7_machine_check;
         wmb();
 
-        printk (KERN_INFO "Intel machine check architecture supported.\n");
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        printk(KERN_INFO "Intel machine check architecture supported.\n");
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<8)) /* Control register present ? */
-                wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
         nr_mce_banks = l & 0xff;
 
         /* Clear status for MC index 0 separately, we don't touch CTL,
          * as some K7 Athlons cause spurious MCEs when its enabled. */
         if (boot_cpu_data.x86 == 6) {
-                wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
+                wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
                 i = 1;
         } else
                 i = 0;
-        for (; i<nr_mce_banks; i++) {
-                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
-                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+        for (; i < nr_mce_banks; i++) {
+                wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
         }
 
-        set_in_cr4 (X86_CR4_MCE);
-        printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+        set_in_cr4(X86_CR4_MCE);
+        printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
                 smp_processor_id());
 }
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index e07e8c068ae0..501ca1cea27d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -31,7 +31,7 @@
 #include <asm/idle.h>
 
 #define MISC_MCELOG_MINOR 227
-#define NR_BANKS 6
+#define NR_SYSFS_BANKS 6
 
 atomic_t mce_entry;
 
@@ -46,7 +46,7 @@ static int mce_dont_init;
  */
 static int tolerant = 1;
 static int banks;
-static unsigned long bank[NR_BANKS] = { [0 ... NR_BANKS-1] = ~0UL };
+static unsigned long bank[NR_SYSFS_BANKS] = { [0 ... NR_SYSFS_BANKS-1] = ~0UL };
 static unsigned long notify_user;
 static int rip_msr;
 static int mce_bootlog = -1;
@@ -209,7 +209,7 @@ void do_machine_check(struct pt_regs * regs, long error_code)
         barrier();
 
         for (i = 0; i < banks; i++) {
-                if (!bank[i])
+                if (i < NR_SYSFS_BANKS && !bank[i])
                         continue;
 
                 m.misc = 0;
@@ -444,9 +444,10 @@ static void mce_init(void *dummy)
 
         rdmsrl(MSR_IA32_MCG_CAP, cap);
         banks = cap & 0xff;
-        if (banks > NR_BANKS) {
-                printk(KERN_INFO "MCE: warning: using only %d banks\n", banks);
-                banks = NR_BANKS;
+        if (banks > MCE_EXTENDED_BANK) {
+                banks = MCE_EXTENDED_BANK;
+                printk(KERN_INFO "MCE: warning: using only %d banks\n",
+                       MCE_EXTENDED_BANK);
         }
         /* Use accurate RIP reporting if available. */
         if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9)
@@ -462,7 +463,11 @@ static void mce_init(void *dummy)
                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 
         for (i = 0; i < banks; i++) {
-                wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
+                if (i < NR_SYSFS_BANKS)
+                        wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
+                else
+                        wrmsrl(MSR_IA32_MC0_CTL+4*i, ~0UL);
+
                 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
         }
 }
@@ -766,7 +771,10 @@ DEFINE_PER_CPU(struct sys_device, device_mce);
         }                                                               \
         static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name);
 
-/* TBD should generate these dynamically based on number of available banks */
+/*
+ * TBD should generate these dynamically based on number of available banks.
+ * Have only 6 contol banks in /sysfs until then.
+ */
 ACCESSOR(bank0ctl,bank[0],mce_restart())
 ACCESSOR(bank1ctl,bank[1],mce_restart())
 ACCESSOR(bank2ctl,bank[2],mce_restart())
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index cb03345554a5..eef001ad3bde 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -8,7 +8,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
-#include <asm/processor.h> 
+#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/msr.h>
 #include <asm/apic.h>
@@ -32,12 +32,12 @@ struct intel_mce_extended_msrs {
         /* u32 *reserved[]; */
 };
 
-static int mce_num_extended_msrs = 0;
+static int mce_num_extended_msrs;
 
 
 #ifdef CONFIG_X86_MCE_P4THERMAL
 static void unexpected_thermal_interrupt(struct pt_regs *regs)
-{       
+{
         printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
                         smp_processor_id());
         add_taint(TAINT_MACHINE_CHECK);
@@ -83,7 +83,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
          * be some SMM goo which handles it, so we can't even put a handler
          * since it might be delivered via SMI already -zwanem.
          */
-        rdmsr (MSR_IA32_MISC_ENABLE, l, h);
+        rdmsr(MSR_IA32_MISC_ENABLE, l, h);
         h = apic_read(APIC_LVTTHMR);
         if ((l & (1<<3)) && (h & APIC_DM_SMI)) {
                 printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",
@@ -91,7 +91,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
                 return; /* -EBUSY */
         }
 
-        /* check whether a vector already exists, temporarily masked? */        
+        /* check whether a vector already exists, temporarily masked? */
         if (h & APIC_VECTOR_MASK) {
                 printk(KERN_DEBUG "CPU%d: Thermal LVT vector (%#x) already "
                                 "installed\n",
@@ -104,18 +104,18 @@ static void intel_init_thermal(struct cpuinfo_x86 *c)
         h |= (APIC_DM_FIXED | APIC_LVT_MASKED); /* we'll mask till we're ready */
         apic_write_around(APIC_LVTTHMR, h);
 
-        rdmsr (MSR_IA32_THERM_INTERRUPT, l, h);
-        wrmsr (MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
+        rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
+        wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03 , h);
 
         /* ok we're good to go... */
         vendor_thermal_interrupt = intel_thermal_interrupt;
-        
-        rdmsr (MSR_IA32_MISC_ENABLE, l, h);
-        wrmsr (MSR_IA32_MISC_ENABLE, l | (1<<3), h);
 
-        l = apic_read (APIC_LVTTHMR);
-        apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
-        printk (KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
+        rdmsr(MSR_IA32_MISC_ENABLE, l, h);
+        wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);
+
+        l = apic_read(APIC_LVTTHMR);
+        apic_write_around(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
+        printk(KERN_INFO "CPU%d: Thermal monitoring enabled\n", cpu);
 
         /* enable thermal throttle processing */
         atomic_set(&therm_throt_en, 1);
@@ -129,28 +129,28 @@ static inline void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
 {
         u32 h;
 
-        rdmsr (MSR_IA32_MCG_EAX, r->eax, h);
-        rdmsr (MSR_IA32_MCG_EBX, r->ebx, h);
-        rdmsr (MSR_IA32_MCG_ECX, r->ecx, h);
-        rdmsr (MSR_IA32_MCG_EDX, r->edx, h);
-        rdmsr (MSR_IA32_MCG_ESI, r->esi, h);
-        rdmsr (MSR_IA32_MCG_EDI, r->edi, h);
-        rdmsr (MSR_IA32_MCG_EBP, r->ebp, h);
-        rdmsr (MSR_IA32_MCG_ESP, r->esp, h);
-        rdmsr (MSR_IA32_MCG_EFLAGS, r->eflags, h);
-        rdmsr (MSR_IA32_MCG_EIP, r->eip, h);
+        rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
+        rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
+        rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
+        rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
+        rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
+        rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
+        rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
+        rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
+        rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
+        rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
 }
 
-static void intel_machine_check(struct pt_regs * regs, long error_code)
+static void intel_machine_check(struct pt_regs *regs, long error_code)
 {
-        int recover=1;
+        int recover = 1;
         u32 alow, ahigh, high, low;
         u32 mcgstl, mcgsth;
         int i;
 
-        rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
+        rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
         if (mcgstl & (1<<0))    /* Recoverable ? */
-                recover=0;
+                recover = 0;
 
         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
                 smp_processor_id(), mcgsth, mcgstl);
@@ -191,20 +191,20 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
         }
 
         if (recover & 2)
-                panic ("CPU context corrupt");
+                panic("CPU context corrupt");
         if (recover & 1)
-                panic ("Unable to continue");
+                panic("Unable to continue");
 
         printk(KERN_EMERG "Attempting to continue.\n");
-        /* 
-         * Do not clear the MSR_IA32_MCi_STATUS if the error is not 
+        /*
+         * Do not clear the MSR_IA32_MCi_STATUS if the error is not
          * recoverable/continuable.This will allow BIOS to look at the MSRs
          * for errors if the OS could not log the error.
          */
-        for (i=0; i<nr_mce_banks; i++) {
+        for (i = 0; i < nr_mce_banks; i++) {
                 u32 msr;
                 msr = MSR_IA32_MC0_STATUS+i*4;
-                rdmsr (msr, low, high);
+                rdmsr(msr, low, high);
                 if (high&(1<<31)) {
                         /* Clear it */
                         wrmsr(msr, 0UL, 0UL);
@@ -214,7 +214,7 @@ static void intel_machine_check(struct pt_regs * regs, long error_code)
                 }
         }
         mcgstl &= ~(1<<2);
-        wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
+        wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 }
 
 
@@ -222,30 +222,30 @@ void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 {
         u32 l, h;
         int i;
-        
+
         machine_check_vector = intel_machine_check;
         wmb();
 
-        printk (KERN_INFO "Intel machine check architecture supported.\n");
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        printk(KERN_INFO "Intel machine check architecture supported.\n");
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<8)) /* Control register present ? */
-                wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
         nr_mce_banks = l & 0xff;
 
-        for (i=0; i<nr_mce_banks; i++) {
-                wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
-                wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
+        for (i = 0; i < nr_mce_banks; i++) {
+                wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+                wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
         }
 
-        set_in_cr4 (X86_CR4_MCE);
-        printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
+        set_in_cr4(X86_CR4_MCE);
+        printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
                 smp_processor_id());
 
         /* Check for P4/Xeon extended MCE MSRs */
-        rdmsr (MSR_IA32_MCG_CAP, l, h);
+        rdmsr(MSR_IA32_MCG_CAP, l, h);
         if (l & (1<<9)) {/* MCG_EXT_P */
                 mce_num_extended_msrs = (l >> 16) & 0xff;
-                printk (KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
+                printk(KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
                                 " available\n",
                         smp_processor_id(), mce_num_extended_msrs);