1 files changed, 222 insertions, 174 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9bfe9d2ea615..b1598a9436d0 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -34,6 +34,7 @@
 #include <linux/smp.h>
 #include <linux/fs.h>
 #include <linux/mm.h>
+#include <linux/debugfs.h>
 
 #include <asm/processor.h>
 #include <asm/hw_irq.h>
@@ -45,21 +46,8 @@
 
 #include "mce-internal.h"
 
-/* Handle unconfigured int18 (should never happen) */
-static void unexpected_machine_check(struct pt_regs *regs, long error_code)
-{
-        printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
-               smp_processor_id());
-}
-
-/* Call the installed machine check handler for this CPU setup. */
-void (*machine_check_vector)(struct pt_regs *, long error_code) =
-                                                unexpected_machine_check;
-
 int mce_disabled __read_mostly;
 
-#ifdef CONFIG_X86_NEW_MCE
-
 #define MISC_MCELOG_MINOR       227
 
 #define SPINUNIT 100    /* 100ns */
@@ -77,7 +65,6 @@ DEFINE_PER_CPU(unsigned, mce_exception_count);
  */
 static int                      tolerant                __read_mostly = 1;
 static int                      banks                   __read_mostly;
-static u64                      *bank                   __read_mostly;
 static int                      rip_msr                 __read_mostly;
 static int                      mce_bootlog             __read_mostly = -1;
 static int                      monarch_timeout         __read_mostly = -1;
@@ -87,28 +74,35 @@ int				mce_cmci_disabled	__read_mostly;
 int                             mce_ignore_ce           __read_mostly;
 int                             mce_ser                 __read_mostly;
 
+struct mce_bank                *mce_banks               __read_mostly;
+
 /* User mode helper program triggered by machine check event */
 static unsigned long            mce_need_notify;
 static char                     mce_helper[128];
 static char                     *mce_helper_argv[2] = { mce_helper, NULL };
 
-static unsigned long            dont_init_banks;
-
 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
 static DEFINE_PER_CPU(struct mce, mces_seen);
 static int                      cpu_missing;
 
+static void default_decode_mce(struct mce *m)
+{
+        pr_emerg("No human readable MCE decoding support on this CPU type.\n");
+        pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
+}
+
+/*
+ * CPU/chipset specific EDAC code can register a callback here to print
+ * MCE errors in a human-readable form:
+ */
+void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce;
+EXPORT_SYMBOL(x86_mce_decode_callback);
 
 /* MCA banks polled by the period polling timer for corrected events */
 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
         [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
 };
 
-static inline int skip_bank_init(int i)
-{
-        return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
-}
-
 static DEFINE_PER_CPU(struct work_struct, mce_work);
 
 /* Do initial initialization of a struct mce */
@@ -183,59 +177,60 @@ void mce_log(struct mce *mce)
         set_bit(0, &mce_need_notify);
 }
 
-void __weak decode_mce(struct mce *m)
-{
-        return;
-}
-
 static void print_mce(struct mce *m)
 {
-        printk(KERN_EMERG
-               "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
+        pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
                m->extcpu, m->mcgstatus, m->bank, m->status);
+
         if (m->ip) {
-                printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
-                       !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
-                       m->cs, m->ip);
+                pr_emerg("RIP%s %02x:<%016Lx> ",
+                        !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
+                                m->cs, m->ip);
+
                 if (m->cs == __KERNEL_CS)
                         print_symbol("{%s}", m->ip);
-                printk(KERN_CONT "\n");
+                pr_cont("\n");
         }
-        printk(KERN_EMERG "TSC %llx ", m->tsc);
+
+        pr_emerg("TSC %llx ", m->tsc);
         if (m->addr)
-                printk(KERN_CONT "ADDR %llx ", m->addr);
+                pr_cont("ADDR %llx ", m->addr);
         if (m->misc)
-                printk(KERN_CONT "MISC %llx ", m->misc);
-        printk(KERN_CONT "\n");
-        printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
-                        m->cpuvendor, m->cpuid, m->time, m->socketid,
-                        m->apicid);
+                pr_cont("MISC %llx ", m->misc);
 
-        decode_mce(m);
+        pr_cont("\n");
+        pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
+                m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
+
+        /*
+         * Print out human-readable details about the MCE error,
+         * (if the CPU has an implementation for that):
+         */
+        x86_mce_decode_callback(m);
 }
 
 static void print_mce_head(void)
 {
-        printk(KERN_EMERG "\nHARDWARE ERROR\n");
+        pr_emerg("\nHARDWARE ERROR\n");
 }
 
 static void print_mce_tail(void)
 {
-        printk(KERN_EMERG "This is not a software problem!\n"
-#if (!defined(CONFIG_EDAC) || !defined(CONFIG_CPU_SUP_AMD))
-               "Run through mcelog --ascii to decode and contact your hardware vendor\n"
-#endif
-               );
+        pr_emerg("This is not a software problem!\n");
 }
 
 #define PANIC_TIMEOUT 5 /* 5 seconds */
 
 static atomic_t mce_paniced;
 
+static int fake_panic;
+static atomic_t mce_fake_paniced;
+
 /* Panic in progress. Enable interrupts and wait for final IPI */
 static void wait_for_panic(void)
 {
         long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
+
         preempt_disable();
         local_irq_enable();
         while (timeout-- > 0)
@@ -249,15 +244,21 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
 {
         int i;
 
-        /*
-         * Make sure only one CPU runs in machine check panic
-         */
-        if (atomic_add_return(1, &mce_paniced) > 1)
-                wait_for_panic();
-        barrier();
+        if (!fake_panic) {
+                /*
+                 * Make sure only one CPU runs in machine check panic
+                 */
+                if (atomic_inc_return(&mce_paniced) > 1)
+                        wait_for_panic();
+                barrier();
 
-        bust_spinlocks(1);
-        console_verbose();
+                bust_spinlocks(1);
+                console_verbose();
+        } else {
+                /* Don't log too much for fake panic */
+                if (atomic_inc_return(&mce_fake_paniced) > 1)
+                        return;
+        }
         print_mce_head();
         /* First print corrected ones that are still unlogged */
         for (i = 0; i < MCE_LOG_LEN; i++) {
@@ -284,9 +285,12 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
         print_mce_tail();
         if (exp)
                 printk(KERN_EMERG "Machine check: %s\n", exp);
-        if (panic_timeout == 0)
-                panic_timeout = mce_panic_timeout;
-        panic(msg);
+        if (!fake_panic) {
+                if (panic_timeout == 0)
+                        panic_timeout = mce_panic_timeout;
+                panic(msg);
+        } else
+                printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
 }
 
 /* Support code for software error injection */
@@ -294,13 +298,14 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
 static int msr_to_offset(u32 msr)
 {
         unsigned bank = __get_cpu_var(injectm.bank);
+
         if (msr == rip_msr)
                 return offsetof(struct mce, ip);
-        if (msr == MSR_IA32_MC0_STATUS + bank*4)
+        if (msr == MSR_IA32_MCx_STATUS(bank))
                 return offsetof(struct mce, status);
-        if (msr == MSR_IA32_MC0_ADDR + bank*4)
+        if (msr == MSR_IA32_MCx_ADDR(bank))
                 return offsetof(struct mce, addr);
-        if (msr == MSR_IA32_MC0_MISC + bank*4)
+        if (msr == MSR_IA32_MCx_MISC(bank))
                 return offsetof(struct mce, misc);
         if (msr == MSR_IA32_MCG_STATUS)
                 return offsetof(struct mce, mcgstatus);
@@ -311,13 +316,25 @@ static int msr_to_offset(u32 msr)
 static u64 mce_rdmsrl(u32 msr)
 {
         u64 v;
+
         if (__get_cpu_var(injectm).finished) {
                 int offset = msr_to_offset(msr);
+
                 if (offset < 0)
                         return 0;
                 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
         }
-        rdmsrl(msr, v);
+
+        if (rdmsrl_safe(msr, &v)) {
+                WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
+                /*
+                 * Return zero in case the access faulted. This should
+                 * not happen normally but can happen if the CPU does
+                 * something weird, or if the code is buggy.
+                 */
+                v = 0;
+        }
+
         return v;
 }
 
@@ -325,6 +342,7 @@ static void mce_wrmsrl(u32 msr, u64 v)
 {
         if (__get_cpu_var(injectm).finished) {
                 int offset = msr_to_offset(msr);
+
                 if (offset >= 0)
                         *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
                 return;
@@ -421,7 +439,7 @@ static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
                 m->ip = mce_rdmsrl(rip_msr);
 }
 
-#ifdef CONFIG_X86_LOCAL_APIC 
+#ifdef CONFIG_X86_LOCAL_APIC
 /*
  * Called after interrupts have been reenabled again
  * when a MCE happened during an interrupts off region
@@ -505,7 +523,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 
         m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
         for (i = 0; i < banks; i++) {
-                if (!bank[i] || !test_bit(i, *b))
+                if (!mce_banks[i].ctl || !test_bit(i, *b))
                         continue;
 
                 m.misc = 0;
@@ -514,7 +532,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 m.tsc = 0;
 
                 barrier();
-                m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
+                m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
                 if (!(m.status & MCI_STATUS_VAL))
                         continue;
 
@@ -529,9 +547,9 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                         continue;
 
                 if (m.status & MCI_STATUS_MISCV)
-                        m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
+                        m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
                 if (m.status & MCI_STATUS_ADDRV)
-                        m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
+                        m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
 
                 if (!(flags & MCP_TIMESTAMP))
                         m.tsc = 0;
@@ -547,7 +565,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 /*
                  * Clear state for this bank.
                  */
-                mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
+                mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
         }
 
         /*
@@ -568,7 +586,7 @@ static int mce_no_way_out(struct mce *m, char **msg)
         int i;
 
         for (i = 0; i < banks; i++) {
-                m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
+                m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
                 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
                         return 1;
         }
@@ -628,7 +646,7 @@ out:
  * This way we prevent any potential data corruption in a unrecoverable case
  * and also makes sure always all CPU's errors are examined.
  *
- * Also this detects the case of an machine check event coming from outer
+ * Also this detects the case of a machine check event coming from outer
  * space (not detected by any CPUs) In this case some external agent wants
  * us to shut down, so panic too.
  *
@@ -681,7 +699,7 @@ static void mce_reign(void)
          * No machine check event found. Must be some external
          * source or one CPU is hung. Panic.
          */
-        if (!m && tolerant < 3)
+        if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
                 mce_panic("Machine check from unknown source", NULL, NULL);
 
         /*
@@ -715,7 +733,7 @@ static int mce_start(int *no_way_out)
          * global_nwo should be updated before mce_callin
          */
         smp_wmb();
-        order = atomic_add_return(1, &mce_callin);
+        order = atomic_inc_return(&mce_callin);
 
         /*
          * Wait for everyone.
@@ -852,7 +870,7 @@ static void mce_clear_state(unsigned long *toclear)
 
         for (i = 0; i < banks; i++) {
                 if (test_bit(i, toclear))
-                        mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
+                        mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
         }
 }
 
@@ -905,11 +923,11 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         mce_setup(&m);
 
         m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
-        no_way_out = mce_no_way_out(&m, &msg);
-
         final = &__get_cpu_var(mces_seen);
         *final = m;
 
+        no_way_out = mce_no_way_out(&m, &msg);
+
         barrier();
 
         /*
@@ -926,14 +944,14 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         order = mce_start(&no_way_out);
         for (i = 0; i < banks; i++) {
                 __clear_bit(i, toclear);
-                if (!bank[i])
+                if (!mce_banks[i].ctl)
                         continue;
 
                 m.misc = 0;
                 m.addr = 0;
                 m.bank = i;
 
-                m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
+                m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
                 if ((m.status & MCI_STATUS_VAL) == 0)
                         continue;
 
@@ -974,9 +992,9 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                         kill_it = 1;
 
                 if (m.status & MCI_STATUS_MISCV)
-                        m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
+                        m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
                 if (m.status & MCI_STATUS_ADDRV)
-                        m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
+                        m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
 
                 /*
                  * Action optional error. Queue address for later processing.
@@ -1101,7 +1119,7 @@ void mce_log_therm_throt_event(__u64 status)
  */
 static int check_interval = 5 * 60; /* 5 minutes */
 
-static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
+static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
 static DEFINE_PER_CPU(struct timer_list, mce_timer);
 
 static void mcheck_timer(unsigned long data)
@@ -1120,7 +1138,7 @@ static void mcheck_timer(unsigned long data)
          * Alert userspace if needed.  If we logged an MCE, reduce the
          * polling interval, otherwise increase the polling interval.
          */
-        n = &__get_cpu_var(next_interval);
+        n = &__get_cpu_var(mce_next_interval);
         if (mce_notify_irq())
                 *n = max(*n/2, HZ/100);
         else
@@ -1169,10 +1187,26 @@ int mce_notify_irq(void)
 }
 EXPORT_SYMBOL_GPL(mce_notify_irq);
 
+static int mce_banks_init(void)
+{
+        int i;
+
+        mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
+        if (!mce_banks)
+                return -ENOMEM;
+        for (i = 0; i < banks; i++) {
+                struct mce_bank *b = &mce_banks[i];
+
+                b->ctl = -1ULL;
+                b->init = 1;
+        }
+        return 0;
+}
+
 /*
  * Initialize Machine Checks for a CPU.
  */
-static int mce_cap_init(void)
+static int __cpuinit mce_cap_init(void)
 {
         unsigned b;
         u64 cap;
@@ -1192,11 +1226,11 @@ static int mce_cap_init(void)
         /* Don't support asymmetric configurations today */
         WARN_ON(banks != 0 && b != banks);
         banks = b;
-        if (!bank) {
-                bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
-                if (!bank)
-                        return -ENOMEM;
-                memset(bank, 0xff, banks * sizeof(u64));
+        if (!mce_banks) {
+                int err = mce_banks_init();
+
+                if (err)
+                        return err;
         }
 
         /* Use accurate RIP reporting if available. */
@@ -1228,15 +1262,17 @@ static void mce_init(void)
                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 
         for (i = 0; i < banks; i++) {
-                if (skip_bank_init(i))
+                struct mce_bank *b = &mce_banks[i];
+
+                if (!b->init)
                         continue;
-                wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
-                wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
+                wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
+                wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
         }
 }
 
 /* Add per CPU specific workarounds here */
-static int mce_cpu_quirks(struct cpuinfo_x86 *c)
+static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
 {
         if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
                 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
@@ -1251,7 +1287,7 @@ static int mce_cpu_quirks(struct cpuinfo_x86 *c)
                          * trips off incorrectly with the IOMMU & 3ware
                          * & Cerberus:
                          */
-                        clear_bit(10, (unsigned long *)&bank[4]);
+                        clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
                 }
                 if (c->x86 <= 17 && mce_bootlog < 0) {
                         /*
@@ -1265,7 +1301,7 @@ static int mce_cpu_quirks(struct cpuinfo_x86 *c)
                  * by default.
                  */
                  if (c->x86 == 6 && banks > 0)
-                        bank[0] = 0;
+                        mce_banks[0].ctl = 0;
         }
 
         if (c->x86_vendor == X86_VENDOR_INTEL) {
@@ -1278,8 +1314,8 @@ static int mce_cpu_quirks(struct cpuinfo_x86 *c)
                  * valid event later, merely don't write CTL0.
                  */
 
-                if (c->x86 == 6 && c->x86_model < 0x1A)
-                        __set_bit(0, &dont_init_banks);
+                if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
+                        mce_banks[0].init = 0;
 
                 /*
                  * All newer Intel systems support MCE broadcasting. Enable
@@ -1335,7 +1371,7 @@ static void mce_cpu_features(struct cpuinfo_x86 *c)
 static void mce_init_timer(void)
 {
         struct timer_list *t = &__get_cpu_var(mce_timer);
-        int *n = &__get_cpu_var(next_interval);
+        int *n = &__get_cpu_var(mce_next_interval);
 
         if (mce_ignore_ce)
                 return;
@@ -1348,6 +1384,17 @@ static void mce_init_timer(void)
         add_timer_on(t, smp_processor_id());
 }
 
+/* Handle unconfigured int18 (should never happen) */
+static void unexpected_machine_check(struct pt_regs *regs, long error_code)
+{
+        printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
+               smp_processor_id());
+}
+
+/* Call the installed machine check handler for this CPU setup. */
+void (*machine_check_vector)(struct pt_regs *, long error_code) =
+                                                unexpected_machine_check;
+
 /*
  * Called for each booted CPU to set up machine checks.
  * Must be called with preempt off:
@@ -1561,8 +1608,10 @@ static struct miscdevice mce_log_device = {
  */
 static int __init mcheck_enable(char *str)
 {
-        if (*str == 0)
+        if (*str == 0) {
                 enable_p5_mce();
+                return 1;
+        }
         if (*str == '=')
                 str++;
         if (!strcmp(str, "off"))
@@ -1603,8 +1652,10 @@ static int mce_disable(void)
         int i;
 
         for (i = 0; i < banks; i++) {
-                if (!skip_bank_init(i))
-                        wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
+                struct mce_bank *b = &mce_banks[i];
+
+                if (b->init)
+                        wrmsrl(MSR_IA32_MCx_CTL(i), 0);
         }
         return 0;
 }
@@ -1679,14 +1730,15 @@ DEFINE_PER_CPU(struct sys_device, mce_dev);
 __cpuinitdata
 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
-static struct sysdev_attribute *bank_attrs;
+static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
+{
+        return container_of(attr, struct mce_bank, attr);
+}
 
 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
                          char *buf)
 {
-        u64 b = bank[attr - bank_attrs];
-
-        return sprintf(buf, "%llx\n", b);
+        return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
 }
 
 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
@@ -1697,7 +1749,7 @@ static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
         if (strict_strtoull(buf, 0, &new) < 0)
                 return -EINVAL;
 
-        bank[attr - bank_attrs] = new;
+        attr_to_bank(attr)->ctl = new;
         mce_restart();
 
         return size;
@@ -1839,7 +1891,7 @@ static __cpuinit int mce_create_device(unsigned int cpu)
         }
         for (j = 0; j < banks; j++) {
                 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
-                                        &bank_attrs[j]);
+                                        &mce_banks[j].attr);
                 if (err)
                         goto error2;
         }
@@ -1848,10 +1900,10 @@ static __cpuinit int mce_create_device(unsigned int cpu)
         return 0;
 error2:
         while (--j >= 0)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[j]);
+                sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
 error:
         while (--i >= 0)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
+                sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
 
         sysdev_unregister(&per_cpu(mce_dev, cpu));
 
@@ -1869,7 +1921,7 @@ static __cpuinit void mce_remove_device(unsigned int cpu)
                 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
 
         for (i = 0; i < banks; i++)
-                sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
+                sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
 
         sysdev_unregister(&per_cpu(mce_dev, cpu));
         cpumask_clear_cpu(cpu, mce_dev_initialized);
@@ -1886,8 +1938,10 @@ static void mce_disable_cpu(void *h)
         if (!(action & CPU_TASKS_FROZEN))
                 cmci_clear();
         for (i = 0; i < banks; i++) {
-                if (!skip_bank_init(i))
-                        wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
+                struct mce_bank *b = &mce_banks[i];
+
+                if (b->init)
+                        wrmsrl(MSR_IA32_MCx_CTL(i), 0);
         }
 }
 
@@ -1902,8 +1956,10 @@ static void mce_reenable_cpu(void *h)
         if (!(action & CPU_TASKS_FROZEN))
                 cmci_reenable();
         for (i = 0; i < banks; i++) {
-                if (!skip_bank_init(i))
-                        wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
+                struct mce_bank *b = &mce_banks[i];
+
+                if (b->init)
+                        wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
         }
 }
 
@@ -1935,7 +1991,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
         case CPU_DOWN_FAILED:
         case CPU_DOWN_FAILED_FROZEN:
                 t->expires = round_jiffies(jiffies +
-                                                __get_cpu_var(next_interval));
+                                           __get_cpu_var(mce_next_interval));
                 add_timer_on(t, cpu);
                 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
                 break;
@@ -1951,35 +2007,21 @@ static struct notifier_block mce_cpu_notifier __cpuinitdata = {
         .notifier_call = mce_cpu_callback,
 };
 
-static __init int mce_init_banks(void)
+static __init void mce_init_banks(void)
 {
         int i;
 
-        bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
-                                GFP_KERNEL);
-        if (!bank_attrs)
-                return -ENOMEM;
-
         for (i = 0; i < banks; i++) {
-                struct sysdev_attribute *a = &bank_attrs[i];
+                struct mce_bank *b = &mce_banks[i];
+                struct sysdev_attribute *a = &b->attr;
 
-                a->attr.name    = kasprintf(GFP_KERNEL, "bank%d", i);
-                if (!a->attr.name)
-                        goto nomem;
+                a->attr.name    = b->attrname;
+                snprintf(b->attrname, ATTR_LEN, "bank%d", i);
 
                 a->attr.mode    = 0644;
                 a->show         = show_bank;
                 a->store        = set_bank;
         }
-        return 0;
-
-nomem:
-        while (--i >= 0)
-                kfree(bank_attrs[i].attr.name);
-        kfree(bank_attrs);
-        bank_attrs = NULL;
-
-        return -ENOMEM;
 }
 
 static __init int mce_init_device(void)
@@ -1992,9 +2034,7 @@ static __init int mce_init_device(void)
 
         zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
 
-        err = mce_init_banks();
-        if (err)
-                return err;
+        mce_init_banks();
 
         err = sysdev_class_register(&mce_sysclass);
         if (err)
@@ -2014,57 +2054,65 @@ static __init int mce_init_device(void)
 
 device_initcall(mce_init_device);
 
-#else /* CONFIG_X86_OLD_MCE: */
-
-int nr_mce_banks;
-EXPORT_SYMBOL_GPL(nr_mce_banks);        /* non-fatal.o */
+/*
+ * Old style boot options parsing. Only for compatibility.
+ */
+static int __init mcheck_disable(char *str)
+{
+        mce_disabled = 1;
+        return 1;
+}
+__setup("nomce", mcheck_disable);
 
-/* This has to be run for each processor */
-void mcheck_init(struct cpuinfo_x86 *c)
+#ifdef CONFIG_DEBUG_FS
+struct dentry *mce_get_debugfs_dir(void)
 {
-        if (mce_disabled)
-                return;
+        static struct dentry *dmce;
 
-        switch (c->x86_vendor) {
-        case X86_VENDOR_AMD:
-                amd_mcheck_init(c);
-                break;
+        if (!dmce)
+                dmce = debugfs_create_dir("mce", NULL);
 
-        case X86_VENDOR_INTEL:
-                if (c->x86 == 5)
-                        intel_p5_mcheck_init(c);
-                if (c->x86 == 6)
-                        intel_p6_mcheck_init(c);
-                if (c->x86 == 15)
-                        intel_p4_mcheck_init(c);
-                break;
+        return dmce;
+}
 
-        case X86_VENDOR_CENTAUR:
-                if (c->x86 == 5)
-                        winchip_mcheck_init(c);
-                break;
+static void mce_reset(void)
+{
+        cpu_missing = 0;
+        atomic_set(&mce_fake_paniced, 0);
+        atomic_set(&mce_executing, 0);
+        atomic_set(&mce_callin, 0);
+        atomic_set(&global_nwo, 0);
+}
 
-        default:
-                break;
-        }
-        printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
+static int fake_panic_get(void *data, u64 *val)
+{
+        *val = fake_panic;
+        return 0;
 }
 
-static int __init mcheck_enable(char *str)
+static int fake_panic_set(void *data, u64 val)
 {
-        mce_p5_enabled = 1;
-        return 1;
+        mce_reset();
+        fake_panic = val;
+        return 0;
 }
-__setup("mce", mcheck_enable);
 
-#endif /* CONFIG_X86_OLD_MCE */
+DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
+                        fake_panic_set, "%llu\n");
 
-/*
- * Old style boot options parsing. Only for compatibility.
- */
-static int __init mcheck_disable(char *str)
+static int __init mce_debugfs_init(void)
 {
-        mce_disabled = 1;
-        return 1;
+        struct dentry *dmce, *ffake_panic;
+
+        dmce = mce_get_debugfs_dir();
+        if (!dmce)
+                return -ENOMEM;
+        ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
+                                          &fake_panic_fops);
+        if (!ffake_panic)
+                return -ENOMEM;
+
+        return 0;
 }
-__setup("nomce", mcheck_disable);
+late_initcall(mce_debugfs_init);
+#endif