1 files changed, 30 insertions, 27 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5cd9bfabd645..a80029035bf2 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -31,11 +31,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
         /* Unmask CPUID levels if masked: */
         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
-                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-
-                if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
-                        misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
-                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
                         c->cpuid_level = cpuid_eax(0);
                         get_cpu_cap(c);
                 }
@@ -129,16 +126,10 @@ static void early_init_intel(struct cpuinfo_x86 *c)
          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
          * (model 2) with the same problem.
          */
-        if (c->x86 == 15) {
-                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-
-                if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
-                        printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
-
-                        misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
-                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-                }
-        }
+        if (c->x86 == 15)
+                if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
+                                  MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
+                        pr_info("kmemcheck: Disabling fast string operations\n");
 #endif
 
         /*
@@ -195,10 +186,16 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
         }
 }
 
-static void intel_workarounds(struct cpuinfo_x86 *c)
+static int forcepae;
+static int __init forcepae_setup(char *__unused)
 {
-        unsigned long lo, hi;
+        forcepae = 1;
+        return 1;
+}
+__setup("forcepae", forcepae_setup);
 
+static void intel_workarounds(struct cpuinfo_x86 *c)
+{
 #ifdef CONFIG_X86_F00F_BUG
         /*
          * All current models of Pentium and Pentium with MMX technology CPUs
@@ -225,16 +222,26 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
                 clear_cpu_cap(c, X86_FEATURE_SEP);
 
         /*
+         * PAE CPUID issue: many Pentium M report no PAE but may have a
+         * functionally usable PAE implementation.
+         * Forcefully enable PAE if kernel parameter "forcepae" is present.
+         */
+        if (forcepae) {
+                printk(KERN_WARNING "PAE forced!\n");
+                set_cpu_cap(c, X86_FEATURE_PAE);
+                add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
+        }
+
+        /*
          * P4 Xeon errata 037 workaround.
          * Hardware prefetcher may cause stale data to be loaded into the cache.
          */
         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-                rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
-                if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
-                        printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
-                        printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
-                        wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
+                if (msr_set_bit(MSR_IA32_MISC_ENABLE,
+                                MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
+                    > 0) {
+                        pr_info("CPU: C0 stepping P4 Xeon detected.\n");
+                        pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
                 }
         }
 
@@ -267,10 +274,6 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
         }
 #endif
 
-#ifdef CONFIG_X86_NUMAQ
-        numaq_tsc_disable();
-#endif
-
         intel_smp_check(c);
 }
 #else