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Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 3db61c644e44..5cd9bfabd645 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -640,21 +640,17 @@ static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
640 case 0x61d: /* six-core 45 nm xeon "Dunnington" */ 640 case 0x61d: /* six-core 45 nm xeon "Dunnington" */
641 tlb_flushall_shift = -1; 641 tlb_flushall_shift = -1;
642 break; 642 break;
643 case 0x63a: /* Ivybridge */
644 tlb_flushall_shift = 2;
645 break;
643 case 0x61a: /* 45 nm nehalem, "Bloomfield" */ 646 case 0x61a: /* 45 nm nehalem, "Bloomfield" */
644 case 0x61e: /* 45 nm nehalem, "Lynnfield" */ 647 case 0x61e: /* 45 nm nehalem, "Lynnfield" */
645 case 0x625: /* 32 nm nehalem, "Clarkdale" */ 648 case 0x625: /* 32 nm nehalem, "Clarkdale" */
646 case 0x62c: /* 32 nm nehalem, "Gulftown" */ 649 case 0x62c: /* 32 nm nehalem, "Gulftown" */
647 case 0x62e: /* 45 nm nehalem-ex, "Beckton" */ 650 case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
648 case 0x62f: /* 32 nm Xeon E7 */ 651 case 0x62f: /* 32 nm Xeon E7 */
649 tlb_flushall_shift = 6;
650 break;
651 case 0x62a: /* SandyBridge */ 652 case 0x62a: /* SandyBridge */
652 case 0x62d: /* SandyBridge, "Romely-EP" */ 653 case 0x62d: /* SandyBridge, "Romely-EP" */
653 tlb_flushall_shift = 5;
654 break;
655 case 0x63a: /* Ivybridge */
656 tlb_flushall_shift = 1;
657 break;
658 default: 654 default:
659 tlb_flushall_shift = 6; 655 tlb_flushall_shift = 6;
660 } 656 }