diff options
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 1a89a2b68d15..7437fa133c02 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <asm/uaccess.h> | 14 | #include <asm/uaccess.h> |
| 15 | #include <asm/ds.h> | 15 | #include <asm/ds.h> |
| 16 | #include <asm/bugs.h> | 16 | #include <asm/bugs.h> |
| 17 | #include <asm/cpu.h> | ||
| 17 | 18 | ||
| 18 | #ifdef CONFIG_X86_64 | 19 | #ifdef CONFIG_X86_64 |
| 19 | #include <asm/topology.h> | 20 | #include <asm/topology.h> |
| @@ -54,6 +55,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) | |||
| 54 | c->x86_cache_alignment = 128; | 55 | c->x86_cache_alignment = 128; |
| 55 | #endif | 56 | #endif |
| 56 | 57 | ||
| 58 | /* CPUID workaround for 0F33/0F34 CPU */ | ||
| 59 | if (c->x86 == 0xF && c->x86_model == 0x3 | ||
| 60 | && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) | ||
| 61 | c->x86_phys_bits = 36; | ||
| 62 | |||
| 57 | /* | 63 | /* |
| 58 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | 64 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate |
| 59 | * with P/T states and does not stop in deep C-states. | 65 | * with P/T states and does not stop in deep C-states. |
| @@ -116,6 +122,28 @@ static void __cpuinit trap_init_f00f_bug(void) | |||
| 116 | } | 122 | } |
| 117 | #endif | 123 | #endif |
| 118 | 124 | ||
| 125 | static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) | ||
| 126 | { | ||
| 127 | #ifdef CONFIG_SMP | ||
| 128 | /* calling is from identify_secondary_cpu() ? */ | ||
| 129 | if (c->cpu_index == boot_cpu_id) | ||
| 130 | return; | ||
| 131 | |||
| 132 | /* | ||
| 133 | * Mask B, Pentium, but not Pentium MMX | ||
| 134 | */ | ||
| 135 | if (c->x86 == 5 && | ||
| 136 | c->x86_mask >= 1 && c->x86_mask <= 4 && | ||
| 137 | c->x86_model <= 3) { | ||
| 138 | /* | ||
| 139 | * Remember we have B step Pentia with bugs | ||
| 140 | */ | ||
| 141 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | ||
| 142 | "with B stepping processors.\n"); | ||
| 143 | } | ||
| 144 | #endif | ||
| 145 | } | ||
| 146 | |||
| 119 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | 147 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
| 120 | { | 148 | { |
| 121 | unsigned long lo, hi; | 149 | unsigned long lo, hi; |
| @@ -192,6 +220,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | |||
| 192 | #ifdef CONFIG_X86_NUMAQ | 220 | #ifdef CONFIG_X86_NUMAQ |
| 193 | numaq_tsc_disable(); | 221 | numaq_tsc_disable(); |
| 194 | #endif | 222 | #endif |
| 223 | |||
| 224 | intel_smp_check(c); | ||
| 195 | } | 225 | } |
| 196 | #else | 226 | #else |
| 197 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | 227 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
| @@ -391,7 +421,7 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned i | |||
| 391 | } | 421 | } |
| 392 | #endif | 422 | #endif |
| 393 | 423 | ||
| 394 | static struct cpu_dev intel_cpu_dev __cpuinitdata = { | 424 | static const struct cpu_dev __cpuinitconst intel_cpu_dev = { |
| 395 | .c_vendor = "Intel", | 425 | .c_vendor = "Intel", |
| 396 | .c_ident = { "GenuineIntel" }, | 426 | .c_ident = { "GenuineIntel" }, |
| 397 | #ifdef CONFIG_X86_32 | 427 | #ifdef CONFIG_X86_32 |
