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diff --git a/arch/x86/kernel/cpu/cpufreq/longhaul.c b/arch/x86/kernel/cpu/cpufreq/longhaul.c
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1/*
2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
7 *
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is backward compatible with v1, but adds
12 * LONGHAUL MSR for purpose of both frequency and voltage scaling.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14 * Version 3 of longhaul got renamed to Powersaver and redesigned
15 * to use only the POWERSAVER MSR at 0x110a.
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17 * It's pretty much the same feature wise to longhaul v2, though
18 * there is provision for scaling FSB too, but this doesn't work
19 * too well in practice so we don't even try to use this.
20 *
21 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/cpufreq.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/string.h>
32#include <linux/delay.h>
33
34#include <asm/msr.h>
35#include <asm/timex.h>
36#include <asm/io.h>
37#include <asm/acpi.h>
38#include <linux/acpi.h>
39#include <acpi/processor.h>
40
41#include "longhaul.h"
42
43#define PFX "longhaul: "
44
45#define TYPE_LONGHAUL_V1 1
46#define TYPE_LONGHAUL_V2 2
47#define TYPE_POWERSAVER 3
48
49#define CPU_SAMUEL 1
50#define CPU_SAMUEL2 2
51#define CPU_EZRA 3
52#define CPU_EZRA_T 4
53#define CPU_NEHEMIAH 5
54#define CPU_NEHEMIAH_C 6
55
56/* Flags */
57#define USE_ACPI_C3 (1 << 1)
58#define USE_NORTHBRIDGE (1 << 2)
59
60static int cpu_model;
61static unsigned int numscales=16;
62static unsigned int fsb;
63
64static const struct mV_pos *vrm_mV_table;
65static const unsigned char *mV_vrm_table;
66
67static unsigned int highest_speed, lowest_speed; /* kHz */
68static unsigned int minmult, maxmult;
69static int can_scale_voltage;
70static struct acpi_processor *pr = NULL;
71static struct acpi_processor_cx *cx = NULL;
72static u32 acpi_regs_addr;
73static u8 longhaul_flags;
74static unsigned int longhaul_index;
75
76/* Module parameters */
77static int scale_voltage;
78static int disable_acpi_c3;
79static int revid_errata;
80
81#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
82
83
84/* Clock ratios multiplied by 10 */
85static int clock_ratio[32];
86static int eblcr_table[32];
87static int longhaul_version;
88static struct cpufreq_frequency_table *longhaul_table;
89
90#ifdef CONFIG_CPU_FREQ_DEBUG
91static char speedbuffer[8];
92
93static char *print_speed(int speed)
94{
95 if (speed < 1000) {
96 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
97 return speedbuffer;
98 }
99
100 if (speed%1000 == 0)
101 snprintf(speedbuffer, sizeof(speedbuffer),
102 "%dGHz", speed/1000);
103 else
104 snprintf(speedbuffer, sizeof(speedbuffer),
105 "%d.%dGHz", speed/1000, (speed%1000)/100);
106
107 return speedbuffer;
108}
109#endif
110
111
112static unsigned int calc_speed(int mult)
113{
114 int khz;
115 khz = (mult/10)*fsb;
116 if (mult%10)
117 khz += fsb/2;
118 khz *= 1000;
119 return khz;
120}
121
122
123static int longhaul_get_cpu_mult(void)
124{
125 unsigned long invalue=0,lo, hi;
126
127 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
128 invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
129 if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
130 if (lo & (1<<27))
131 invalue+=16;
132 }
133 return eblcr_table[invalue];
134}
135
136/* For processor with BCR2 MSR */
137
138static void do_longhaul1(unsigned int clock_ratio_index)
139{
140 union msr_bcr2 bcr2;
141
142 rdmsrl(MSR_VIA_BCR2, bcr2.val);
143 /* Enable software clock multiplier */
144 bcr2.bits.ESOFTBF = 1;
145 bcr2.bits.CLOCKMUL = clock_ratio_index & 0xff;
146
147 /* Sync to timer tick */
148 safe_halt();
149 /* Change frequency on next halt or sleep */
150 wrmsrl(MSR_VIA_BCR2, bcr2.val);
151 /* Invoke transition */
152 ACPI_FLUSH_CPU_CACHE();
153 halt();
154
155 /* Disable software clock multiplier */
156 local_irq_disable();
157 rdmsrl(MSR_VIA_BCR2, bcr2.val);
158 bcr2.bits.ESOFTBF = 0;
159 wrmsrl(MSR_VIA_BCR2, bcr2.val);
160}
161
162/* For processor with Longhaul MSR */
163
164static void do_powersaver(int cx_address, unsigned int clock_ratio_index,
165 unsigned int dir)
166{
167 union msr_longhaul longhaul;
168 u32 t;
169
170 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
171 /* Setup new frequency */
172 if (!revid_errata)
173 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
174 else
175 longhaul.bits.RevisionKey = 0;
176 longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
177 longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
178 /* Setup new voltage */
179 if (can_scale_voltage)
180 longhaul.bits.SoftVID = (clock_ratio_index >> 8) & 0x1f;
181 /* Sync to timer tick */
182 safe_halt();
183 /* Raise voltage if necessary */
184 if (can_scale_voltage && dir) {
185 longhaul.bits.EnableSoftVID = 1;
186 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
187 /* Change voltage */
188 if (!cx_address) {
189 ACPI_FLUSH_CPU_CACHE();
190 halt();
191 } else {
192 ACPI_FLUSH_CPU_CACHE();
193 /* Invoke C3 */
194 inb(cx_address);
195 /* Dummy op - must do something useless after P_LVL3
196 * read */
197 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
198 }
199 longhaul.bits.EnableSoftVID = 0;
200 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
201 }
202
203 /* Change frequency on next halt or sleep */
204 longhaul.bits.EnableSoftBusRatio = 1;
205 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
206 if (!cx_address) {
207 ACPI_FLUSH_CPU_CACHE();
208 halt();
209 } else {
210 ACPI_FLUSH_CPU_CACHE();
211 /* Invoke C3 */
212 inb(cx_address);
213 /* Dummy op - must do something useless after P_LVL3 read */
214 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
215 }
216 /* Disable bus ratio bit */
217 longhaul.bits.EnableSoftBusRatio = 0;
218 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
219
220 /* Reduce voltage if necessary */
221 if (can_scale_voltage && !dir) {
222 longhaul.bits.EnableSoftVID = 1;
223 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
224 /* Change voltage */
225 if (!cx_address) {
226 ACPI_FLUSH_CPU_CACHE();
227 halt();
228 } else {
229 ACPI_FLUSH_CPU_CACHE();
230 /* Invoke C3 */
231 inb(cx_address);
232 /* Dummy op - must do something useless after P_LVL3
233 * read */
234 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
235 }
236 longhaul.bits.EnableSoftVID = 0;
237 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
238 }
239}
240
241/**
242 * longhaul_set_cpu_frequency()
243 * @clock_ratio_index : bitpattern of the new multiplier.
244 *
245 * Sets a new clock ratio.
246 */
247
248static void longhaul_setstate(unsigned int table_index)
249{
250 unsigned int clock_ratio_index;
251 int speed, mult;
252 struct cpufreq_freqs freqs;
253 unsigned long flags;
254 unsigned int pic1_mask, pic2_mask;
255 u16 bm_status = 0;
256 u32 bm_timeout = 1000;
257 unsigned int dir = 0;
258
259 clock_ratio_index = longhaul_table[table_index].index;
260 /* Safety precautions */
261 mult = clock_ratio[clock_ratio_index & 0x1f];
262 if (mult == -1)
263 return;
264 speed = calc_speed(mult);
265 if ((speed > highest_speed) || (speed < lowest_speed))
266 return;
267 /* Voltage transition before frequency transition? */
268 if (can_scale_voltage && longhaul_index < table_index)
269 dir = 1;
270
271 freqs.old = calc_speed(longhaul_get_cpu_mult());
272 freqs.new = speed;
273 freqs.cpu = 0; /* longhaul.c is UP only driver */
274
275 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
276
277 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
278 fsb, mult/10, mult%10, print_speed(speed/1000));
279retry_loop:
280 preempt_disable();
281 local_irq_save(flags);
282
283 pic2_mask = inb(0xA1);
284 pic1_mask = inb(0x21); /* works on C3. save mask. */
285 outb(0xFF,0xA1); /* Overkill */
286 outb(0xFE,0x21); /* TMR0 only */
287
288 /* Wait while PCI bus is busy. */
289 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
290 || ((pr != NULL) && pr->flags.bm_control))) {
291 bm_status = inw(acpi_regs_addr);
292 bm_status &= 1 << 4;
293 while (bm_status && bm_timeout) {
294 outw(1 << 4, acpi_regs_addr);
295 bm_timeout--;
296 bm_status = inw(acpi_regs_addr);
297 bm_status &= 1 << 4;
298 }
299 }
300
301 if (longhaul_flags & USE_NORTHBRIDGE) {
302 /* Disable AGP and PCI arbiters */
303 outb(3, 0x22);
304 } else if ((pr != NULL) && pr->flags.bm_control) {
305 /* Disable bus master arbitration */
306 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
307 }
308 switch (longhaul_version) {
309
310 /*
311 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
312 * Software controlled multipliers only.
313 */
314 case TYPE_LONGHAUL_V1:
315 do_longhaul1(clock_ratio_index);
316 break;
317
318 /*
319 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
320 *
321 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
322 * Nehemiah can do FSB scaling too, but this has never been proven
323 * to work in practice.
324 */
325 case TYPE_LONGHAUL_V2:
326 case TYPE_POWERSAVER:
327 if (longhaul_flags & USE_ACPI_C3) {
328 /* Don't allow wakeup */
329 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
330 do_powersaver(cx->address, clock_ratio_index, dir);
331 } else {
332 do_powersaver(0, clock_ratio_index, dir);
333 }
334 break;
335 }
336
337 if (longhaul_flags & USE_NORTHBRIDGE) {
338 /* Enable arbiters */
339 outb(0, 0x22);
340 } else if ((pr != NULL) && pr->flags.bm_control) {
341 /* Enable bus master arbitration */
342 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
343 }
344 outb(pic2_mask,0xA1); /* restore mask */
345 outb(pic1_mask,0x21);
346
347 local_irq_restore(flags);
348 preempt_enable();
349
350 freqs.new = calc_speed(longhaul_get_cpu_mult());
351 /* Check if requested frequency is set. */
352 if (unlikely(freqs.new != speed)) {
353 printk(KERN_INFO PFX "Failed to set requested frequency!\n");
354 /* Revision ID = 1 but processor is expecting revision key
355 * equal to 0. Jumpers at the bottom of processor will change
356 * multiplier and FSB, but will not change bits in Longhaul
357 * MSR nor enable voltage scaling. */
358 if (!revid_errata) {
359 printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
360 "option.\n");
361 revid_errata = 1;
362 msleep(200);
363 goto retry_loop;
364 }
365 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
366 * But it does happen. Processor is entering ACPI C3 state,
367 * but it doesn't change frequency. I tried poking various
368 * bits in northbridge registers, but without success. */
369 if (longhaul_flags & USE_ACPI_C3) {
370 printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
371 longhaul_flags &= ~USE_ACPI_C3;
372 if (revid_errata) {
373 printk(KERN_INFO PFX "Disabling \"Ignore "
374 "Revision ID\" option.\n");
375 revid_errata = 0;
376 }
377 msleep(200);
378 goto retry_loop;
379 }
380 /* This shouldn't happen. Longhaul ver. 2 was reported not
381 * working on processors without voltage scaling, but with
382 * RevID = 1. RevID errata will make things right. Just
383 * to be 100% sure. */
384 if (longhaul_version == TYPE_LONGHAUL_V2) {
385 printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
386 longhaul_version = TYPE_LONGHAUL_V1;
387 msleep(200);
388 goto retry_loop;
389 }
390 }
391 /* Report true CPU frequency */
392 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
393
394 if (!bm_timeout)
395 printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n");
396}
397
398/*
399 * Centaur decided to make life a little more tricky.
400 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
401 * Samuel2 and above have to try and guess what the FSB is.
402 * We do this by assuming we booted at maximum multiplier, and interpolate
403 * between that value multiplied by possible FSBs and cpu_mhz which
404 * was calculated at boot time. Really ugly, but no other way to do this.
405 */
406
407#define ROUNDING 0xf
408
409static int guess_fsb(int mult)
410{
411 int speed = cpu_khz / 1000;
412 int i;
413 int speeds[] = { 666, 1000, 1333, 2000 };
414 int f_max, f_min;
415
416 for (i = 0; i < 4; i++) {
417 f_max = ((speeds[i] * mult) + 50) / 100;
418 f_max += (ROUNDING / 2);
419 f_min = f_max - ROUNDING;
420 if ((speed <= f_max) && (speed >= f_min))
421 return speeds[i] / 10;
422 }
423 return 0;
424}
425
426
427static int __init longhaul_get_ranges(void)
428{
429 unsigned int i, j, k = 0;
430 unsigned int ratio;
431 int mult;
432
433 /* Get current frequency */
434 mult = longhaul_get_cpu_mult();
435 if (mult == -1) {
436 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
437 return -EINVAL;
438 }
439 fsb = guess_fsb(mult);
440 if (fsb == 0) {
441 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
442 return -EINVAL;
443 }
444 /* Get max multiplier - as we always did.
445 * Longhaul MSR is usefull only when voltage scaling is enabled.
446 * C3 is booting at max anyway. */
447 maxmult = mult;
448 /* Get min multiplier */
449 switch (cpu_model) {
450 case CPU_NEHEMIAH:
451 minmult = 50;
452 break;
453 case CPU_NEHEMIAH_C:
454 minmult = 40;
455 break;
456 default:
457 minmult = 30;
458 break;
459 }
460
461 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
462 minmult/10, minmult%10, maxmult/10, maxmult%10);
463
464 highest_speed = calc_speed(maxmult);
465 lowest_speed = calc_speed(minmult);
466 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
467 print_speed(lowest_speed/1000),
468 print_speed(highest_speed/1000));
469
470 if (lowest_speed == highest_speed) {
471 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
472 return -EINVAL;
473 }
474 if (lowest_speed > highest_speed) {
475 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
476 lowest_speed, highest_speed);
477 return -EINVAL;
478 }
479
480 longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
481 if(!longhaul_table)
482 return -ENOMEM;
483
484 for (j = 0; j < numscales; j++) {
485 ratio = clock_ratio[j];
486 if (ratio == -1)
487 continue;
488 if (ratio > maxmult || ratio < minmult)
489 continue;
490 longhaul_table[k].frequency = calc_speed(ratio);
491 longhaul_table[k].index = j;
492 k++;
493 }
494 if (k <= 1) {
495 kfree(longhaul_table);
496 return -ENODEV;
497 }
498 /* Sort */
499 for (j = 0; j < k - 1; j++) {
500 unsigned int min_f, min_i;
501 min_f = longhaul_table[j].frequency;
502 min_i = j;
503 for (i = j + 1; i < k; i++) {
504 if (longhaul_table[i].frequency < min_f) {
505 min_f = longhaul_table[i].frequency;
506 min_i = i;
507 }
508 }
509 if (min_i != j) {
510 unsigned int temp;
511 temp = longhaul_table[j].frequency;
512 longhaul_table[j].frequency = longhaul_table[min_i].frequency;
513 longhaul_table[min_i].frequency = temp;
514 temp = longhaul_table[j].index;
515 longhaul_table[j].index = longhaul_table[min_i].index;
516 longhaul_table[min_i].index = temp;
517 }
518 }
519
520 longhaul_table[k].frequency = CPUFREQ_TABLE_END;
521
522 /* Find index we are running on */
523 for (j = 0; j < k; j++) {
524 if (clock_ratio[longhaul_table[j].index & 0x1f] == mult) {
525 longhaul_index = j;
526 break;
527 }
528 }
529 return 0;
530}
531
532
533static void __init longhaul_setup_voltagescaling(void)
534{
535 union msr_longhaul longhaul;
536 struct mV_pos minvid, maxvid, vid;
537 unsigned int j, speed, pos, kHz_step, numvscales;
538 int min_vid_speed;
539
540 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
541 if (!(longhaul.bits.RevisionID & 1)) {
542 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
543 return;
544 }
545
546 if (!longhaul.bits.VRMRev) {
547 printk(KERN_INFO PFX "VRM 8.5\n");
548 vrm_mV_table = &vrm85_mV[0];
549 mV_vrm_table = &mV_vrm85[0];
550 } else {
551 printk(KERN_INFO PFX "Mobile VRM\n");
552 if (cpu_model < CPU_NEHEMIAH)
553 return;
554 vrm_mV_table = &mobilevrm_mV[0];
555 mV_vrm_table = &mV_mobilevrm[0];
556 }
557
558 minvid = vrm_mV_table[longhaul.bits.MinimumVID];
559 maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
560
561 if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
562 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
563 "Voltage scaling disabled.\n",
564 minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
565 return;
566 }
567
568 if (minvid.mV == maxvid.mV) {
569 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
570 "both %d.%03d. Voltage scaling disabled\n",
571 maxvid.mV/1000, maxvid.mV%1000);
572 return;
573 }
574
575 /* How many voltage steps */
576 numvscales = maxvid.pos - minvid.pos + 1;
577 printk(KERN_INFO PFX
578 "Max VID=%d.%03d "
579 "Min VID=%d.%03d, "
580 "%d possible voltage scales\n",
581 maxvid.mV/1000, maxvid.mV%1000,
582 minvid.mV/1000, minvid.mV%1000,
583 numvscales);
584
585 /* Calculate max frequency at min voltage */
586 j = longhaul.bits.MinMHzBR;
587 if (longhaul.bits.MinMHzBR4)
588 j += 16;
589 min_vid_speed = eblcr_table[j];
590 if (min_vid_speed == -1)
591 return;
592 switch (longhaul.bits.MinMHzFSB) {
593 case 0:
594 min_vid_speed *= 13333;
595 break;
596 case 1:
597 min_vid_speed *= 10000;
598 break;
599 case 3:
600 min_vid_speed *= 6666;
601 break;
602 default:
603 return;
604 break;
605 }
606 if (min_vid_speed >= highest_speed)
607 return;
608 /* Calculate kHz for one voltage step */
609 kHz_step = (highest_speed - min_vid_speed) / numvscales;
610
611 j = 0;
612 while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
613 speed = longhaul_table[j].frequency;
614 if (speed > min_vid_speed)
615 pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
616 else
617 pos = minvid.pos;
618 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
619 vid = vrm_mV_table[mV_vrm_table[pos]];
620 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", speed, j, vid.mV);
621 j++;
622 }
623
624 can_scale_voltage = 1;
625 printk(KERN_INFO PFX "Voltage scaling enabled.\n");
626}
627
628
629static int longhaul_verify(struct cpufreq_policy *policy)
630{
631 return cpufreq_frequency_table_verify(policy, longhaul_table);
632}
633
634
635static int longhaul_target(struct cpufreq_policy *policy,
636 unsigned int target_freq, unsigned int relation)
637{
638 unsigned int table_index = 0;
639 unsigned int i;
640 unsigned int dir = 0;
641 u8 vid, current_vid;
642
643 if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
644 return -EINVAL;
645
646 /* Don't set same frequency again */
647 if (longhaul_index == table_index)
648 return 0;
649
650 if (!can_scale_voltage)
651 longhaul_setstate(table_index);
652 else {
653 /* On test system voltage transitions exceeding single
654 * step up or down were turning motherboard off. Both
655 * "ondemand" and "userspace" are unsafe. C7 is doing
656 * this in hardware, C3 is old and we need to do this
657 * in software. */
658 i = longhaul_index;
659 current_vid = (longhaul_table[longhaul_index].index >> 8) & 0x1f;
660 if (table_index > longhaul_index)
661 dir = 1;
662 while (i != table_index) {
663 vid = (longhaul_table[i].index >> 8) & 0x1f;
664 if (vid != current_vid) {
665 longhaul_setstate(i);
666 current_vid = vid;
667 msleep(200);
668 }
669 if (dir)
670 i++;
671 else
672 i--;
673 }
674 longhaul_setstate(table_index);
675 }
676 longhaul_index = table_index;
677 return 0;
678}
679
680
681static unsigned int longhaul_get(unsigned int cpu)
682{
683 if (cpu)
684 return 0;
685 return calc_speed(longhaul_get_cpu_mult());
686}
687
688static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
689 u32 nesting_level,
690 void *context, void **return_value)
691{
692 struct acpi_device *d;
693
694 if ( acpi_bus_get_device(obj_handle, &d) ) {
695 return 0;
696 }
697 *return_value = (void *)acpi_driver_data(d);
698 return 1;
699}
700
701/* VIA don't support PM2 reg, but have something similar */
702static int enable_arbiter_disable(void)
703{
704 struct pci_dev *dev;
705 int status = 1;
706 int reg;
707 u8 pci_cmd;
708
709 /* Find PLE133 host bridge */
710 reg = 0x78;
711 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
712 NULL);
713 /* Find CLE266 host bridge */
714 if (dev == NULL) {
715 reg = 0x76;
716 dev = pci_get_device(PCI_VENDOR_ID_VIA,
717 PCI_DEVICE_ID_VIA_862X_0, NULL);
718 /* Find CN400 V-Link host bridge */
719 if (dev == NULL)
720 dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
721 }
722 if (dev != NULL) {
723 /* Enable access to port 0x22 */
724 pci_read_config_byte(dev, reg, &pci_cmd);
725 if (!(pci_cmd & 1<<7)) {
726 pci_cmd |= 1<<7;
727 pci_write_config_byte(dev, reg, pci_cmd);
728 pci_read_config_byte(dev, reg, &pci_cmd);
729 if (!(pci_cmd & 1<<7)) {
730 printk(KERN_ERR PFX
731 "Can't enable access to port 0x22.\n");
732 status = 0;
733 }
734 }
735 pci_dev_put(dev);
736 return status;
737 }
738 return 0;
739}
740
741static int longhaul_setup_southbridge(void)
742{
743 struct pci_dev *dev;
744 u8 pci_cmd;
745
746 /* Find VT8235 southbridge */
747 dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
748 if (dev == NULL)
749 /* Find VT8237 southbridge */
750 dev = pci_get_device(PCI_VENDOR_ID_VIA,
751 PCI_DEVICE_ID_VIA_8237, NULL);
752 if (dev != NULL) {
753 /* Set transition time to max */
754 pci_read_config_byte(dev, 0xec, &pci_cmd);
755 pci_cmd &= ~(1 << 2);
756 pci_write_config_byte(dev, 0xec, pci_cmd);
757 pci_read_config_byte(dev, 0xe4, &pci_cmd);
758 pci_cmd &= ~(1 << 7);
759 pci_write_config_byte(dev, 0xe4, pci_cmd);
760 pci_read_config_byte(dev, 0xe5, &pci_cmd);
761 pci_cmd |= 1 << 7;
762 pci_write_config_byte(dev, 0xe5, pci_cmd);
763 /* Get address of ACPI registers block*/
764 pci_read_config_byte(dev, 0x81, &pci_cmd);
765 if (pci_cmd & 1 << 7) {
766 pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
767 acpi_regs_addr &= 0xff00;
768 printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr);
769 }
770
771 pci_dev_put(dev);
772 return 1;
773 }
774 return 0;
775}
776
777static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
778{
779 struct cpuinfo_x86 *c = cpu_data;
780 char *cpuname=NULL;
781 int ret;
782 u32 lo, hi;
783
784 /* Check what we have on this motherboard */
785 switch (c->x86_model) {
786 case 6:
787 cpu_model = CPU_SAMUEL;
788 cpuname = "C3 'Samuel' [C5A]";
789 longhaul_version = TYPE_LONGHAUL_V1;
790 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
791 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
792 break;
793
794 case 7:
795 switch (c->x86_mask) {
796 case 0:
797 longhaul_version = TYPE_LONGHAUL_V1;
798 cpu_model = CPU_SAMUEL2;
799 cpuname = "C3 'Samuel 2' [C5B]";
800 /* Note, this is not a typo, early Samuel2's had
801 * Samuel1 ratios. */
802 memcpy(clock_ratio, samuel1_clock_ratio,
803 sizeof(samuel1_clock_ratio));
804 memcpy(eblcr_table, samuel2_eblcr,
805 sizeof(samuel2_eblcr));
806 break;
807 case 1 ... 15:
808 longhaul_version = TYPE_LONGHAUL_V1;
809 if (c->x86_mask < 8) {
810 cpu_model = CPU_SAMUEL2;
811 cpuname = "C3 'Samuel 2' [C5B]";
812 } else {
813 cpu_model = CPU_EZRA;
814 cpuname = "C3 'Ezra' [C5C]";
815 }
816 memcpy(clock_ratio, ezra_clock_ratio,
817 sizeof(ezra_clock_ratio));
818 memcpy(eblcr_table, ezra_eblcr,
819 sizeof(ezra_eblcr));
820 break;
821 }
822 break;
823
824 case 8:
825 cpu_model = CPU_EZRA_T;
826 cpuname = "C3 'Ezra-T' [C5M]";
827 longhaul_version = TYPE_POWERSAVER;
828 numscales=32;
829 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
830 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
831 break;
832
833 case 9:
834 longhaul_version = TYPE_POWERSAVER;
835 numscales = 32;
836 memcpy(clock_ratio,
837 nehemiah_clock_ratio,
838 sizeof(nehemiah_clock_ratio));
839 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
840 switch (c->x86_mask) {
841 case 0 ... 1:
842 cpu_model = CPU_NEHEMIAH;
843 cpuname = "C3 'Nehemiah A' [C5XLOE]";
844 break;
845 case 2 ... 4:
846 cpu_model = CPU_NEHEMIAH;
847 cpuname = "C3 'Nehemiah B' [C5XLOH]";
848 break;
849 case 5 ... 15:
850 cpu_model = CPU_NEHEMIAH_C;
851 cpuname = "C3 'Nehemiah C' [C5P]";
852 break;
853 }
854 break;
855
856 default:
857 cpuname = "Unknown";
858 break;
859 }
860 /* Check Longhaul ver. 2 */
861 if (longhaul_version == TYPE_LONGHAUL_V2) {
862 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
863 if (lo == 0 && hi == 0)
864 /* Looks like MSR isn't present */
865 longhaul_version = TYPE_LONGHAUL_V1;
866 }
867
868 printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
869 switch (longhaul_version) {
870 case TYPE_LONGHAUL_V1:
871 case TYPE_LONGHAUL_V2:
872 printk ("Longhaul v%d supported.\n", longhaul_version);
873 break;
874 case TYPE_POWERSAVER:
875 printk ("Powersaver supported.\n");
876 break;
877 };
878
879 /* Doesn't hurt */
880 longhaul_setup_southbridge();
881
882 /* Find ACPI data for processor */
883 acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
884 ACPI_UINT32_MAX, &longhaul_walk_callback,
885 NULL, (void *)&pr);
886
887 /* Check ACPI support for C3 state */
888 if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
889 cx = &pr->power.states[ACPI_STATE_C3];
890 if (cx->address > 0 && cx->latency <= 1000)
891 longhaul_flags |= USE_ACPI_C3;
892 }
893 /* Disable if it isn't working */
894 if (disable_acpi_c3)
895 longhaul_flags &= ~USE_ACPI_C3;
896 /* Check if northbridge is friendly */
897 if (enable_arbiter_disable())
898 longhaul_flags |= USE_NORTHBRIDGE;
899
900 /* Check ACPI support for bus master arbiter disable */
901 if (!(longhaul_flags & USE_ACPI_C3
902 || longhaul_flags & USE_NORTHBRIDGE)
903 && ((pr == NULL) || !(pr->flags.bm_control))) {
904 printk(KERN_ERR PFX
905 "No ACPI support. Unsupported northbridge.\n");
906 return -ENODEV;
907 }
908
909 if (longhaul_flags & USE_NORTHBRIDGE)
910 printk(KERN_INFO PFX "Using northbridge support.\n");
911 if (longhaul_flags & USE_ACPI_C3)
912 printk(KERN_INFO PFX "Using ACPI support.\n");
913
914 ret = longhaul_get_ranges();
915 if (ret != 0)
916 return ret;
917
918 if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
919 longhaul_setup_voltagescaling();
920
921 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
922 policy->cpuinfo.transition_latency = 200000; /* nsec */
923 policy->cur = calc_speed(longhaul_get_cpu_mult());
924
925 ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
926 if (ret)
927 return ret;
928
929 cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
930
931 return 0;
932}
933
934static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
935{
936 cpufreq_frequency_table_put_attr(policy->cpu);
937 return 0;
938}
939
940static struct freq_attr* longhaul_attr[] = {
941 &cpufreq_freq_attr_scaling_available_freqs,
942 NULL,
943};
944
945static struct cpufreq_driver longhaul_driver = {
946 .verify = longhaul_verify,
947 .target = longhaul_target,
948 .get = longhaul_get,
949 .init = longhaul_cpu_init,
950 .exit = __devexit_p(longhaul_cpu_exit),
951 .name = "longhaul",
952 .owner = THIS_MODULE,
953 .attr = longhaul_attr,
954};
955
956
957static int __init longhaul_init(void)
958{
959 struct cpuinfo_x86 *c = cpu_data;
960
961 if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
962 return -ENODEV;
963
964#ifdef CONFIG_SMP
965 if (num_online_cpus() > 1) {
966 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
967 return -ENODEV;
968 }
969#endif
970#ifdef CONFIG_X86_IO_APIC
971 if (cpu_has_apic) {
972 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
973 return -ENODEV;
974 }
975#endif
976 switch (c->x86_model) {
977 case 6 ... 9:
978 return cpufreq_register_driver(&longhaul_driver);
979 case 10:
980 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
981 default:
982 ;;
983 }
984
985 return -ENODEV;
986}
987
988
989static void __exit longhaul_exit(void)
990{
991 int i;
992
993 for (i=0; i < numscales; i++) {
994 if (clock_ratio[i] == maxmult) {
995 longhaul_setstate(i);
996 break;
997 }
998 }
999
1000 cpufreq_unregister_driver(&longhaul_driver);
1001 kfree(longhaul_table);
1002}
1003
1004/* Even if BIOS is exporting ACPI C3 state, and it is used
1005 * with success when CPU is idle, this state doesn't
1006 * trigger frequency transition in some cases. */
1007module_param (disable_acpi_c3, int, 0644);
1008MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1009/* Change CPU voltage with frequency. Very usefull to save
1010 * power, but most VIA C3 processors aren't supporting it. */
1011module_param (scale_voltage, int, 0644);
1012MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1013/* Force revision key to 0 for processors which doesn't
1014 * support voltage scaling, but are introducing itself as
1015 * such. */
1016module_param(revid_errata, int, 0644);
1017MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1018
1019MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
1020MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
1021MODULE_LICENSE ("GPL");
1022
1023late_initcall(longhaul_init);
1024module_exit(longhaul_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 14:38:36 -0500