aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/kernel/cpu/centaur.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/x86/kernel/cpu/centaur.c')
-rw-r--r--arch/x86/kernel/cpu/centaur.c273
1 files changed, 0 insertions, 273 deletions
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 8d5652dc99dd..d8fba5c15fbd 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -1,6 +1,5 @@
1#include <linux/bitops.h> 1#include <linux/bitops.h>
2#include <linux/kernel.h> 2#include <linux/kernel.h>
3#include <linux/init.h>
4 3
5#include <asm/processor.h> 4#include <asm/processor.h>
6#include <asm/e820.h> 5#include <asm/e820.h>
@@ -9,236 +8,6 @@
9 8
10#include "cpu.h" 9#include "cpu.h"
11 10
12#ifdef CONFIG_X86_OOSTORE
13
14static u32 power2(u32 x)
15{
16 u32 s = 1;
17
18 while (s <= x)
19 s <<= 1;
20
21 return s >>= 1;
22}
23
24
25/*
26 * Set up an actual MCR
27 */
28static void centaur_mcr_insert(int reg, u32 base, u32 size, int key)
29{
30 u32 lo, hi;
31
32 hi = base & ~0xFFF;
33 lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
34 lo &= ~0xFFF; /* Remove the ctrl value bits */
35 lo |= key; /* Attribute we wish to set */
36 wrmsr(reg+MSR_IDT_MCR0, lo, hi);
37 mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
38}
39
40/*
41 * Figure what we can cover with MCR's
42 *
43 * Shortcut: We know you can't put 4Gig of RAM on a winchip
44 */
45static u32 ramtop(void)
46{
47 u32 clip = 0xFFFFFFFFUL;
48 u32 top = 0;
49 int i;
50
51 for (i = 0; i < e820.nr_map; i++) {
52 unsigned long start, end;
53
54 if (e820.map[i].addr > 0xFFFFFFFFUL)
55 continue;
56 /*
57 * Don't MCR over reserved space. Ignore the ISA hole
58 * we frob around that catastrophe already
59 */
60 if (e820.map[i].type == E820_RESERVED) {
61 if (e820.map[i].addr >= 0x100000UL &&
62 e820.map[i].addr < clip)
63 clip = e820.map[i].addr;
64 continue;
65 }
66 start = e820.map[i].addr;
67 end = e820.map[i].addr + e820.map[i].size;
68 if (start >= end)
69 continue;
70 if (end > top)
71 top = end;
72 }
73 /*
74 * Everything below 'top' should be RAM except for the ISA hole.
75 * Because of the limited MCR's we want to map NV/ACPI into our
76 * MCR range for gunk in RAM
77 *
78 * Clip might cause us to MCR insufficient RAM but that is an
79 * acceptable failure mode and should only bite obscure boxes with
80 * a VESA hole at 15Mb
81 *
82 * The second case Clip sometimes kicks in is when the EBDA is marked
83 * as reserved. Again we fail safe with reasonable results
84 */
85 if (top > clip)
86 top = clip;
87
88 return top;
89}
90
91/*
92 * Compute a set of MCR's to give maximum coverage
93 */
94static int centaur_mcr_compute(int nr, int key)
95{
96 u32 mem = ramtop();
97 u32 root = power2(mem);
98 u32 base = root;
99 u32 top = root;
100 u32 floor = 0;
101 int ct = 0;
102
103 while (ct < nr) {
104 u32 fspace = 0;
105 u32 high;
106 u32 low;
107
108 /*
109 * Find the largest block we will fill going upwards
110 */
111 high = power2(mem-top);
112
113 /*
114 * Find the largest block we will fill going downwards
115 */
116 low = base/2;
117
118 /*
119 * Don't fill below 1Mb going downwards as there
120 * is an ISA hole in the way.
121 */
122 if (base <= 1024*1024)
123 low = 0;
124
125 /*
126 * See how much space we could cover by filling below
127 * the ISA hole
128 */
129
130 if (floor == 0)
131 fspace = 512*1024;
132 else if (floor == 512*1024)
133 fspace = 128*1024;
134
135 /* And forget ROM space */
136
137 /*
138 * Now install the largest coverage we get
139 */
140 if (fspace > high && fspace > low) {
141 centaur_mcr_insert(ct, floor, fspace, key);
142 floor += fspace;
143 } else if (high > low) {
144 centaur_mcr_insert(ct, top, high, key);
145 top += high;
146 } else if (low > 0) {
147 base -= low;
148 centaur_mcr_insert(ct, base, low, key);
149 } else
150 break;
151 ct++;
152 }
153 /*
154 * We loaded ct values. We now need to set the mask. The caller
155 * must do this bit.
156 */
157 return ct;
158}
159
160static void centaur_create_optimal_mcr(void)
161{
162 int used;
163 int i;
164
165 /*
166 * Allocate up to 6 mcrs to mark as much of ram as possible
167 * as write combining and weak write ordered.
168 *
169 * To experiment with: Linux never uses stack operations for
170 * mmio spaces so we could globally enable stack operation wc
171 *
172 * Load the registers with type 31 - full write combining, all
173 * writes weakly ordered.
174 */
175 used = centaur_mcr_compute(6, 31);
176
177 /*
178 * Wipe unused MCRs
179 */
180 for (i = used; i < 8; i++)
181 wrmsr(MSR_IDT_MCR0+i, 0, 0);
182}
183
184static void winchip2_create_optimal_mcr(void)
185{
186 u32 lo, hi;
187 int used;
188 int i;
189
190 /*
191 * Allocate up to 6 mcrs to mark as much of ram as possible
192 * as write combining, weak store ordered.
193 *
194 * Load the registers with type 25
195 * 8 - weak write ordering
196 * 16 - weak read ordering
197 * 1 - write combining
198 */
199 used = centaur_mcr_compute(6, 25);
200
201 /*
202 * Mark the registers we are using.
203 */
204 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
205 for (i = 0; i < used; i++)
206 lo |= 1<<(9+i);
207 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
208
209 /*
210 * Wipe unused MCRs
211 */
212
213 for (i = used; i < 8; i++)
214 wrmsr(MSR_IDT_MCR0+i, 0, 0);
215}
216
217/*
218 * Handle the MCR key on the Winchip 2.
219 */
220static void winchip2_unprotect_mcr(void)
221{
222 u32 lo, hi;
223 u32 key;
224
225 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
226 lo &= ~0x1C0; /* blank bits 8-6 */
227 key = (lo>>17) & 7;
228 lo |= key<<6; /* replace with unlock key */
229 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
230}
231
232static void winchip2_protect_mcr(void)
233{
234 u32 lo, hi;
235
236 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
237 lo &= ~0x1C0; /* blank bits 8-6 */
238 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
239}
240#endif /* CONFIG_X86_OOSTORE */
241
242#define ACE_PRESENT (1 << 6) 11#define ACE_PRESENT (1 << 6)
243#define ACE_ENABLED (1 << 7) 12#define ACE_ENABLED (1 << 7)
244#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ 13#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
@@ -363,20 +132,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
363 fcr_clr = DPDC; 132 fcr_clr = DPDC;
364 printk(KERN_NOTICE "Disabling bugged TSC.\n"); 133 printk(KERN_NOTICE "Disabling bugged TSC.\n");
365 clear_cpu_cap(c, X86_FEATURE_TSC); 134 clear_cpu_cap(c, X86_FEATURE_TSC);
366#ifdef CONFIG_X86_OOSTORE
367 centaur_create_optimal_mcr();
368 /*
369 * Enable:
370 * write combining on non-stack, non-string
371 * write combining on string, all types
372 * weak write ordering
373 *
374 * The C6 original lacks weak read order
375 *
376 * Note 0x120 is write only on Winchip 1
377 */
378 wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
379#endif
380 break; 135 break;
381 case 8: 136 case 8:
382 switch (c->x86_mask) { 137 switch (c->x86_mask) {
@@ -393,40 +148,12 @@ static void init_centaur(struct cpuinfo_x86 *c)
393 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 148 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
394 E2MMX|EAMD3D; 149 E2MMX|EAMD3D;
395 fcr_clr = DPDC; 150 fcr_clr = DPDC;
396#ifdef CONFIG_X86_OOSTORE
397 winchip2_unprotect_mcr();
398 winchip2_create_optimal_mcr();
399 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
400 /*
401 * Enable:
402 * write combining on non-stack, non-string
403 * write combining on string, all types
404 * weak write ordering
405 */
406 lo |= 31;
407 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
408 winchip2_protect_mcr();
409#endif
410 break; 151 break;
411 case 9: 152 case 9:
412 name = "3"; 153 name = "3";
413 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK| 154 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
414 E2MMX|EAMD3D; 155 E2MMX|EAMD3D;
415 fcr_clr = DPDC; 156 fcr_clr = DPDC;
416#ifdef CONFIG_X86_OOSTORE
417 winchip2_unprotect_mcr();
418 winchip2_create_optimal_mcr();
419 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
420 /*
421 * Enable:
422 * write combining on non-stack, non-string
423 * write combining on string, all types
424 * weak write ordering
425 */
426 lo |= 31;
427 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
428 winchip2_protect_mcr();
429#endif
430 break; 157 break;
431 default: 158 default:
432 name = "??"; 159 name = "??";
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-09 20:18:41 -0400