1 files changed, 53 insertions, 24 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index ba5f62f45f01..9e093f8fe78c 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -148,7 +148,7 @@ static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
         /* calling is from identify_secondary_cpu() ? */
-        if (c->cpu_index == boot_cpu_id)
+        if (!c->cpu_index)
                 return;
 
         /*
@@ -253,37 +253,51 @@ static int __cpuinit nearby_node(int apicid)
 #endif
 
 /*
- * Fixup core topology information for AMD multi-node processors.
- * Assumption: Number of cores in each internal node is the same.
+ * Fixup core topology information for
+ * (1) AMD multi-node processors
+ *     Assumption: Number of cores in each internal node is the same.
+ * (2) AMD processors supporting compute units
  */
 #ifdef CONFIG_X86_HT
-static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
+static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
 {
-        unsigned long long value;
-        u32 nodes, cores_per_node;
+        u32 nodes;
+        u8 node_id;
         int cpu = smp_processor_id();
 
-        if (!cpu_has(c, X86_FEATURE_NODEID_MSR))
-                return;
+        /* get information required for multi-node processors */
+        if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+                u32 eax, ebx, ecx, edx;
 
-        /* fixup topology information only once for a core */
-        if (cpu_has(c, X86_FEATURE_AMD_DCM))
-                return;
+                cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
+                nodes = ((ecx >> 8) & 7) + 1;
+                node_id = ecx & 7;
 
-        rdmsrl(MSR_FAM10H_NODE_ID, value);
+                /* get compute unit information */
+                smp_num_siblings = ((ebx >> 8) & 3) + 1;
+                c->compute_unit_id = ebx & 0xff;
+        } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
+                u64 value;
 
-        nodes = ((value >> 3) & 7) + 1;
-        if (nodes == 1)
+                rdmsrl(MSR_FAM10H_NODE_ID, value);
+                nodes = ((value >> 3) & 7) + 1;
+                node_id = value & 7;
+        } else
                 return;
 
-        set_cpu_cap(c, X86_FEATURE_AMD_DCM);
-        cores_per_node = c->x86_max_cores / nodes;
+        /* fixup multi-node processor information */
+        if (nodes > 1) {
+                u32 cores_per_node;
+
+                set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+                cores_per_node = c->x86_max_cores / nodes;
 
-        /* store NodeID, use llc_shared_map to store sibling info */
-        per_cpu(cpu_llc_id, cpu) = value & 7;
+                /* store NodeID, use llc_shared_map to store sibling info */
+                per_cpu(cpu_llc_id, cpu) = node_id;
 
-        /* fixup core id to be in range from 0 to (cores_per_node - 1) */
-        c->cpu_core_id = c->cpu_core_id % cores_per_node;
+                /* core id to be in range from 0 to (cores_per_node - 1) */
+                c->cpu_core_id = c->cpu_core_id % cores_per_node;
+        }
 }
 #endif
 
@@ -304,9 +318,7 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
         c->phys_proc_id = c->initial_apicid >> bits;
         /* use socket ID also for last level cache */
         per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
-        /* fixup topology information on multi-node processors */
-        if ((c->x86 == 0x10) && (c->x86_model == 9))
-                amd_fixup_dcm(c);
+        amd_get_topology(c);
 #endif
 }
 
@@ -412,6 +424,23 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
                         set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
         }
 #endif
+
+        /* We need to do the following only once */
+        if (c != &boot_cpu_data)
+                return;
+
+        if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
+
+                if (c->x86 > 0x10 ||
+                    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
+                        u64 val;
+
+                        rdmsrl(MSR_K7_HWCR, val);
+                        if (!(val & BIT(24)))
+                                printk(KERN_WARNING FW_BUG "TSC doesn't count "
+                                        "with P0 frequency!\n");
+                }
+        }
 }
 
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
@@ -523,7 +552,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 #endif
 
         if (c->extended_cpuid_level >= 0x80000006) {
-                if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
+                if (cpuid_edx(0x80000006) & 0xf000)
                         num_cache_leaves = 4;
                 else
                         num_cache_leaves = 3;