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-rw-r--r--arch/x86/kernel/cpu/amd.c337
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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1#include <linux/init.h>
2#include <linux/bitops.h>
3#include <linux/mm.h>
4#include <asm/io.h>
5#include <asm/processor.h>
6#include <asm/apic.h>
7
8#include "cpu.h"
9
10/*
11 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
12 * misexecution of code under Linux. Owners of such processors should
13 * contact AMD for precise details and a CPU swap.
14 *
15 * See http://www.multimania.com/poulot/k6bug.html
16 * http://www.amd.com/K6/k6docs/revgd.html
17 *
18 * The following test is erm.. interesting. AMD neglected to up
19 * the chip setting when fixing the bug but they also tweaked some
20 * performance at the same time..
21 */
22
23extern void vide(void);
24__asm__(".align 4\nvide: ret");
25
26#ifdef CONFIG_X86_LOCAL_APIC
27#define ENABLE_C1E_MASK 0x18000000
28#define CPUID_PROCESSOR_SIGNATURE 1
29#define CPUID_XFAM 0x0ff00000
30#define CPUID_XFAM_K8 0x00000000
31#define CPUID_XFAM_10H 0x00100000
32#define CPUID_XFAM_11H 0x00200000
33#define CPUID_XMOD 0x000f0000
34#define CPUID_XMOD_REV_F 0x00040000
35
36/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
37static __cpuinit int amd_apic_timer_broken(void)
38{
39 u32 lo, hi;
40 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
41 switch (eax & CPUID_XFAM) {
42 case CPUID_XFAM_K8:
43 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
44 break;
45 case CPUID_XFAM_10H:
46 case CPUID_XFAM_11H:
47 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
48 if (lo & ENABLE_C1E_MASK)
49 return 1;
50 break;
51 default:
52 /* err on the side of caution */
53 return 1;
54 }
55 return 0;
56}
57#endif
58
59int force_mwait __cpuinitdata;
60
61static void __cpuinit init_amd(struct cpuinfo_x86 *c)
62{
63 u32 l, h;
64 int mbytes = num_physpages >> (20-PAGE_SHIFT);
65 int r;
66
67#ifdef CONFIG_SMP
68 unsigned long long value;
69
70 /* Disable TLB flush filter by setting HWCR.FFDIS on K8
71 * bit 6 of msr C001_0015
72 *
73 * Errata 63 for SH-B3 steppings
74 * Errata 122 for all steppings (F+ have it disabled by default)
75 */
76 if (c->x86 == 15) {
77 rdmsrl(MSR_K7_HWCR, value);
78 value |= 1 << 6;
79 wrmsrl(MSR_K7_HWCR, value);
80 }
81#endif
82
83 /*
84 * FIXME: We should handle the K5 here. Set up the write
85 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
86 * no bus pipeline)
87 */
88
89 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
90 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
91 clear_bit(0*32+31, c->x86_capability);
92
93 r = get_model_name(c);
94
95 switch(c->x86)
96 {
97 case 4:
98 /*
99 * General Systems BIOSen alias the cpu frequency registers
100 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
101 * drivers subsequently pokes it, and changes the CPU speed.
102 * Workaround : Remove the unneeded alias.
103 */
104#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
105#define CBAR_ENB (0x80000000)
106#define CBAR_KEY (0X000000CB)
107 if (c->x86_model==9 || c->x86_model == 10) {
108 if (inl (CBAR) & CBAR_ENB)
109 outl (0 | CBAR_KEY, CBAR);
110 }
111 break;
112 case 5:
113 if( c->x86_model < 6 )
114 {
115 /* Based on AMD doc 20734R - June 2000 */
116 if ( c->x86_model == 0 ) {
117 clear_bit(X86_FEATURE_APIC, c->x86_capability);
118 set_bit(X86_FEATURE_PGE, c->x86_capability);
119 }
120 break;
121 }
122
123 if ( c->x86_model == 6 && c->x86_mask == 1 ) {
124 const int K6_BUG_LOOP = 1000000;
125 int n;
126 void (*f_vide)(void);
127 unsigned long d, d2;
128
129 printk(KERN_INFO "AMD K6 stepping B detected - ");
130
131 /*
132 * It looks like AMD fixed the 2.6.2 bug and improved indirect
133 * calls at the same time.
134 */
135
136 n = K6_BUG_LOOP;
137 f_vide = vide;
138 rdtscl(d);
139 while (n--)
140 f_vide();
141 rdtscl(d2);
142 d = d2-d;
143
144 if (d > 20*K6_BUG_LOOP)
145 printk("system stability may be impaired when more than 32 MB are used.\n");
146 else
147 printk("probably OK (after B9730xxxx).\n");
148 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
149 }
150
151 /* K6 with old style WHCR */
152 if (c->x86_model < 8 ||
153 (c->x86_model== 8 && c->x86_mask < 8)) {
154 /* We can only write allocate on the low 508Mb */
155 if(mbytes>508)
156 mbytes=508;
157
158 rdmsr(MSR_K6_WHCR, l, h);
159 if ((l&0x0000FFFF)==0) {
160 unsigned long flags;
161 l=(1<<0)|((mbytes/4)<<1);
162 local_irq_save(flags);
163 wbinvd();
164 wrmsr(MSR_K6_WHCR, l, h);
165 local_irq_restore(flags);
166 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
167 mbytes);
168 }
169 break;
170 }
171
172 if ((c->x86_model == 8 && c->x86_mask >7) ||
173 c->x86_model == 9 || c->x86_model == 13) {
174 /* The more serious chips .. */
175
176 if(mbytes>4092)
177 mbytes=4092;
178
179 rdmsr(MSR_K6_WHCR, l, h);
180 if ((l&0xFFFF0000)==0) {
181 unsigned long flags;
182 l=((mbytes>>2)<<22)|(1<<16);
183 local_irq_save(flags);
184 wbinvd();
185 wrmsr(MSR_K6_WHCR, l, h);
186 local_irq_restore(flags);
187 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
188 mbytes);
189 }
190
191 /* Set MTRR capability flag if appropriate */
192 if (c->x86_model == 13 || c->x86_model == 9 ||
193 (c->x86_model == 8 && c->x86_mask >= 8))
194 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
195 break;
196 }
197
198 if (c->x86_model == 10) {
199 /* AMD Geode LX is model 10 */
200 /* placeholder for any needed mods */
201 break;
202 }
203 break;
204 case 6: /* An Athlon/Duron */
205
206 /* Bit 15 of Athlon specific MSR 15, needs to be 0
207 * to enable SSE on Palomino/Morgan/Barton CPU's.
208 * If the BIOS didn't enable it already, enable it here.
209 */
210 if (c->x86_model >= 6 && c->x86_model <= 10) {
211 if (!cpu_has(c, X86_FEATURE_XMM)) {
212 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
213 rdmsr(MSR_K7_HWCR, l, h);
214 l &= ~0x00008000;
215 wrmsr(MSR_K7_HWCR, l, h);
216 set_bit(X86_FEATURE_XMM, c->x86_capability);
217 }
218 }
219
220 /* It's been determined by AMD that Athlons since model 8 stepping 1
221 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
222 * As per AMD technical note 27212 0.2
223 */
224 if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
225 rdmsr(MSR_K7_CLK_CTL, l, h);
226 if ((l & 0xfff00000) != 0x20000000) {
227 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
228 ((l & 0x000fffff)|0x20000000));
229 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
230 }
231 }
232 break;
233 }
234
235 switch (c->x86) {
236 case 15:
237 /* Use K8 tuning for Fam10h and Fam11h */
238 case 0x10:
239 case 0x11:
240 set_bit(X86_FEATURE_K8, c->x86_capability);
241 break;
242 case 6:
243 set_bit(X86_FEATURE_K7, c->x86_capability);
244 break;
245 }
246 if (c->x86 >= 6)
247 set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
248
249 display_cacheinfo(c);
250
251 if (cpuid_eax(0x80000000) >= 0x80000008) {
252 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
253 }
254
255 if (cpuid_eax(0x80000000) >= 0x80000007) {
256 c->x86_power = cpuid_edx(0x80000007);
257 if (c->x86_power & (1<<8))
258 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
259 }
260
261#ifdef CONFIG_X86_HT
262 /*
263 * On a AMD multi core setup the lower bits of the APIC id
264 * distingush the cores.
265 */
266 if (c->x86_max_cores > 1) {
267 int cpu = smp_processor_id();
268 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
269
270 if (bits == 0) {
271 while ((1 << bits) < c->x86_max_cores)
272 bits++;
273 }
274 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
275 c->phys_proc_id >>= bits;
276 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
277 cpu, c->x86_max_cores, c->cpu_core_id);
278 }
279#endif
280
281 if (cpuid_eax(0x80000000) >= 0x80000006) {
282 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
283 num_cache_leaves = 4;
284 else
285 num_cache_leaves = 3;
286 }
287
288#ifdef CONFIG_X86_LOCAL_APIC
289 if (amd_apic_timer_broken())
290 local_apic_timer_disabled = 1;
291#endif
292
293 if (c->x86 == 0x10 && !force_mwait)
294 clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
295
296 /* K6s reports MCEs but don't actually have all the MSRs */
297 if (c->x86 < 6)
298 clear_bit(X86_FEATURE_MCE, c->x86_capability);
299}
300
301static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
302{
303 /* AMD errata T13 (order #21922) */
304 if ((c->x86 == 6)) {
305 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
306 size = 64;
307 if (c->x86_model == 4 &&
308 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
309 size = 256;
310 }
311 return size;
312}
313
314static struct cpu_dev amd_cpu_dev __cpuinitdata = {
315 .c_vendor = "AMD",
316 .c_ident = { "AuthenticAMD" },
317 .c_models = {
318 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
319 {
320 [3] = "486 DX/2",
321 [7] = "486 DX/2-WB",
322 [8] = "486 DX/4",
323 [9] = "486 DX/4-WB",
324 [14] = "Am5x86-WT",
325 [15] = "Am5x86-WB"
326 }
327 },
328 },
329 .c_init = init_amd,
330 .c_size_cache = amd_size_cache,
331};
332
333int __init amd_init_cpu(void)
334{
335 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
336 return 0;
337}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 19:39:42 -0400