1 files changed, 108 insertions, 19 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 63fddcd082cd..f32fa71ccf97 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -2,7 +2,7 @@
 #include <linux/bitops.h>
 #include <linux/mm.h>
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/processor.h>
 #include <asm/apic.h>
 #include <asm/cpu.h>
@@ -45,8 +45,8 @@ static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
 #define CBAR_ENB        (0x80000000)
 #define CBAR_KEY        (0X000000CB)
         if (c->x86_model == 9 || c->x86_model == 10) {
-                if (inl (CBAR) & CBAR_ENB)
-                        outl (0 | CBAR_KEY, CBAR);
+                if (inl(CBAR) & CBAR_ENB)
+                        outl(0 | CBAR_KEY, CBAR);
         }
 }
 
@@ -87,9 +87,10 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                 d = d2-d;
 
                 if (d > 20*K6_BUG_LOOP)
-                        printk("system stability may be impaired when more than 32 MB are used.\n");
+                        printk(KERN_CONT
+                                "system stability may be impaired when more than 32 MB are used.\n");
                 else
-                        printk("probably OK (after B9730xxxx).\n");
+                        printk(KERN_CONT "probably OK (after B9730xxxx).\n");
                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
         }
 
@@ -219,8 +220,9 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
                 rdmsr(MSR_K7_CLK_CTL, l, h);
                 if ((l & 0xfff00000) != 0x20000000) {
-                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
-                                ((l & 0x000fffff)|0x20000000));
+                        printk(KERN_INFO
+                            "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
+                                        l, ((l & 0x000fffff)|0x20000000));
                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
                 }
         }
@@ -251,6 +253,64 @@ static int __cpuinit nearby_node(int apicid)
 #endif
 
 /*
+ * Fixup core topology information for AMD multi-node processors.
+ * Assumption 1: Number of cores in each internal node is the same.
+ * Assumption 2: Mixed systems with both single-node and dual-node
+ *               processors are not supported.
+ */
+#ifdef CONFIG_X86_HT
+static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_PCI
+        u32 t, cpn;
+        u8 n, n_id;
+        int cpu = smp_processor_id();
+
+        /* fixup topology information only once for a core */
+        if (cpu_has(c, X86_FEATURE_AMD_DCM))
+                return;
+
+        /* check for multi-node processor on boot cpu */
+        t = read_pci_config(0, 24, 3, 0xe8);
+        if (!(t & (1 << 29)))
+                return;
+
+        set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+
+        /* cores per node: each internal node has half the number of cores */
+        cpn = c->x86_max_cores >> 1;
+
+        /* even-numbered NB_id of this dual-node processor */
+        n = c->phys_proc_id << 1;
+
+        /*
+         * determine internal node id and assign cores fifty-fifty to
+         * each node of the dual-node processor
+         */
+        t = read_pci_config(0, 24 + n, 3, 0xe8);
+        n = (t>>30) & 0x3;
+        if (n == 0) {
+                if (c->cpu_core_id < cpn)
+                        n_id = 0;
+                else
+                        n_id = 1;
+        } else {
+                if (c->cpu_core_id < cpn)
+                        n_id = 1;
+                else
+                        n_id = 0;
+        }
+
+        /* compute entire NodeID, use llc_shared_map to store sibling info */
+        per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id;
+
+        /* fixup core id to be in range from 0 to cpn */
+        c->cpu_core_id = c->cpu_core_id % cpn;
+#endif
+}
+#endif
+
+/*
  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  * Assumes number of cores is a power of two.
  */
@@ -267,17 +327,31 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
         c->phys_proc_id = c->initial_apicid >> bits;
         /* use socket ID also for last level cache */
         per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
+        /* fixup topology information on multi-node processors */
+        if ((c->x86 == 0x10) && (c->x86_model == 9))
+                amd_fixup_dcm(c);
 #endif
 }
 
+int amd_get_nb_id(int cpu)
+{
+        int id = 0;
+#ifdef CONFIG_SMP
+        id = per_cpu(cpu_llc_id, cpu);
+#endif
+        return id;
+}
+EXPORT_SYMBOL_GPL(amd_get_nb_id);
+
 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 {
 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
         int cpu = smp_processor_id();
         int node;
-        unsigned apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
+        unsigned apicid = c->apicid;
+
+        node = per_cpu(cpu_llc_id, cpu);
 
-        node = c->phys_proc_id;
         if (apicid_to_node[apicid] != NUMA_NO_NODE)
                 node = apicid_to_node[apicid];
         if (!node_online(node)) {
@@ -398,18 +472,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 u32 level;
 
                 level = cpuid_eax(1);
-                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
+                if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
                         set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 
                 /*
                  * Some BIOSes incorrectly force this feature, but only K8
                  * revision D (model = 0x14) and later actually support it.
+                 * (AMD Erratum #110, docId: 25759).
                  */
-                if (c->x86_model < 0x14)
+                if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
+                        u64 val;
+
                         clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
+                        if (!rdmsrl_amd_safe(0xc001100d, &val)) {
+                                val &= ~(1ULL << 32);
+                                wrmsrl_amd_safe(0xc001100d, val);
+                        }
+                }
+
         }
         if (c->x86 == 0x10 || c->x86 == 0x11)
                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+
+        /* get apicid instead of initial apic id from cpuid */
+        c->apicid = hard_smp_processor_id();
 #else
 
         /*
@@ -494,27 +580,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                  * benefit in doing so.
                  */
                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
-                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
-                    if ((tseg>>PMD_SHIFT) <
+                        printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                        if ((tseg>>PMD_SHIFT) <
                                 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
-                        ((tseg>>PMD_SHIFT) <
+                                ((tseg>>PMD_SHIFT) <
                                 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
-                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
-                        set_memory_4k((unsigned long)__va(tseg), 1);
+                                (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
+                                set_memory_4k((unsigned long)__va(tseg), 1);
                 }
         }
 #endif
 }
 
 #ifdef CONFIG_X86_32
-static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
+static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
+                                                        unsigned int size)
 {
         /* AMD errata T13 (order #21922) */
         if ((c->x86 == 6)) {
-                if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
+                /* Duron Rev A0 */
+                if (c->x86_model == 3 && c->x86_mask == 0)
                         size = 64;
+                /* Tbird rev A1/A2 */
                 if (c->x86_model == 4 &&
-                    (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
+                        (c->x86_mask == 0 || c->x86_mask == 1))
                         size = 256;
         }
         return size;