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-rw-r--r--arch/x86/kernel/apic_64.c26
1 files changed, 22 insertions, 4 deletions
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index d341f798255c..027004262105 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -187,17 +187,35 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
187} 187}
188 188
189/* 189/*
190 * Setup extended LVT (K8 specific) 190 * Setup extended LVT, AMD specific (K8, family 10h)
191 *
192 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
193 * MCE interrupts are supported. Thus MCE offset must be set to 0.
191 */ 194 */
192void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector, 195
193 unsigned char msg_type, unsigned char mask) 196#define APIC_EILVT_LVTOFF_MCE 0
197#define APIC_EILVT_LVTOFF_IBS 1
198
199static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
194{ 200{
195 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE; 201 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
196 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 202 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
197 203
198 apic_write(reg, v); 204 apic_write(reg, v);
199} 205}
200 206
207u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
208{
209 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
210 return APIC_EILVT_LVTOFF_MCE;
211}
212
213u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
214{
215 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
216 return APIC_EILVT_LVTOFF_IBS;
217}
218
201/* 219/*
202 * Program the next event, relative to now 220 * Program the next event, relative to now
203 */ 221 */