diff options
Diffstat (limited to 'arch/x86/kernel/apic_32.c')
-rw-r--r-- | arch/x86/kernel/apic_32.c | 175 |
1 files changed, 88 insertions, 87 deletions
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c index a437d027f20b..d6c898358371 100644 --- a/arch/x86/kernel/apic_32.c +++ b/arch/x86/kernel/apic_32.c | |||
@@ -75,7 +75,7 @@ char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |||
75 | /* | 75 | /* |
76 | * Debug level, exported for io_apic.c | 76 | * Debug level, exported for io_apic.c |
77 | */ | 77 | */ |
78 | int apic_verbosity; | 78 | unsigned int apic_verbosity; |
79 | 79 | ||
80 | int pic_mode; | 80 | int pic_mode; |
81 | 81 | ||
@@ -177,7 +177,7 @@ void __cpuinit enable_NMI_through_LVT0(void) | |||
177 | /* Level triggered for 82489DX */ | 177 | /* Level triggered for 82489DX */ |
178 | if (!lapic_is_integrated()) | 178 | if (!lapic_is_integrated()) |
179 | v |= APIC_LVT_LEVEL_TRIGGER; | 179 | v |= APIC_LVT_LEVEL_TRIGGER; |
180 | apic_write_around(APIC_LVT0, v); | 180 | apic_write(APIC_LVT0, v); |
181 | } | 181 | } |
182 | 182 | ||
183 | /** | 183 | /** |
@@ -212,9 +212,6 @@ int lapic_get_maxlvt(void) | |||
212 | * this function twice on the boot CPU, once with a bogus timeout | 212 | * this function twice on the boot CPU, once with a bogus timeout |
213 | * value, second time for real. The other (noncalibrating) CPUs | 213 | * value, second time for real. The other (noncalibrating) CPUs |
214 | * call this function only once, with the real, calibrated value. | 214 | * call this function only once, with the real, calibrated value. |
215 | * | ||
216 | * We do reads before writes even if unnecessary, to get around the | ||
217 | * P5 APIC double write bug. | ||
218 | */ | 215 | */ |
219 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | 216 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
220 | { | 217 | { |
@@ -229,18 +226,18 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |||
229 | if (!irqen) | 226 | if (!irqen) |
230 | lvtt_value |= APIC_LVT_MASKED; | 227 | lvtt_value |= APIC_LVT_MASKED; |
231 | 228 | ||
232 | apic_write_around(APIC_LVTT, lvtt_value); | 229 | apic_write(APIC_LVTT, lvtt_value); |
233 | 230 | ||
234 | /* | 231 | /* |
235 | * Divide PICLK by 16 | 232 | * Divide PICLK by 16 |
236 | */ | 233 | */ |
237 | tmp_value = apic_read(APIC_TDCR); | 234 | tmp_value = apic_read(APIC_TDCR); |
238 | apic_write_around(APIC_TDCR, (tmp_value | 235 | apic_write(APIC_TDCR, |
239 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 236 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
240 | | APIC_TDR_DIV_16); | 237 | APIC_TDR_DIV_16); |
241 | 238 | ||
242 | if (!oneshot) | 239 | if (!oneshot) |
243 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | 240 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
244 | } | 241 | } |
245 | 242 | ||
246 | /* | 243 | /* |
@@ -249,7 +246,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |||
249 | static int lapic_next_event(unsigned long delta, | 246 | static int lapic_next_event(unsigned long delta, |
250 | struct clock_event_device *evt) | 247 | struct clock_event_device *evt) |
251 | { | 248 | { |
252 | apic_write_around(APIC_TMICT, delta); | 249 | apic_write(APIC_TMICT, delta); |
253 | return 0; | 250 | return 0; |
254 | } | 251 | } |
255 | 252 | ||
@@ -278,7 +275,7 @@ static void lapic_timer_setup(enum clock_event_mode mode, | |||
278 | case CLOCK_EVT_MODE_SHUTDOWN: | 275 | case CLOCK_EVT_MODE_SHUTDOWN: |
279 | v = apic_read(APIC_LVTT); | 276 | v = apic_read(APIC_LVTT); |
280 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | 277 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
281 | apic_write_around(APIC_LVTT, v); | 278 | apic_write(APIC_LVTT, v); |
282 | break; | 279 | break; |
283 | case CLOCK_EVT_MODE_RESUME: | 280 | case CLOCK_EVT_MODE_RESUME: |
284 | /* Nothing to do here */ | 281 | /* Nothing to do here */ |
@@ -372,12 +369,7 @@ static void __init lapic_cal_handler(struct clock_event_device *dev) | |||
372 | } | 369 | } |
373 | } | 370 | } |
374 | 371 | ||
375 | /* | 372 | static int __init calibrate_APIC_clock(void) |
376 | * Setup the boot APIC | ||
377 | * | ||
378 | * Calibrate and verify the result. | ||
379 | */ | ||
380 | void __init setup_boot_APIC_clock(void) | ||
381 | { | 373 | { |
382 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | 374 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); |
383 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; | 375 | const long pm_100ms = PMTMR_TICKS_PER_SEC/10; |
@@ -387,24 +379,6 @@ void __init setup_boot_APIC_clock(void) | |||
387 | long delta, deltapm; | 379 | long delta, deltapm; |
388 | int pm_referenced = 0; | 380 | int pm_referenced = 0; |
389 | 381 | ||
390 | /* | ||
391 | * The local apic timer can be disabled via the kernel | ||
392 | * commandline or from the CPU detection code. Register the lapic | ||
393 | * timer as a dummy clock event source on SMP systems, so the | ||
394 | * broadcast mechanism is used. On UP systems simply ignore it. | ||
395 | */ | ||
396 | if (local_apic_timer_disabled) { | ||
397 | /* No broadcast on UP ! */ | ||
398 | if (num_possible_cpus() > 1) { | ||
399 | lapic_clockevent.mult = 1; | ||
400 | setup_APIC_timer(); | ||
401 | } | ||
402 | return; | ||
403 | } | ||
404 | |||
405 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" | ||
406 | "calibrating APIC timer ...\n"); | ||
407 | |||
408 | local_irq_disable(); | 382 | local_irq_disable(); |
409 | 383 | ||
410 | /* Replace the global interrupt handler */ | 384 | /* Replace the global interrupt handler */ |
@@ -489,8 +463,6 @@ void __init setup_boot_APIC_clock(void) | |||
489 | calibration_result / (1000000 / HZ), | 463 | calibration_result / (1000000 / HZ), |
490 | calibration_result % (1000000 / HZ)); | 464 | calibration_result % (1000000 / HZ)); |
491 | 465 | ||
492 | local_apic_timer_verify_ok = 1; | ||
493 | |||
494 | /* | 466 | /* |
495 | * Do a sanity check on the APIC calibration result | 467 | * Do a sanity check on the APIC calibration result |
496 | */ | 468 | */ |
@@ -498,12 +470,11 @@ void __init setup_boot_APIC_clock(void) | |||
498 | local_irq_enable(); | 470 | local_irq_enable(); |
499 | printk(KERN_WARNING | 471 | printk(KERN_WARNING |
500 | "APIC frequency too slow, disabling apic timer\n"); | 472 | "APIC frequency too slow, disabling apic timer\n"); |
501 | /* No broadcast on UP ! */ | 473 | return -1; |
502 | if (num_possible_cpus() > 1) | ||
503 | setup_APIC_timer(); | ||
504 | return; | ||
505 | } | 474 | } |
506 | 475 | ||
476 | local_apic_timer_verify_ok = 1; | ||
477 | |||
507 | /* We trust the pm timer based calibration */ | 478 | /* We trust the pm timer based calibration */ |
508 | if (!pm_referenced) { | 479 | if (!pm_referenced) { |
509 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | 480 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
@@ -543,22 +514,55 @@ void __init setup_boot_APIC_clock(void) | |||
543 | if (!local_apic_timer_verify_ok) { | 514 | if (!local_apic_timer_verify_ok) { |
544 | printk(KERN_WARNING | 515 | printk(KERN_WARNING |
545 | "APIC timer disabled due to verification failure.\n"); | 516 | "APIC timer disabled due to verification failure.\n"); |
517 | return -1; | ||
518 | } | ||
519 | |||
520 | return 0; | ||
521 | } | ||
522 | |||
523 | /* | ||
524 | * Setup the boot APIC | ||
525 | * | ||
526 | * Calibrate and verify the result. | ||
527 | */ | ||
528 | void __init setup_boot_APIC_clock(void) | ||
529 | { | ||
530 | /* | ||
531 | * The local apic timer can be disabled via the kernel | ||
532 | * commandline or from the CPU detection code. Register the lapic | ||
533 | * timer as a dummy clock event source on SMP systems, so the | ||
534 | * broadcast mechanism is used. On UP systems simply ignore it. | ||
535 | */ | ||
536 | if (local_apic_timer_disabled) { | ||
546 | /* No broadcast on UP ! */ | 537 | /* No broadcast on UP ! */ |
547 | if (num_possible_cpus() == 1) | 538 | if (num_possible_cpus() > 1) { |
548 | return; | 539 | lapic_clockevent.mult = 1; |
549 | } else { | 540 | setup_APIC_timer(); |
550 | /* | 541 | } |
551 | * If nmi_watchdog is set to IO_APIC, we need the | 542 | return; |
552 | * PIT/HPET going. Otherwise register lapic as a dummy | ||
553 | * device. | ||
554 | */ | ||
555 | if (nmi_watchdog != NMI_IO_APIC) | ||
556 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | ||
557 | else | ||
558 | printk(KERN_WARNING "APIC timer registered as dummy," | ||
559 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | ||
560 | } | 543 | } |
561 | 544 | ||
545 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" | ||
546 | "calibrating APIC timer ...\n"); | ||
547 | |||
548 | if (calibrate_APIC_clock()) { | ||
549 | /* No broadcast on UP ! */ | ||
550 | if (num_possible_cpus() > 1) | ||
551 | setup_APIC_timer(); | ||
552 | return; | ||
553 | } | ||
554 | |||
555 | /* | ||
556 | * If nmi_watchdog is set to IO_APIC, we need the | ||
557 | * PIT/HPET going. Otherwise register lapic as a dummy | ||
558 | * device. | ||
559 | */ | ||
560 | if (nmi_watchdog != NMI_IO_APIC) | ||
561 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | ||
562 | else | ||
563 | printk(KERN_WARNING "APIC timer registered as dummy," | ||
564 | " due to nmi_watchdog=%d!\n", nmi_watchdog); | ||
565 | |||
562 | /* Setup the lapic or request the broadcast */ | 566 | /* Setup the lapic or request the broadcast */ |
563 | setup_APIC_timer(); | 567 | setup_APIC_timer(); |
564 | } | 568 | } |
@@ -693,44 +697,44 @@ void clear_local_APIC(void) | |||
693 | */ | 697 | */ |
694 | if (maxlvt >= 3) { | 698 | if (maxlvt >= 3) { |
695 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | 699 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
696 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | 700 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
697 | } | 701 | } |
698 | /* | 702 | /* |
699 | * Careful: we have to set masks only first to deassert | 703 | * Careful: we have to set masks only first to deassert |
700 | * any level-triggered sources. | 704 | * any level-triggered sources. |
701 | */ | 705 | */ |
702 | v = apic_read(APIC_LVTT); | 706 | v = apic_read(APIC_LVTT); |
703 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | 707 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
704 | v = apic_read(APIC_LVT0); | 708 | v = apic_read(APIC_LVT0); |
705 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | 709 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
706 | v = apic_read(APIC_LVT1); | 710 | v = apic_read(APIC_LVT1); |
707 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | 711 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
708 | if (maxlvt >= 4) { | 712 | if (maxlvt >= 4) { |
709 | v = apic_read(APIC_LVTPC); | 713 | v = apic_read(APIC_LVTPC); |
710 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | 714 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
711 | } | 715 | } |
712 | 716 | ||
713 | /* lets not touch this if we didn't frob it */ | 717 | /* lets not touch this if we didn't frob it */ |
714 | #ifdef CONFIG_X86_MCE_P4THERMAL | 718 | #ifdef CONFIG_X86_MCE_P4THERMAL |
715 | if (maxlvt >= 5) { | 719 | if (maxlvt >= 5) { |
716 | v = apic_read(APIC_LVTTHMR); | 720 | v = apic_read(APIC_LVTTHMR); |
717 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | 721 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
718 | } | 722 | } |
719 | #endif | 723 | #endif |
720 | /* | 724 | /* |
721 | * Clean APIC state for other OSs: | 725 | * Clean APIC state for other OSs: |
722 | */ | 726 | */ |
723 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | 727 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
724 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | 728 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
725 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | 729 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
726 | if (maxlvt >= 3) | 730 | if (maxlvt >= 3) |
727 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | 731 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
728 | if (maxlvt >= 4) | 732 | if (maxlvt >= 4) |
729 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | 733 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
730 | 734 | ||
731 | #ifdef CONFIG_X86_MCE_P4THERMAL | 735 | #ifdef CONFIG_X86_MCE_P4THERMAL |
732 | if (maxlvt >= 5) | 736 | if (maxlvt >= 5) |
733 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | 737 | apic_write(APIC_LVTTHMR, APIC_LVT_MASKED); |
734 | #endif | 738 | #endif |
735 | /* Integrated APIC (!82489DX) ? */ | 739 | /* Integrated APIC (!82489DX) ? */ |
736 | if (lapic_is_integrated()) { | 740 | if (lapic_is_integrated()) { |
@@ -756,7 +760,7 @@ void disable_local_APIC(void) | |||
756 | */ | 760 | */ |
757 | value = apic_read(APIC_SPIV); | 761 | value = apic_read(APIC_SPIV); |
758 | value &= ~APIC_SPIV_APIC_ENABLED; | 762 | value &= ~APIC_SPIV_APIC_ENABLED; |
759 | apic_write_around(APIC_SPIV, value); | 763 | apic_write(APIC_SPIV, value); |
760 | 764 | ||
761 | /* | 765 | /* |
762 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | 766 | * When LAPIC was disabled by the BIOS and enabled by the kernel, |
@@ -865,8 +869,8 @@ void __init sync_Arb_IDs(void) | |||
865 | apic_wait_icr_idle(); | 869 | apic_wait_icr_idle(); |
866 | 870 | ||
867 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | 871 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
868 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | 872 | apic_write(APIC_ICR, |
869 | | APIC_DM_INIT); | 873 | APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
870 | } | 874 | } |
871 | 875 | ||
872 | /* | 876 | /* |
@@ -902,16 +906,16 @@ void __init init_bsp_APIC(void) | |||
902 | else | 906 | else |
903 | value |= APIC_SPIV_FOCUS_DISABLED; | 907 | value |= APIC_SPIV_FOCUS_DISABLED; |
904 | value |= SPURIOUS_APIC_VECTOR; | 908 | value |= SPURIOUS_APIC_VECTOR; |
905 | apic_write_around(APIC_SPIV, value); | 909 | apic_write(APIC_SPIV, value); |
906 | 910 | ||
907 | /* | 911 | /* |
908 | * Set up the virtual wire mode. | 912 | * Set up the virtual wire mode. |
909 | */ | 913 | */ |
910 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | 914 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
911 | value = APIC_DM_NMI; | 915 | value = APIC_DM_NMI; |
912 | if (!lapic_is_integrated()) /* 82489DX */ | 916 | if (!lapic_is_integrated()) /* 82489DX */ |
913 | value |= APIC_LVT_LEVEL_TRIGGER; | 917 | value |= APIC_LVT_LEVEL_TRIGGER; |
914 | apic_write_around(APIC_LVT1, value); | 918 | apic_write(APIC_LVT1, value); |
915 | } | 919 | } |
916 | 920 | ||
917 | static void __cpuinit lapic_setup_esr(void) | 921 | static void __cpuinit lapic_setup_esr(void) |
@@ -926,7 +930,7 @@ static void __cpuinit lapic_setup_esr(void) | |||
926 | 930 | ||
927 | /* enables sending errors */ | 931 | /* enables sending errors */ |
928 | value = ERROR_APIC_VECTOR; | 932 | value = ERROR_APIC_VECTOR; |
929 | apic_write_around(APIC_LVTERR, value); | 933 | apic_write(APIC_LVTERR, value); |
930 | /* | 934 | /* |
931 | * spec says clear errors after enabling vector. | 935 | * spec says clear errors after enabling vector. |
932 | */ | 936 | */ |
@@ -989,7 +993,7 @@ void __cpuinit setup_local_APIC(void) | |||
989 | */ | 993 | */ |
990 | value = apic_read(APIC_TASKPRI); | 994 | value = apic_read(APIC_TASKPRI); |
991 | value &= ~APIC_TPRI_MASK; | 995 | value &= ~APIC_TPRI_MASK; |
992 | apic_write_around(APIC_TASKPRI, value); | 996 | apic_write(APIC_TASKPRI, value); |
993 | 997 | ||
994 | /* | 998 | /* |
995 | * After a crash, we no longer service the interrupts and a pending | 999 | * After a crash, we no longer service the interrupts and a pending |
@@ -1047,7 +1051,7 @@ void __cpuinit setup_local_APIC(void) | |||
1047 | * Set spurious IRQ vector | 1051 | * Set spurious IRQ vector |
1048 | */ | 1052 | */ |
1049 | value |= SPURIOUS_APIC_VECTOR; | 1053 | value |= SPURIOUS_APIC_VECTOR; |
1050 | apic_write_around(APIC_SPIV, value); | 1054 | apic_write(APIC_SPIV, value); |
1051 | 1055 | ||
1052 | /* | 1056 | /* |
1053 | * Set up LVT0, LVT1: | 1057 | * Set up LVT0, LVT1: |
@@ -1069,7 +1073,7 @@ void __cpuinit setup_local_APIC(void) | |||
1069 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | 1073 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
1070 | smp_processor_id()); | 1074 | smp_processor_id()); |
1071 | } | 1075 | } |
1072 | apic_write_around(APIC_LVT0, value); | 1076 | apic_write(APIC_LVT0, value); |
1073 | 1077 | ||
1074 | /* | 1078 | /* |
1075 | * only the BP should see the LINT1 NMI signal, obviously. | 1079 | * only the BP should see the LINT1 NMI signal, obviously. |
@@ -1080,7 +1084,7 @@ void __cpuinit setup_local_APIC(void) | |||
1080 | value = APIC_DM_NMI | APIC_LVT_MASKED; | 1084 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
1081 | if (!integrated) /* 82489DX */ | 1085 | if (!integrated) /* 82489DX */ |
1082 | value |= APIC_LVT_LEVEL_TRIGGER; | 1086 | value |= APIC_LVT_LEVEL_TRIGGER; |
1083 | apic_write_around(APIC_LVT1, value); | 1087 | apic_write(APIC_LVT1, value); |
1084 | } | 1088 | } |
1085 | 1089 | ||
1086 | void __cpuinit end_local_APIC_setup(void) | 1090 | void __cpuinit end_local_APIC_setup(void) |
@@ -1091,7 +1095,7 @@ void __cpuinit end_local_APIC_setup(void) | |||
1091 | /* Disable the local apic timer */ | 1095 | /* Disable the local apic timer */ |
1092 | value = apic_read(APIC_LVTT); | 1096 | value = apic_read(APIC_LVTT); |
1093 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | 1097 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
1094 | apic_write_around(APIC_LVTT, value); | 1098 | apic_write(APIC_LVTT, value); |
1095 | 1099 | ||
1096 | setup_apic_nmi_watchdog(NULL); | 1100 | setup_apic_nmi_watchdog(NULL); |
1097 | apic_pm_activate(); | 1101 | apic_pm_activate(); |
@@ -1214,9 +1218,6 @@ int apic_version[MAX_APICS]; | |||
1214 | 1218 | ||
1215 | int __init APIC_init_uniprocessor(void) | 1219 | int __init APIC_init_uniprocessor(void) |
1216 | { | 1220 | { |
1217 | if (disable_apic) | ||
1218 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | ||
1219 | |||
1220 | if (!smp_found_config && !cpu_has_apic) | 1221 | if (!smp_found_config && !cpu_has_apic) |
1221 | return -1; | 1222 | return -1; |
1222 | 1223 | ||
@@ -1419,7 +1420,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) | |||
1419 | value &= ~APIC_VECTOR_MASK; | 1420 | value &= ~APIC_VECTOR_MASK; |
1420 | value |= APIC_SPIV_APIC_ENABLED; | 1421 | value |= APIC_SPIV_APIC_ENABLED; |
1421 | value |= 0xf; | 1422 | value |= 0xf; |
1422 | apic_write_around(APIC_SPIV, value); | 1423 | apic_write(APIC_SPIV, value); |
1423 | 1424 | ||
1424 | if (!virt_wire_setup) { | 1425 | if (!virt_wire_setup) { |
1425 | /* | 1426 | /* |
@@ -1432,10 +1433,10 @@ void disconnect_bsp_APIC(int virt_wire_setup) | |||
1432 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | 1433 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
1433 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | 1434 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1434 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | 1435 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
1435 | apic_write_around(APIC_LVT0, value); | 1436 | apic_write(APIC_LVT0, value); |
1436 | } else { | 1437 | } else { |
1437 | /* Disable LVT0 */ | 1438 | /* Disable LVT0 */ |
1438 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | 1439 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
1439 | } | 1440 | } |
1440 | 1441 | ||
1441 | /* | 1442 | /* |
@@ -1449,7 +1450,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) | |||
1449 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | 1450 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
1450 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | 1451 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
1451 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | 1452 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
1452 | apic_write_around(APIC_LVT1, value); | 1453 | apic_write(APIC_LVT1, value); |
1453 | } | 1454 | } |
1454 | } | 1455 | } |
1455 | 1456 | ||
@@ -1700,7 +1701,7 @@ early_param("lapic", parse_lapic); | |||
1700 | static int __init parse_nolapic(char *arg) | 1701 | static int __init parse_nolapic(char *arg) |
1701 | { | 1702 | { |
1702 | disable_apic = 1; | 1703 | disable_apic = 1; |
1703 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | 1704 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
1704 | return 0; | 1705 | return 0; |
1705 | } | 1706 | } |
1706 | early_param("nolapic", parse_nolapic); | 1707 | early_param("nolapic", parse_nolapic); |