13 files changed, 372 insertions, 262 deletions

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index f9cecdfd05c5..098ec84b8c00 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -46,6 +46,7 @@
 #include <asm/idle.h>
 #include <asm/mtrr.h>
 #include <asm/smp.h>
+#include <asm/mce.h>
 
 unsigned int num_processors;
 
@@ -808,7 +809,7 @@ void clear_local_APIC(void)
         u32 v;
 
         /* APIC hasn't been mapped yet */
-        if (!apic_phys)
+        if (!x2apic && !apic_phys)
                 return;
 
         maxlvt = lapic_get_maxlvt();
@@ -842,6 +843,14 @@ void clear_local_APIC(void)
                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
         }
 #endif
+#ifdef CONFIG_X86_MCE_INTEL
+        if (maxlvt >= 6) {
+                v = apic_read(APIC_LVTCMCI);
+                if (!(v & APIC_LVT_MASKED))
+                        apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
+        }
+#endif
+
         /*
          * Clean APIC state for other OSs:
          */
@@ -1241,6 +1250,12 @@ void __cpuinit setup_local_APIC(void)
         apic_write(APIC_LVT1, value);
 
         preempt_enable();
+
+#ifdef CONFIG_X86_MCE_INTEL
+        /* Recheck CMCI information after local APIC is up on CPU #0 */
+        if (smp_processor_id() == 0)
+                cmci_recheck();
+#endif
 }
 
 void __cpuinit end_local_APIC_setup(void)
@@ -1289,6 +1304,7 @@ void __init enable_IR_x2apic(void)
 #ifdef CONFIG_INTR_REMAP
         int ret;
         unsigned long flags;
+        struct IO_APIC_route_entry **ioapic_entries = NULL;
 
         if (!cpu_has_x2apic)
                 return;
@@ -1319,16 +1335,23 @@ void __init enable_IR_x2apic(void)
                 return;
         }
 
-        local_irq_save(flags);
-        mask_8259A();
+        ioapic_entries = alloc_ioapic_entries();
+        if (!ioapic_entries) {
+                pr_info("Allocate ioapic_entries failed: %d\n", ret);
+                goto end;
+        }
 
-        ret = save_mask_IO_APIC_setup();
+        ret = save_IO_APIC_setup(ioapic_entries);
         if (ret) {
                 pr_info("Saving IO-APIC state failed: %d\n", ret);
                 goto end;
         }
 
-        ret = enable_intr_remapping(1);
+        local_irq_save(flags);
+        mask_IO_APIC_setup(ioapic_entries);
+        mask_8259A();
+
+        ret = enable_intr_remapping(EIM_32BIT_APIC_ID);
 
         if (ret && x2apic_preenabled) {
                 local_irq_restore(flags);
@@ -1348,14 +1371,14 @@ end_restore:
                 /*
                  * IR enabling failed
                  */
-                restore_IO_APIC_setup();
+                restore_IO_APIC_setup(ioapic_entries);
         else
-                reinit_intr_remapped_IO_APIC(x2apic_preenabled);
+                reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries);
 
-end:
         unmask_8259A();
         local_irq_restore(flags);
 
+end:
         if (!ret) {
                 if (!x2apic_preenabled)
                         pr_info("Enabled x2apic and interrupt-remapping\n");
@@ -1363,6 +1386,8 @@ end:
                         pr_info("Enabled Interrupt-remapping\n");
         } else
                 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
+        if (ioapic_entries)
+                free_ioapic_entries(ioapic_entries);
 #else
         if (!cpu_has_x2apic)
                 return;
@@ -1508,12 +1533,10 @@ void __init early_init_lapic_mapping(void)
  */
 void __init init_apic_mappings(void)
 {
-#ifdef CONFIG_X86_X2APIC
         if (x2apic) {
                 boot_cpu_physical_apicid = read_apic_id();
                 return;
         }
-#endif
 
         /*
          * If no local APIC can be found then set up a fake all
@@ -1940,6 +1963,10 @@ static int lapic_suspend(struct sys_device *dev, pm_message_t state)
 
         local_irq_save(flags);
         disable_local_APIC();
+#ifdef CONFIG_INTR_REMAP
+        if (intr_remapping_enabled)
+                disable_intr_remapping();
+#endif
         local_irq_restore(flags);
         return 0;
 }
@@ -1950,19 +1977,42 @@ static int lapic_resume(struct sys_device *dev)
         unsigned long flags;
         int maxlvt;
 
+#ifdef CONFIG_INTR_REMAP
+        int ret;
+        struct IO_APIC_route_entry **ioapic_entries = NULL;
+
         if (!apic_pm_state.active)
                 return 0;
 
-        maxlvt = lapic_get_maxlvt();
-
         local_irq_save(flags);
+        if (x2apic) {
+                ioapic_entries = alloc_ioapic_entries();
+                if (!ioapic_entries) {
+                        WARN(1, "Alloc ioapic_entries in lapic resume failed.");
+                        return -ENOMEM;
+                }
 
-#ifdef CONFIG_X86_X2APIC
+                ret = save_IO_APIC_setup(ioapic_entries);
+                if (ret) {
+                        WARN(1, "Saving IO-APIC state failed: %d\n", ret);
+                        free_ioapic_entries(ioapic_entries);
+                        return ret;
+                }
+
+                mask_IO_APIC_setup(ioapic_entries);
+                mask_8259A();
+                enable_x2apic();
+        }
+#else
+        if (!apic_pm_state.active)
+                return 0;
+
+        local_irq_save(flags);
         if (x2apic)
                 enable_x2apic();
-        else
 #endif
-        {
+
+        else {
                 /*
                  * Make sure the APICBASE points to the right address
                  *
@@ -1975,6 +2025,7 @@ static int lapic_resume(struct sys_device *dev)
                 wrmsr(MSR_IA32_APICBASE, l, h);
         }
 
+        maxlvt = lapic_get_maxlvt();
         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
         apic_write(APIC_ID, apic_pm_state.apic_id);
         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
@@ -1998,8 +2049,20 @@ static int lapic_resume(struct sys_device *dev)
         apic_write(APIC_ESR, 0);
         apic_read(APIC_ESR);
 
+#ifdef CONFIG_INTR_REMAP
+        if (intr_remapping_enabled)
+                reenable_intr_remapping(EIM_32BIT_APIC_ID);
+
+        if (x2apic) {
+                unmask_8259A();
+                restore_IO_APIC_setup(ioapic_entries);
+                free_ioapic_entries(ioapic_entries);
+        }
+#endif
+
         local_irq_restore(flags);
 
+
         return 0;
 }
 
@@ -2037,7 +2100,9 @@ static int __init init_lapic_sysfs(void)
                 error = sysdev_register(&device_lapic);
         return error;
 }
-device_initcall(init_lapic_sysfs);
+
+/* local apic needs to resume before other devices access its registers. */
+core_initcall(init_lapic_sysfs);
 
 #else   /* CONFIG_PM */
 
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index f933822dba18..0014714ea97b 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -159,20 +159,6 @@ static int flat_apic_id_registered(void)
         return physid_isset(read_xapic_id(), phys_cpu_present_map);
 }
 
-static unsigned int flat_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
-}
-
-static unsigned int flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                                                const struct cpumask *andmask)
-{
-        unsigned long mask1 = cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
-        unsigned long mask2 = cpumask_bits(andmask)[0] & APIC_ALL_CPUS;
-
-        return mask1 & mask2;
-}
-
 static int flat_phys_pkg_id(int initial_apic_id, int index_msb)
 {
         return hard_smp_processor_id() >> index_msb;
@@ -213,8 +199,8 @@ struct apic apic_flat =  {
         .set_apic_id                    = set_apic_id,
         .apic_id_mask                   = 0xFFu << 24,
 
-        .cpu_mask_to_apicid             = flat_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = flat_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid             = default_cpu_mask_to_apicid,
+        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = flat_send_IPI_mask,
         .send_IPI_mask_allbutself       = flat_send_IPI_mask_allbutself,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index d806ecaa948f..676cdac385c0 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -26,12 +26,12 @@ static int bigsmp_apic_id_registered(void)
         return 1;
 }
 
-static const cpumask_t *bigsmp_target_cpus(void)
+static const struct cpumask *bigsmp_target_cpus(void)
 {
 #ifdef CONFIG_SMP
-        return &cpu_online_map;
+        return cpu_online_mask;
 #else
-        return &cpumask_of_cpu(0);
+        return cpumask_of(0);
 #endif
 }
 
@@ -118,9 +118,9 @@ static int bigsmp_check_phys_apicid_present(int boot_cpu_physical_apicid)
 }
 
 /* As we are using single CPU as destination, pick only one CPU here */
-static unsigned int bigsmp_cpu_mask_to_apicid(const cpumask_t *cpumask)
+static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask)
 {
-        return bigsmp_cpu_to_logical_apicid(first_cpu(*cpumask));
+        return bigsmp_cpu_to_logical_apicid(cpumask_first(cpumask));
 }
 
 static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
@@ -188,10 +188,10 @@ static const struct dmi_system_id bigsmp_dmi_table[] = {
         { } /* NULL entry stops DMI scanning */
 };
 
-static void bigsmp_vector_allocation_domain(int cpu, cpumask_t *retmask)
+static void bigsmp_vector_allocation_domain(int cpu, struct cpumask *retmask)
 {
-        cpus_clear(*retmask);
-        cpu_set(cpu, *retmask);
+        cpumask_clear(retmask);
+        cpumask_set_cpu(cpu, retmask);
 }
 
 static int probe_bigsmp(void)
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 19588f2770ee..1c11b819f245 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -410,7 +410,7 @@ static void es7000_enable_apic_mode(void)
                 WARN(1, "Command failed, status = %x\n", mip_status);
 }
 
-static void es7000_vector_allocation_domain(int cpu, cpumask_t *retmask)
+static void es7000_vector_allocation_domain(int cpu, struct cpumask *retmask)
 {
         /* Careful. Some cpus do not strictly honor the set of cpus
          * specified in the interrupt destination when using lowest
@@ -420,7 +420,8 @@ static void es7000_vector_allocation_domain(int cpu, cpumask_t *retmask)
          * deliver interrupts to the wrong hyperthread when only one
          * hyperthread was specified in the interrupt desitination.
          */
-        *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
+        cpumask_clear(retmask);
+        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 }
 
 
@@ -455,14 +456,14 @@ static int es7000_apic_id_registered(void)
         return 1;
 }
 
-static const cpumask_t *target_cpus_cluster(void)
+static const struct cpumask *target_cpus_cluster(void)
 {
-        return &CPU_MASK_ALL;
+        return cpu_all_mask;
 }
 
-static const cpumask_t *es7000_target_cpus(void)
+static const struct cpumask *es7000_target_cpus(void)
 {
-        return &cpumask_of_cpu(smp_processor_id());
+        return cpumask_of(smp_processor_id());
 }
 
 static unsigned long
@@ -517,7 +518,7 @@ static void es7000_setup_apic_routing(void)
           "Enabling APIC mode:  %s. Using %d I/O APICs, target cpus %lx\n",
                 (apic_version[apic] == 0x14) ?
                         "Physical Cluster" : "Logical Cluster",
-                nr_ioapics, cpus_addr(*es7000_target_cpus())[0]);
+                nr_ioapics, cpumask_bits(es7000_target_cpus())[0]);
 }
 
 static int es7000_apicid_to_node(int logical_apicid)
@@ -572,7 +573,7 @@ static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
         return 1;
 }
 
-static unsigned int es7000_cpu_mask_to_apicid(const cpumask_t *cpumask)
+static unsigned int es7000_cpu_mask_to_apicid(const struct cpumask *cpumask)
 {
         unsigned int round = 0;
         int cpu, uninitialized_var(apicid);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 00e6071cefc4..767fe7e46d68 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -389,6 +389,8 @@ struct io_apic {
         unsigned int index;
         unsigned int unused[3];
         unsigned int data;
+        unsigned int unused2[11];
+        unsigned int eoi;
 };
 
 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
@@ -397,6 +399,12 @@ static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 }
 
+static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
+{
+        struct io_apic __iomem *io_apic = io_apic_base(apic);
+        writel(vector, &io_apic->eoi);
+}
+
 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 {
         struct io_apic __iomem *io_apic = io_apic_base(apic);
@@ -546,16 +554,12 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
 
                 apic = entry->apic;
                 pin = entry->pin;
-#ifdef CONFIG_INTR_REMAP
                 /*
                  * With interrupt-remapping, destination information comes
                  * from interrupt-remapping table entry.
                  */
                 if (!irq_remapped(irq))
                         io_apic_write(apic, 0x11 + pin*2, dest);
-#else
-                io_apic_write(apic, 0x11 + pin*2, dest);
-#endif
                 reg = io_apic_read(apic, 0x10 + pin*2);
                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
                 reg |= vector;
@@ -588,10 +592,12 @@ set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
         if (assign_irq_vector(irq, cfg, mask))
                 return BAD_APICID;
 
-        cpumask_and(desc->affinity, cfg->domain, mask);
+        /* check that before desc->addinity get updated */
         set_extra_move_desc(desc, mask);
 
-        return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
+        cpumask_copy(desc->affinity, mask);
+
+        return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
 }
 
 static void
@@ -845,75 +851,106 @@ __setup("pirq=", ioapic_pirq_setup);
 #endif /* CONFIG_X86_32 */
 
 #ifdef CONFIG_INTR_REMAP
-/* I/O APIC RTE contents at the OS boot up */
-static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
+struct IO_APIC_route_entry **alloc_ioapic_entries(void)
+{
+        int apic;
+        struct IO_APIC_route_entry **ioapic_entries;
+
+        ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
+                                GFP_ATOMIC);
+        if (!ioapic_entries)
+                return 0;
+
+        for (apic = 0; apic < nr_ioapics; apic++) {
+                ioapic_entries[apic] =
+                        kzalloc(sizeof(struct IO_APIC_route_entry) *
+                                nr_ioapic_registers[apic], GFP_ATOMIC);
+                if (!ioapic_entries[apic])
+                        goto nomem;
+        }
+
+        return ioapic_entries;
+
+nomem:
+        while (--apic >= 0)
+                kfree(ioapic_entries[apic]);
+        kfree(ioapic_entries);
+
+        return 0;
+}
 
 /*
- * Saves and masks all the unmasked IO-APIC RTE's
+ * Saves all the IO-APIC RTE's
  */
-int save_mask_IO_APIC_setup(void)
+int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 {
-        union IO_APIC_reg_01 reg_01;
-        unsigned long flags;
         int apic, pin;
 
-        /*
-         * The number of IO-APIC IRQ registers (== #pins):
-         */
+        if (!ioapic_entries)
+                return -ENOMEM;
+
         for (apic = 0; apic < nr_ioapics; apic++) {
-                spin_lock_irqsave(&ioapic_lock, flags);
-                reg_01.raw = io_apic_read(apic, 1);
-                spin_unlock_irqrestore(&ioapic_lock, flags);
-                nr_ioapic_registers[apic] = reg_01.bits.entries+1;
+                if (!ioapic_entries[apic])
+                        return -ENOMEM;
+
+                for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+                        ioapic_entries[apic][pin] =
+                                ioapic_read_entry(apic, pin);
         }
 
+        return 0;
+}
+
+/*
+ * Mask all IO APIC entries.
+ */
+void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
+{
+        int apic, pin;
+
+        if (!ioapic_entries)
+                return;
+
         for (apic = 0; apic < nr_ioapics; apic++) {
-                early_ioapic_entries[apic] =
-                        kzalloc(sizeof(struct IO_APIC_route_entry) *
-                                nr_ioapic_registers[apic], GFP_KERNEL);
-                if (!early_ioapic_entries[apic])
-                        goto nomem;
-        }
+                if (!ioapic_entries[apic])
+                        break;
 
-        for (apic = 0; apic < nr_ioapics; apic++)
                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
                         struct IO_APIC_route_entry entry;
 
-                        entry = early_ioapic_entries[apic][pin] =
-                                ioapic_read_entry(apic, pin);
+                        entry = ioapic_entries[apic][pin];
                         if (!entry.mask) {
                                 entry.mask = 1;
                                 ioapic_write_entry(apic, pin, entry);
                         }
                 }
-
-        return 0;
-
-nomem:
-        while (apic >= 0)
-                kfree(early_ioapic_entries[apic--]);
-        memset(early_ioapic_entries, 0,
-                ARRAY_SIZE(early_ioapic_entries));
-
-        return -ENOMEM;
+        }
 }
 
-void restore_IO_APIC_setup(void)
+/*
+ * Restore IO APIC entries which was saved in ioapic_entries.
+ */
+int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
 {
         int apic, pin;
 
+        if (!ioapic_entries)
+                return -ENOMEM;
+
         for (apic = 0; apic < nr_ioapics; apic++) {
-                if (!early_ioapic_entries[apic])
-                        break;
+                if (!ioapic_entries[apic])
+                        return -ENOMEM;
+
                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
                         ioapic_write_entry(apic, pin,
-                                           early_ioapic_entries[apic][pin]);
-                kfree(early_ioapic_entries[apic]);
-                early_ioapic_entries[apic] = NULL;
+                                        ioapic_entries[apic][pin]);
         }
+        return 0;
 }
 
-void reinit_intr_remapped_IO_APIC(int intr_remapping)
+void reinit_intr_remapped_IO_APIC(int intr_remapping,
+        struct IO_APIC_route_entry **ioapic_entries)
+
 {
         /*
          * for now plain restore of previous settings.
@@ -922,7 +959,17 @@ void reinit_intr_remapped_IO_APIC(int intr_remapping)
          * table entries. for now, do a plain restore, and wait for
          * the setup_IO_APIC_irqs() to do proper initialization.
          */
-        restore_IO_APIC_setup();
+        restore_IO_APIC_setup(ioapic_entries);
+}
+
+void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
+{
+        int apic;
+
+        for (apic = 0; apic < nr_ioapics; apic++)
+                kfree(ioapic_entries[apic]);
+
+        kfree(ioapic_entries);
 }
 #endif
 
@@ -1411,9 +1458,7 @@ void __setup_vector_irq(int cpu)
 }
 
 static struct irq_chip ioapic_chip;
-#ifdef CONFIG_INTR_REMAP
 static struct irq_chip ir_ioapic_chip;
-#endif
 
 #define IOAPIC_AUTO     -1
 #define IOAPIC_EDGE     0
@@ -1452,7 +1497,6 @@ static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long t
         else
                 desc->status &= ~IRQ_LEVEL;
 
-#ifdef CONFIG_INTR_REMAP
         if (irq_remapped(irq)) {
                 desc->status |= IRQ_MOVE_PCNTXT;
                 if (trigger)
@@ -1464,7 +1508,7 @@ static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long t
                                                       handle_edge_irq, "edge");
                 return;
         }
-#endif
+
         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
             trigger == IOAPIC_LEVEL)
                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
@@ -1478,14 +1522,13 @@ static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long t
 int setup_ioapic_entry(int apic_id, int irq,
                        struct IO_APIC_route_entry *entry,
                        unsigned int destination, int trigger,
-                       int polarity, int vector)
+                       int polarity, int vector, int pin)
 {
         /*
          * add it to the IO-APIC irq-routing table:
          */
         memset(entry,0,sizeof(*entry));
 
-#ifdef CONFIG_INTR_REMAP
         if (intr_remapping_enabled) {
                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
                 struct irte irte;
@@ -1504,7 +1547,14 @@ int setup_ioapic_entry(int apic_id, int irq,
 
                 irte.present = 1;
                 irte.dst_mode = apic->irq_dest_mode;
-                irte.trigger_mode = trigger;
+                /*
+                 * Trigger mode in the IRTE will always be edge, and the
+                 * actual level or edge trigger will be setup in the IO-APIC
+                 * RTE. This will help simplify level triggered irq migration.
+                 * For more details, see the comments above explainig IO-APIC
+                 * irq migration in the presence of interrupt-remapping.
+                 */
+                irte.trigger_mode = 0;
                 irte.dlvry_mode = apic->irq_delivery_mode;
                 irte.vector = vector;
                 irte.dest_id = IRTE_DEST(destination);
@@ -1515,18 +1565,21 @@ int setup_ioapic_entry(int apic_id, int irq,
                 ir_entry->zero = 0;
                 ir_entry->format = 1;
                 ir_entry->index = (index & 0x7fff);
-        } else
-#endif
-        {
+                /*
+                 * IO-APIC RTE will be configured with virtual vector.
+                 * irq handler will do the explicit EOI to the io-apic.
+                 */
+                ir_entry->vector = pin;
+        } else {
                 entry->delivery_mode = apic->irq_delivery_mode;
                 entry->dest_mode = apic->irq_dest_mode;
                 entry->dest = destination;
+                entry->vector = vector;
         }
 
         entry->mask = 0;                                /* enable IRQ */
         entry->trigger = trigger;
         entry->polarity = polarity;
-        entry->vector = vector;
 
         /* Mask level triggered irqs.
          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
@@ -1561,7 +1614,7 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq
 
 
         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
-                               dest, trigger, polarity, cfg->vector)) {
+                               dest, trigger, polarity, cfg->vector, pin)) {
                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
                        mp_ioapics[apic_id].apicid, pin);
                 __clear_irq_vector(irq, cfg);
@@ -1642,10 +1695,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
 {
         struct IO_APIC_route_entry entry;
 
-#ifdef CONFIG_INTR_REMAP
         if (intr_remapping_enabled)
                 return;
-#endif
 
         memset(&entry, 0, sizeof(entry));
 
@@ -2040,8 +2091,13 @@ void disable_IO_APIC(void)
          * If the i8259 is routed through an IOAPIC
          * Put that IOAPIC in virtual wire mode
          * so legacy interrupts can be delivered.
+         *
+         * With interrupt-remapping, for now we will use virtual wire A mode,
+         * as virtual wire B is little complex (need to configure both
+         * IOAPIC RTE aswell as interrupt-remapping table entry).
+         * As this gets called during crash dump, keep this simple for now.
          */
-        if (ioapic_i8259.pin != -1) {
+        if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
                 struct IO_APIC_route_entry entry;
 
                 memset(&entry, 0, sizeof(entry));
@@ -2061,7 +2117,10 @@ void disable_IO_APIC(void)
                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
         }
 
-        disconnect_bsp_APIC(ioapic_i8259.pin != -1);
+        /*
+         * Use virtual wire A mode when interrupt remapping is enabled.
+         */
+        disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
 }
 
 #ifdef CONFIG_X86_32
@@ -2303,37 +2362,24 @@ static int ioapic_retrigger_irq(unsigned int irq)
 #ifdef CONFIG_SMP
 
 #ifdef CONFIG_INTR_REMAP
-static void ir_irq_migration(struct work_struct *work);
-
-static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
 
 /*
  * Migrate the IO-APIC irq in the presence of intr-remapping.
  *
- * For edge triggered, irq migration is a simple atomic update(of vector
- * and cpu destination) of IRTE and flush the hardware cache.
- *
- * For level triggered, we need to modify the io-apic RTE aswell with the update
- * vector information, along with modifying IRTE with vector and destination.
- * So irq migration for level triggered is little  bit more complex compared to
- * edge triggered migration. But the good news is, we use the same algorithm
- * for level triggered migration as we have today, only difference being,
- * we now initiate the irq migration from process context instead of the
- * interrupt context.
+ * For both level and edge triggered, irq migration is a simple atomic
+ * update(of vector and cpu destination) of IRTE and flush the hardware cache.
  *
- * In future, when we do a directed EOI (combined with cpu EOI broadcast
- * suppression) to the IO-APIC, level triggered irq migration will also be
- * as simple as edge triggered migration and we can do the irq migration
- * with a simple atomic update to IO-APIC RTE.
+ * For level triggered, we eliminate the io-apic RTE modification (with the
+ * updated vector information), by using a virtual vector (io-apic pin number).
+ * Real vector that is used for interrupting cpu will be coming from
+ * the interrupt-remapping table entry.
  */
 static void
 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 {
         struct irq_cfg *cfg;
         struct irte irte;
-        int modify_ioapic_rte;
         unsigned int dest;
-        unsigned long flags;
         unsigned int irq;
 
         if (!cpumask_intersects(mask, cpu_online_mask))
@@ -2351,13 +2397,6 @@ migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 
         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
 
-        modify_ioapic_rte = desc->status & IRQ_LEVEL;
-        if (modify_ioapic_rte) {
-                spin_lock_irqsave(&ioapic_lock, flags);
-                __target_IO_APIC_irq(irq, dest, cfg);
-                spin_unlock_irqrestore(&ioapic_lock, flags);
-        }
-
         irte.vector = cfg->vector;
         irte.dest_id = IRTE_DEST(dest);
 
@@ -2372,73 +2411,12 @@ migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
         cpumask_copy(desc->affinity, mask);
 }
 
-static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
-{
-        int ret = -1;
-        struct irq_cfg *cfg = desc->chip_data;
-
-        mask_IO_APIC_irq_desc(desc);
-
-        if (io_apic_level_ack_pending(cfg)) {
-                /*
-                 * Interrupt in progress. Migrating irq now will change the
-                 * vector information in the IO-APIC RTE and that will confuse
-                 * the EOI broadcast performed by cpu.
-                 * So, delay the irq migration to the next instance.
-                 */
-                schedule_delayed_work(&ir_migration_work, 1);
-                goto unmask;
-        }
-
-        /* everthing is clear. we have right of way */
-        migrate_ioapic_irq_desc(desc, desc->pending_mask);
-
-        ret = 0;
-        desc->status &= ~IRQ_MOVE_PENDING;
-        cpumask_clear(desc->pending_mask);
-
-unmask:
-        unmask_IO_APIC_irq_desc(desc);
-
-        return ret;
-}
-
-static void ir_irq_migration(struct work_struct *work)
-{
-        unsigned int irq;
-        struct irq_desc *desc;
-
-        for_each_irq_desc(irq, desc) {
-                if (desc->status & IRQ_MOVE_PENDING) {
-                        unsigned long flags;
-
-                        spin_lock_irqsave(&desc->lock, flags);
-                        if (!desc->chip->set_affinity ||
-                            !(desc->status & IRQ_MOVE_PENDING)) {
-                                desc->status &= ~IRQ_MOVE_PENDING;
-                                spin_unlock_irqrestore(&desc->lock, flags);
-                                continue;
-                        }
-
-                        desc->chip->set_affinity(irq, desc->pending_mask);
-                        spin_unlock_irqrestore(&desc->lock, flags);
-                }
-        }
-}
-
 /*
  * Migrates the IRQ destination in the process context.
  */
 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
                                             const struct cpumask *mask)
 {
-        if (desc->status & IRQ_LEVEL) {
-                desc->status |= IRQ_MOVE_PENDING;
-                cpumask_copy(desc->pending_mask, mask);
-                migrate_irq_remapped_level_desc(desc);
-                return;
-        }
-
         migrate_ioapic_irq_desc(desc, mask);
 }
 static void set_ir_ioapic_affinity_irq(unsigned int irq,
@@ -2448,6 +2426,11 @@ static void set_ir_ioapic_affinity_irq(unsigned int irq,
 
         set_ir_ioapic_affinity_irq_desc(desc, mask);
 }
+#else
+static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
+                                                   const struct cpumask *mask)
+{
+}
 #endif
 
 asmlinkage void smp_irq_move_cleanup_interrupt(void)
@@ -2461,6 +2444,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
         me = smp_processor_id();
         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
                 unsigned int irq;
+                unsigned int irr;
                 struct irq_desc *desc;
                 struct irq_cfg *cfg;
                 irq = __get_cpu_var(vector_irq)[vector];
@@ -2480,6 +2464,18 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
                         goto unlock;
 
+                irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
+                /*
+                 * Check if the vector that needs to be cleanedup is
+                 * registered at the cpu's IRR. If so, then this is not
+                 * the best time to clean it up. Lets clean it up in the
+                 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
+                 * to myself.
+                 */
+                if (irr  & (1 << (vector % 32))) {
+                        apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
+                        goto unlock;
+                }
                 __get_cpu_var(vector_irq)[vector] = -1;
                 cfg->move_cleanup_count--;
 unlock:
@@ -2528,17 +2524,51 @@ static void irq_complete_move(struct irq_desc **descp)
 static inline void irq_complete_move(struct irq_desc **descp) {}
 #endif
 
-#ifdef CONFIG_INTR_REMAP
+#ifdef CONFIG_X86_X2APIC
+static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
+{
+        int apic, pin;
+        struct irq_pin_list *entry;
+
+        entry = cfg->irq_2_pin;
+        for (;;) {
+
+                if (!entry)
+                        break;
+
+                apic = entry->apic;
+                pin = entry->pin;
+                io_apic_eoi(apic, pin);
+                entry = entry->next;
+        }
+}
+
+static void
+eoi_ioapic_irq(struct irq_desc *desc)
+{
+        struct irq_cfg *cfg;
+        unsigned long flags;
+        unsigned int irq;
+
+        irq = desc->irq;
+        cfg = desc->chip_data;
+
+        spin_lock_irqsave(&ioapic_lock, flags);
+        __eoi_ioapic_irq(irq, cfg);
+        spin_unlock_irqrestore(&ioapic_lock, flags);
+}
+
 static void ack_x2apic_level(unsigned int irq)
 {
+        struct irq_desc *desc = irq_to_desc(irq);
         ack_x2APIC_irq();
+        eoi_ioapic_irq(desc);
 }
 
 static void ack_x2apic_edge(unsigned int irq)
 {
         ack_x2APIC_irq();
 }
-
 #endif
 
 static void ack_apic_edge(unsigned int irq)
@@ -2649,6 +2679,26 @@ static void ack_apic_level(unsigned int irq)
 #endif
 }
 
+#ifdef CONFIG_INTR_REMAP
+static void ir_ack_apic_edge(unsigned int irq)
+{
+#ifdef CONFIG_X86_X2APIC
+       if (x2apic_enabled())
+               return ack_x2apic_edge(irq);
+#endif
+       return ack_apic_edge(irq);
+}
+
+static void ir_ack_apic_level(unsigned int irq)
+{
+#ifdef CONFIG_X86_X2APIC
+       if (x2apic_enabled())
+               return ack_x2apic_level(irq);
+#endif
+       return ack_apic_level(irq);
+}
+#endif /* CONFIG_INTR_REMAP */
+
 static struct irq_chip ioapic_chip __read_mostly = {
         .name           = "IO-APIC",
         .startup        = startup_ioapic_irq,
@@ -2662,20 +2712,20 @@ static struct irq_chip ioapic_chip __read_mostly = {
         .retrigger      = ioapic_retrigger_irq,
 };
 
-#ifdef CONFIG_INTR_REMAP
 static struct irq_chip ir_ioapic_chip __read_mostly = {
         .name           = "IR-IO-APIC",
         .startup        = startup_ioapic_irq,
         .mask           = mask_IO_APIC_irq,
         .unmask         = unmask_IO_APIC_irq,
-        .ack            = ack_x2apic_edge,
-        .eoi            = ack_x2apic_level,
+#ifdef CONFIG_INTR_REMAP
+        .ack            = ir_ack_apic_edge,
+        .eoi            = ir_ack_apic_level,
 #ifdef CONFIG_SMP
         .set_affinity   = set_ir_ioapic_affinity_irq,
 #endif
+#endif
         .retrigger      = ioapic_retrigger_irq,
 };
-#endif
 
 static inline void init_IO_APIC_traps(void)
 {
@@ -2901,10 +2951,8 @@ static inline void __init check_timer(void)
          * 8259A.
          */
         if (pin1 == -1) {
-#ifdef CONFIG_INTR_REMAP
                 if (intr_remapping_enabled)
                         panic("BIOS bug: timer not connected to IO-APIC");
-#endif
                 pin1 = pin2;
                 apic1 = apic2;
                 no_pin1 = 1;
@@ -2940,10 +2988,8 @@ static inline void __init check_timer(void)
                                 clear_IO_APIC_pin(0, pin1);
                         goto out;
                 }
-#ifdef CONFIG_INTR_REMAP
                 if (intr_remapping_enabled)
                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
-#endif
                 local_irq_disable();
                 clear_IO_APIC_pin(apic1, pin1);
                 if (!no_pin1)
@@ -3237,9 +3283,7 @@ void destroy_irq(unsigned int irq)
         if (desc)
                 desc->chip_data = cfg;
 
-#ifdef CONFIG_INTR_REMAP
         free_irte(irq);
-#endif
         spin_lock_irqsave(&vector_lock, flags);
         __clear_irq_vector(irq, cfg);
         spin_unlock_irqrestore(&vector_lock, flags);
@@ -3265,7 +3309,6 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
 
         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
 
-#ifdef CONFIG_INTR_REMAP
         if (irq_remapped(irq)) {
                 struct irte irte;
                 int ir_index;
@@ -3291,10 +3334,13 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
                                   MSI_ADDR_IR_SHV |
                                   MSI_ADDR_IR_INDEX1(ir_index) |
                                   MSI_ADDR_IR_INDEX2(ir_index);
-        } else
-#endif
-        {
-                msg->address_hi = MSI_ADDR_BASE_HI;
+        } else {
+                if (x2apic_enabled())
+                        msg->address_hi = MSI_ADDR_BASE_HI |
+                                          MSI_ADDR_EXT_DEST_ID(dest);
+                else
+                        msg->address_hi = MSI_ADDR_BASE_HI;
+
                 msg->address_lo =
                         MSI_ADDR_BASE_LO |
                         ((apic->irq_dest_mode == 0) ?
@@ -3394,15 +3440,16 @@ static struct irq_chip msi_chip = {
         .retrigger      = ioapic_retrigger_irq,
 };
 
-#ifdef CONFIG_INTR_REMAP
 static struct irq_chip msi_ir_chip = {
         .name           = "IR-PCI-MSI",
         .unmask         = unmask_msi_irq,
         .mask           = mask_msi_irq,
-        .ack            = ack_x2apic_edge,
+#ifdef CONFIG_INTR_REMAP
+        .ack            = ir_ack_apic_edge,
 #ifdef CONFIG_SMP
         .set_affinity   = ir_set_msi_irq_affinity,
 #endif
+#endif
         .retrigger      = ioapic_retrigger_irq,
 };
 
@@ -3432,7 +3479,6 @@ static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
         }
         return index;
 }
-#endif
 
 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
 {
@@ -3446,7 +3492,6 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
         set_irq_msi(irq, msidesc);
         write_msi_msg(irq, &msg);
 
-#ifdef CONFIG_INTR_REMAP
         if (irq_remapped(irq)) {
                 struct irq_desc *desc = irq_to_desc(irq);
                 /*
@@ -3455,7 +3500,6 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
                 desc->status |= IRQ_MOVE_PCNTXT;
                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
         } else
-#endif
                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
 
         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
@@ -3469,11 +3513,12 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         int ret, sub_handle;
         struct msi_desc *msidesc;
         unsigned int irq_want;
-
-#ifdef CONFIG_INTR_REMAP
-        struct intel_iommu *iommu = 0;
+        struct intel_iommu *iommu = NULL;
         int index = 0;
-#endif
+
+        /* x86 doesn't support multiple MSI yet */
+        if (type == PCI_CAP_ID_MSI && nvec > 1)
+                return 1;
 
         irq_want = nr_irqs_gsi;
         sub_handle = 0;
@@ -3482,7 +3527,6 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                 if (irq == 0)
                         return -1;
                 irq_want = irq + 1;
-#ifdef CONFIG_INTR_REMAP
                 if (!intr_remapping_enabled)
                         goto no_ir;
 
@@ -3510,7 +3554,6 @@ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                         set_irte_irq(irq, iommu, index, sub_handle);
                 }
 no_ir:
-#endif
                 ret = setup_msi_irq(dev, msidesc, irq);
                 if (ret < 0)
                         goto error;
@@ -3528,7 +3571,7 @@ void arch_teardown_msi_irq(unsigned int irq)
         destroy_irq(irq);
 }
 
-#ifdef CONFIG_DMAR
+#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
 #ifdef CONFIG_SMP
 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 {
@@ -3609,7 +3652,7 @@ static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
 
 #endif /* CONFIG_SMP */
 
-struct irq_chip hpet_msi_type = {
+static struct irq_chip hpet_msi_type = {
         .name = "HPET_MSI",
         .unmask = hpet_msi_unmask,
         .mask = hpet_msi_mask,
@@ -4045,11 +4088,9 @@ void __init setup_ioapic_dest(void)
                         else
                                 mask = apic->target_cpus();
 
-#ifdef CONFIG_INTR_REMAP
                         if (intr_remapping_enabled)
                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
                         else
-#endif
                                 set_ioapic_affinity_irq_desc(desc, mask);
                 }
 
@@ -4142,9 +4183,12 @@ static int __init ioapic_insert_resources(void)
         struct resource *r = ioapic_resources;
 
         if (!r) {
-                printk(KERN_ERR
-                       "IO APIC resources could be not be allocated.\n");
-                return -1;
+                if (nr_ioapics > 0) {
+                        printk(KERN_ERR
+                                "IO APIC resources couldn't be allocated.\n");
+                        return -1;
+                }
+                return 0;
         }
 
         for (i = 0; i < nr_ioapics; i++) {
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
index bdfad80c3cf1..d6bd62407152 100644
--- a/arch/x86/kernel/apic/nmi.c
+++ b/arch/x86/kernel/apic/nmi.c
@@ -39,7 +39,7 @@
 int unknown_nmi_panic;
 int nmi_watchdog_enabled;
 
-static cpumask_t backtrace_mask = CPU_MASK_NONE;
+static cpumask_var_t backtrace_mask;
 
 /* nmi_active:
  * >0: the lapic NMI watchdog is active, but can be disabled
@@ -138,6 +138,7 @@ int __init check_nmi_watchdog(void)
         if (!prev_nmi_count)
                 goto error;
 
+        alloc_cpumask_var(&backtrace_mask, GFP_KERNEL);
         printk(KERN_INFO "Testing NMI watchdog ... ");
 
 #ifdef CONFIG_SMP
@@ -413,14 +414,14 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
                 touched = 1;
         }
 
-        if (cpu_isset(cpu, backtrace_mask)) {
+        if (cpumask_test_cpu(cpu, backtrace_mask)) {
                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 
                 spin_lock(&lock);
                 printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
                 dump_stack();
                 spin_unlock(&lock);
-                cpu_clear(cpu, backtrace_mask);
+                cpumask_clear_cpu(cpu, backtrace_mask);
         }
 
         /* Could check oops_in_progress here too, but it's safer not to */
@@ -554,10 +555,10 @@ void __trigger_all_cpu_backtrace(void)
 {
         int i;
 
-        backtrace_mask = cpu_online_map;
+        cpumask_copy(backtrace_mask, cpu_online_mask);
         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
         for (i = 0; i < 10 * 1000; i++) {
-                if (cpus_empty(backtrace_mask))
+                if (cpumask_empty(backtrace_mask))
                         break;
                 mdelay(1);
         }
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index ba2fc6465534..533e59c6fc82 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -334,9 +334,9 @@ static inline void numaq_smp_callin_clear_local_apic(void)
         clear_local_APIC();
 }
 
-static inline const cpumask_t *numaq_target_cpus(void)
+static inline const struct cpumask *numaq_target_cpus(void)
 {
-        return &CPU_MASK_ALL;
+        return cpu_all_mask;
 }
 
 static inline unsigned long
@@ -427,7 +427,7 @@ static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
  * We use physical apicids here, not logical, so just return the default
  * physical broadcast to stop people from breaking us
  */
-static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask)
+static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask)
 {
         return 0x0F;
 }
@@ -462,7 +462,7 @@ static int probe_numaq(void)
         return found_numaq;
 }
 
-static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask)
+static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask)
 {
         /* Careful. Some cpus do not strictly honor the set of cpus
          * specified in the interrupt destination when using lowest
@@ -472,7 +472,8 @@ static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask)
          * deliver interrupts to the wrong hyperthread when only one
          * hyperthread was specified in the interrupt desitination.
          */
-        *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
+        cpumask_clear(retmask);
+        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 }
 
 static void numaq_setup_portio_remap(void)
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 141c99a1c264..01eda2ac65e4 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -83,7 +83,8 @@ static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
          * deliver interrupts to the wrong hyperthread when only one
          * hyperthread was specified in the interrupt desitination.
          */
-        *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
+        cpumask_clear(retmask);
+        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 }
 
 /* should be called last. */
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index 8d7748efe6a8..1783652bb0e5 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -68,6 +68,13 @@ void __init default_setup_apic_routing(void)
                         apic = &apic_physflat;
                 printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
         }
+
+        /*
+         * Now that apic routing model is selected, configure the
+         * fault handling for intr remapping.
+         */
+        if (intr_remapping_enabled)
+                enable_drhd_fault_handling();
 }
 
 /* Same for both flat and physical. */
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index aac52fa873ff..9cfe1f415d81 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -53,23 +53,19 @@ static unsigned summit_get_apic_id(unsigned long x)
         return (x >> 24) & 0xFF;
 }
 
-static inline void summit_send_IPI_mask(const cpumask_t *mask, int vector)
+static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
 {
         default_send_IPI_mask_sequence_logical(mask, vector);
 }
 
 static void summit_send_IPI_allbutself(int vector)
 {
-        cpumask_t mask = cpu_online_map;
-        cpu_clear(smp_processor_id(), mask);
-
-        if (!cpus_empty(mask))
-                summit_send_IPI_mask(&mask, vector);
+        default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
 }
 
 static void summit_send_IPI_all(int vector)
 {
-        summit_send_IPI_mask(&cpu_online_map, vector);
+        summit_send_IPI_mask(cpu_online_mask, vector);
 }
 
 #include <asm/tsc.h>
@@ -186,13 +182,13 @@ static inline int is_WPEG(struct rio_detail *rio){
 
 #define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
 
-static const cpumask_t *summit_target_cpus(void)
+static const struct cpumask *summit_target_cpus(void)
 {
         /* CPU_MASK_ALL (0xff) has undefined behaviour with
          * dest_LowestPrio mode logical clustered apic interrupt routing
          * Just start on cpu 0.  IRQ balancing will spread load
          */
-        return &cpumask_of_cpu(0);
+        return cpumask_of(0);
 }
 
 static unsigned long summit_check_apicid_used(physid_mask_t bitmap, int apicid)
@@ -289,7 +285,7 @@ static int summit_check_phys_apicid_present(int boot_cpu_physical_apicid)
         return 1;
 }
 
-static unsigned int summit_cpu_mask_to_apicid(const cpumask_t *cpumask)
+static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask)
 {
         unsigned int round = 0;
         int cpu, apicid = 0;
@@ -346,7 +342,7 @@ static int probe_summit(void)
         return 0;
 }
 
-static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask)
+static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask)
 {
         /* Careful. Some cpus do not strictly honor the set of cpus
          * specified in the interrupt destination when using lowest
@@ -356,7 +352,8 @@ static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask)
          * deliver interrupts to the wrong hyperthread when only one
          * hyperthread was specified in the interrupt desitination.
          */
-        *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
+        cpumask_clear(retmask);
+        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
 }
 
 #ifdef CONFIG_X86_SUMMIT_NUMA
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 8fb87b6dd633..4a903e2f0d17 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -57,6 +57,8 @@ static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_cpu(query_cpu, mask) {
                 __x2apic_send_IPI_dest(
@@ -73,6 +75,8 @@ static void
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_cpu(query_cpu, mask) {
                 if (query_cpu == this_cpu)
@@ -90,6 +94,8 @@ static void x2apic_send_IPI_allbutself(int vector)
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_online_cpu(query_cpu) {
                 if (query_cpu == this_cpu)
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 23625b9f98b2..a284359627e7 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -58,6 +58,8 @@ static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_cpu(query_cpu, mask) {
                 __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
@@ -73,6 +75,8 @@ static void
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_cpu(query_cpu, mask) {
                 if (query_cpu != this_cpu)
@@ -89,6 +93,8 @@ static void x2apic_send_IPI_allbutself(int vector)
         unsigned long query_cpu;
         unsigned long flags;
 
+        x2apic_wrmsr_fence();
+
         local_irq_save(flags);
         for_each_online_cpu(query_cpu) {
                 if (query_cpu == this_cpu)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 1bd6da1f8fad..1248318436e8 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -118,17 +118,12 @@ static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 
 static void uv_send_IPI_one(int cpu, int vector)
 {
-        unsigned long val, apicid;
+        unsigned long apicid;
         int pnode;
 
         apicid = per_cpu(x86_cpu_to_apicid, cpu);
         pnode = uv_apicid_to_pnode(apicid);
-
-        val = (1UL << UVH_IPI_INT_SEND_SHFT) |
-              (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
-              (vector << UVH_IPI_INT_VECTOR_SHFT);
-
-        uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
+        uv_hub_send_ipi(pnode, apicid, vector);
 }
 
 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)