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-rw-r--r--arch/x86/kernel/apic/Makefile19
-rw-r--r--arch/x86/kernel/apic/apic.c2219
-rw-r--r--arch/x86/kernel/apic/apic_flat_64.c387
-rw-r--r--arch/x86/kernel/apic/bigsmp_32.c267
-rw-r--r--arch/x86/kernel/apic/es7000_32.c781
-rw-r--r--arch/x86/kernel/apic/io_apic.c4160
-rw-r--r--arch/x86/kernel/apic/ipi.c164
-rw-r--r--arch/x86/kernel/apic/nmi.c565
-rw-r--r--arch/x86/kernel/apic/numaq_32.c558
-rw-r--r--arch/x86/kernel/apic/probe_32.c285
-rw-r--r--arch/x86/kernel/apic/probe_64.c93
-rw-r--r--arch/x86/kernel/apic/summit_32.c576
-rw-r--r--arch/x86/kernel/apic/x2apic_cluster.c239
-rw-r--r--arch/x86/kernel/apic/x2apic_phys.c228
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c647
15 files changed, 11188 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
new file mode 100644
index 000000000000..da7b7b9f8bd8
--- /dev/null
+++ b/arch/x86/kernel/apic/Makefile
@@ -0,0 +1,19 @@
1#
2# Makefile for local APIC drivers and for the IO-APIC code
3#
4
5obj-$(CONFIG_X86_LOCAL_APIC) += apic.o probe_$(BITS).o ipi.o nmi.o
6obj-$(CONFIG_X86_IO_APIC) += io_apic.o
7obj-$(CONFIG_SMP) += ipi.o
8
9ifeq ($(CONFIG_X86_64),y)
10obj-y += apic_flat_64.o
11obj-$(CONFIG_X86_X2APIC) += x2apic_cluster.o
12obj-$(CONFIG_X86_X2APIC) += x2apic_phys.o
13obj-$(CONFIG_X86_UV) += x2apic_uv_x.o
14endif
15
16obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
17obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
18obj-$(CONFIG_X86_ES7000) += es7000_32.o
19obj-$(CONFIG_X86_SUMMIT) += summit_32.o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
new file mode 100644
index 000000000000..30909a258d0f
--- /dev/null
+++ b/arch/x86/kernel/apic/apic.c
@@ -0,0 +1,2219 @@
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/mc146818rtc.h>
19#include <linux/acpi_pmtmr.h>
20#include <linux/clockchips.h>
21#include <linux/interrupt.h>
22#include <linux/bootmem.h>
23#include <linux/ftrace.h>
24#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/sysdev.h>
27#include <linux/delay.h>
28#include <linux/timex.h>
29#include <linux/dmar.h>
30#include <linux/init.h>
31#include <linux/cpu.h>
32#include <linux/dmi.h>
33#include <linux/nmi.h>
34#include <linux/smp.h>
35#include <linux/mm.h>
36
37#include <asm/pgalloc.h>
38#include <asm/atomic.h>
39#include <asm/mpspec.h>
40#include <asm/i8253.h>
41#include <asm/i8259.h>
42#include <asm/proto.h>
43#include <asm/apic.h>
44#include <asm/desc.h>
45#include <asm/hpet.h>
46#include <asm/idle.h>
47#include <asm/mtrr.h>
48#include <asm/smp.h>
49#include <asm/mce.h>
50
51unsigned int num_processors;
52
53unsigned disabled_cpus __cpuinitdata;
54
55/* Processor that is doing the boot up */
56unsigned int boot_cpu_physical_apicid = -1U;
57
58/*
59 * The highest APIC ID seen during enumeration.
60 *
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
64 *
65 * If there's an APIC ID above 8, we use physical addressing.
66 */
67unsigned int max_physical_apicid;
68
69/*
70 * Bitmask of physically existing CPUs:
71 */
72physid_mask_t phys_cpu_present_map;
73
74/*
75 * Map cpu index to physical APIC ID
76 */
77DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
81
82#ifdef CONFIG_X86_32
83/*
84 * Knob to control our willingness to enable the local APIC.
85 *
86 * +1=force-enable
87 */
88static int force_enable_local_apic;
89/*
90 * APIC command line parameters
91 */
92static int __init parse_lapic(char *arg)
93{
94 force_enable_local_apic = 1;
95 return 0;
96}
97early_param("lapic", parse_lapic);
98/* Local APIC was disabled by the BIOS and enabled by the kernel */
99static int enabled_via_apicbase;
100
101#endif
102
103#ifdef CONFIG_X86_64
104static int apic_calibrate_pmtmr __initdata;
105static __init int setup_apicpmtimer(char *s)
106{
107 apic_calibrate_pmtmr = 1;
108 notsc_setup(NULL);
109 return 0;
110}
111__setup("apicpmtimer", setup_apicpmtimer);
112#endif
113
114#ifdef CONFIG_X86_X2APIC
115int x2apic;
116/* x2apic enabled before OS handover */
117static int x2apic_preenabled;
118static int disable_x2apic;
119static __init int setup_nox2apic(char *str)
120{
121 disable_x2apic = 1;
122 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
123 return 0;
124}
125early_param("nox2apic", setup_nox2apic);
126#endif
127
128unsigned long mp_lapic_addr;
129int disable_apic;
130/* Disable local APIC timer from the kernel commandline or via dmi quirk */
131static int disable_apic_timer __cpuinitdata;
132/* Local APIC timer works in C2 */
133int local_apic_timer_c2_ok;
134EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
135
136int first_system_vector = 0xfe;
137
138/*
139 * Debug level, exported for io_apic.c
140 */
141unsigned int apic_verbosity;
142
143int pic_mode;
144
145/* Have we found an MP table */
146int smp_found_config;
147
148static struct resource lapic_resource = {
149 .name = "Local APIC",
150 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
151};
152
153static unsigned int calibration_result;
154
155static int lapic_next_event(unsigned long delta,
156 struct clock_event_device *evt);
157static void lapic_timer_setup(enum clock_event_mode mode,
158 struct clock_event_device *evt);
159static void lapic_timer_broadcast(const struct cpumask *mask);
160static void apic_pm_activate(void);
161
162/*
163 * The local apic timer can be used for any function which is CPU local.
164 */
165static struct clock_event_device lapic_clockevent = {
166 .name = "lapic",
167 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
168 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
169 .shift = 32,
170 .set_mode = lapic_timer_setup,
171 .set_next_event = lapic_next_event,
172 .broadcast = lapic_timer_broadcast,
173 .rating = 100,
174 .irq = -1,
175};
176static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
177
178static unsigned long apic_phys;
179
180/*
181 * Get the LAPIC version
182 */
183static inline int lapic_get_version(void)
184{
185 return GET_APIC_VERSION(apic_read(APIC_LVR));
186}
187
188/*
189 * Check, if the APIC is integrated or a separate chip
190 */
191static inline int lapic_is_integrated(void)
192{
193#ifdef CONFIG_X86_64
194 return 1;
195#else
196 return APIC_INTEGRATED(lapic_get_version());
197#endif
198}
199
200/*
201 * Check, whether this is a modern or a first generation APIC
202 */
203static int modern_apic(void)
204{
205 /* AMD systems use old APIC versions, so check the CPU */
206 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
207 boot_cpu_data.x86 >= 0xf)
208 return 1;
209 return lapic_get_version() >= 0x14;
210}
211
212void native_apic_wait_icr_idle(void)
213{
214 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
215 cpu_relax();
216}
217
218u32 native_safe_apic_wait_icr_idle(void)
219{
220 u32 send_status;
221 int timeout;
222
223 timeout = 0;
224 do {
225 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
226 if (!send_status)
227 break;
228 udelay(100);
229 } while (timeout++ < 1000);
230
231 return send_status;
232}
233
234void native_apic_icr_write(u32 low, u32 id)
235{
236 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
237 apic_write(APIC_ICR, low);
238}
239
240u64 native_apic_icr_read(void)
241{
242 u32 icr1, icr2;
243
244 icr2 = apic_read(APIC_ICR2);
245 icr1 = apic_read(APIC_ICR);
246
247 return icr1 | ((u64)icr2 << 32);
248}
249
250/**
251 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
252 */
253void __cpuinit enable_NMI_through_LVT0(void)
254{
255 unsigned int v;
256
257 /* unmask and set to NMI */
258 v = APIC_DM_NMI;
259
260 /* Level triggered for 82489DX (32bit mode) */
261 if (!lapic_is_integrated())
262 v |= APIC_LVT_LEVEL_TRIGGER;
263
264 apic_write(APIC_LVT0, v);
265}
266
267#ifdef CONFIG_X86_32
268/**
269 * get_physical_broadcast - Get number of physical broadcast IDs
270 */
271int get_physical_broadcast(void)
272{
273 return modern_apic() ? 0xff : 0xf;
274}
275#endif
276
277/**
278 * lapic_get_maxlvt - get the maximum number of local vector table entries
279 */
280int lapic_get_maxlvt(void)
281{
282 unsigned int v;
283
284 v = apic_read(APIC_LVR);
285 /*
286 * - we always have APIC integrated on 64bit mode
287 * - 82489DXs do not report # of LVT entries
288 */
289 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
290}
291
292/*
293 * Local APIC timer
294 */
295
296/* Clock divisor */
297#define APIC_DIVISOR 16
298
299/*
300 * This function sets up the local APIC timer, with a timeout of
301 * 'clocks' APIC bus clock. During calibration we actually call
302 * this function twice on the boot CPU, once with a bogus timeout
303 * value, second time for real. The other (noncalibrating) CPUs
304 * call this function only once, with the real, calibrated value.
305 *
306 * We do reads before writes even if unnecessary, to get around the
307 * P5 APIC double write bug.
308 */
309static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
310{
311 unsigned int lvtt_value, tmp_value;
312
313 lvtt_value = LOCAL_TIMER_VECTOR;
314 if (!oneshot)
315 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
316 if (!lapic_is_integrated())
317 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
318
319 if (!irqen)
320 lvtt_value |= APIC_LVT_MASKED;
321
322 apic_write(APIC_LVTT, lvtt_value);
323
324 /*
325 * Divide PICLK by 16
326 */
327 tmp_value = apic_read(APIC_TDCR);
328 apic_write(APIC_TDCR,
329 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
330 APIC_TDR_DIV_16);
331
332 if (!oneshot)
333 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
334}
335
336/*
337 * Setup extended LVT, AMD specific (K8, family 10h)
338 *
339 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
340 * MCE interrupts are supported. Thus MCE offset must be set to 0.
341 *
342 * If mask=1, the LVT entry does not generate interrupts while mask=0
343 * enables the vector. See also the BKDGs.
344 */
345
346#define APIC_EILVT_LVTOFF_MCE 0
347#define APIC_EILVT_LVTOFF_IBS 1
348
349static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
350{
351 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
352 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
353
354 apic_write(reg, v);
355}
356
357u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
358{
359 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
360 return APIC_EILVT_LVTOFF_MCE;
361}
362
363u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
364{
365 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
366 return APIC_EILVT_LVTOFF_IBS;
367}
368EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
369
370/*
371 * Program the next event, relative to now
372 */
373static int lapic_next_event(unsigned long delta,
374 struct clock_event_device *evt)
375{
376 apic_write(APIC_TMICT, delta);
377 return 0;
378}
379
380/*
381 * Setup the lapic timer in periodic or oneshot mode
382 */
383static void lapic_timer_setup(enum clock_event_mode mode,
384 struct clock_event_device *evt)
385{
386 unsigned long flags;
387 unsigned int v;
388
389 /* Lapic used as dummy for broadcast ? */
390 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
391 return;
392
393 local_irq_save(flags);
394
395 switch (mode) {
396 case CLOCK_EVT_MODE_PERIODIC:
397 case CLOCK_EVT_MODE_ONESHOT:
398 __setup_APIC_LVTT(calibration_result,
399 mode != CLOCK_EVT_MODE_PERIODIC, 1);
400 break;
401 case CLOCK_EVT_MODE_UNUSED:
402 case CLOCK_EVT_MODE_SHUTDOWN:
403 v = apic_read(APIC_LVTT);
404 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
405 apic_write(APIC_LVTT, v);
406 apic_write(APIC_TMICT, 0xffffffff);
407 break;
408 case CLOCK_EVT_MODE_RESUME:
409 /* Nothing to do here */
410 break;
411 }
412
413 local_irq_restore(flags);
414}
415
416/*
417 * Local APIC timer broadcast function
418 */
419static void lapic_timer_broadcast(const struct cpumask *mask)
420{
421#ifdef CONFIG_SMP
422 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
423#endif
424}
425
426/*
427 * Setup the local APIC timer for this CPU. Copy the initilized values
428 * of the boot CPU and register the clock event in the framework.
429 */
430static void __cpuinit setup_APIC_timer(void)
431{
432 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
433
434 memcpy(levt, &lapic_clockevent, sizeof(*levt));
435 levt->cpumask = cpumask_of(smp_processor_id());
436
437 clockevents_register_device(levt);
438}
439
440/*
441 * In this functions we calibrate APIC bus clocks to the external timer.
442 *
443 * We want to do the calibration only once since we want to have local timer
444 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
445 * frequency.
446 *
447 * This was previously done by reading the PIT/HPET and waiting for a wrap
448 * around to find out, that a tick has elapsed. I have a box, where the PIT
449 * readout is broken, so it never gets out of the wait loop again. This was
450 * also reported by others.
451 *
452 * Monitoring the jiffies value is inaccurate and the clockevents
453 * infrastructure allows us to do a simple substitution of the interrupt
454 * handler.
455 *
456 * The calibration routine also uses the pm_timer when possible, as the PIT
457 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
458 * back to normal later in the boot process).
459 */
460
461#define LAPIC_CAL_LOOPS (HZ/10)
462
463static __initdata int lapic_cal_loops = -1;
464static __initdata long lapic_cal_t1, lapic_cal_t2;
465static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
466static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
467static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
468
469/*
470 * Temporary interrupt handler.
471 */
472static void __init lapic_cal_handler(struct clock_event_device *dev)
473{
474 unsigned long long tsc = 0;
475 long tapic = apic_read(APIC_TMCCT);
476 unsigned long pm = acpi_pm_read_early();
477
478 if (cpu_has_tsc)
479 rdtscll(tsc);
480
481 switch (lapic_cal_loops++) {
482 case 0:
483 lapic_cal_t1 = tapic;
484 lapic_cal_tsc1 = tsc;
485 lapic_cal_pm1 = pm;
486 lapic_cal_j1 = jiffies;
487 break;
488
489 case LAPIC_CAL_LOOPS:
490 lapic_cal_t2 = tapic;
491 lapic_cal_tsc2 = tsc;
492 if (pm < lapic_cal_pm1)
493 pm += ACPI_PM_OVRRUN;
494 lapic_cal_pm2 = pm;
495 lapic_cal_j2 = jiffies;
496 break;
497 }
498}
499
500static int __init
501calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
502{
503 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
504 const long pm_thresh = pm_100ms / 100;
505 unsigned long mult;
506 u64 res;
507
508#ifndef CONFIG_X86_PM_TIMER
509 return -1;
510#endif
511
512 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
513
514 /* Check, if the PM timer is available */
515 if (!deltapm)
516 return -1;
517
518 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
519
520 if (deltapm > (pm_100ms - pm_thresh) &&
521 deltapm < (pm_100ms + pm_thresh)) {
522 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
523 return 0;
524 }
525
526 res = (((u64)deltapm) * mult) >> 22;
527 do_div(res, 1000000);
528 pr_warning("APIC calibration not consistent "
529 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
530
531 /* Correct the lapic counter value */
532 res = (((u64)(*delta)) * pm_100ms);
533 do_div(res, deltapm);
534 pr_info("APIC delta adjusted to PM-Timer: "
535 "%lu (%ld)\n", (unsigned long)res, *delta);
536 *delta = (long)res;
537
538 /* Correct the tsc counter value */
539 if (cpu_has_tsc) {
540 res = (((u64)(*deltatsc)) * pm_100ms);
541 do_div(res, deltapm);
542 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
543 "PM-Timer: %lu (%ld) \n",
544 (unsigned long)res, *deltatsc);
545 *deltatsc = (long)res;
546 }
547
548 return 0;
549}
550
551static int __init calibrate_APIC_clock(void)
552{
553 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
554 void (*real_handler)(struct clock_event_device *dev);
555 unsigned long deltaj;
556 long delta, deltatsc;
557 int pm_referenced = 0;
558
559 local_irq_disable();
560
561 /* Replace the global interrupt handler */
562 real_handler = global_clock_event->event_handler;
563 global_clock_event->event_handler = lapic_cal_handler;
564
565 /*
566 * Setup the APIC counter to maximum. There is no way the lapic
567 * can underflow in the 100ms detection time frame
568 */
569 __setup_APIC_LVTT(0xffffffff, 0, 0);
570
571 /* Let the interrupts run */
572 local_irq_enable();
573
574 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
575 cpu_relax();
576
577 local_irq_disable();
578
579 /* Restore the real event handler */
580 global_clock_event->event_handler = real_handler;
581
582 /* Build delta t1-t2 as apic timer counts down */
583 delta = lapic_cal_t1 - lapic_cal_t2;
584 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
585
586 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
587
588 /* we trust the PM based calibration if possible */
589 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
590 &delta, &deltatsc);
591
592 /* Calculate the scaled math multiplication factor */
593 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
594 lapic_clockevent.shift);
595 lapic_clockevent.max_delta_ns =
596 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
597 lapic_clockevent.min_delta_ns =
598 clockevent_delta2ns(0xF, &lapic_clockevent);
599
600 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
601
602 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
603 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
604 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
605 calibration_result);
606
607 if (cpu_has_tsc) {
608 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
609 "%ld.%04ld MHz.\n",
610 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
611 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
612 }
613
614 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
615 "%u.%04u MHz.\n",
616 calibration_result / (1000000 / HZ),
617 calibration_result % (1000000 / HZ));
618
619 /*
620 * Do a sanity check on the APIC calibration result
621 */
622 if (calibration_result < (1000000 / HZ)) {
623 local_irq_enable();
624 pr_warning("APIC frequency too slow, disabling apic timer\n");
625 return -1;
626 }
627
628 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
629
630 /*
631 * PM timer calibration failed or not turned on
632 * so lets try APIC timer based calibration
633 */
634 if (!pm_referenced) {
635 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
636
637 /*
638 * Setup the apic timer manually
639 */
640 levt->event_handler = lapic_cal_handler;
641 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
642 lapic_cal_loops = -1;
643
644 /* Let the interrupts run */
645 local_irq_enable();
646
647 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
648 cpu_relax();
649
650 /* Stop the lapic timer */
651 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
652
653 /* Jiffies delta */
654 deltaj = lapic_cal_j2 - lapic_cal_j1;
655 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
656
657 /* Check, if the jiffies result is consistent */
658 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
659 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
660 else
661 levt->features |= CLOCK_EVT_FEAT_DUMMY;
662 } else
663 local_irq_enable();
664
665 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
666 pr_warning("APIC timer disabled due to verification failure\n");
667 return -1;
668 }
669
670 return 0;
671}
672
673/*
674 * Setup the boot APIC
675 *
676 * Calibrate and verify the result.
677 */
678void __init setup_boot_APIC_clock(void)
679{
680 /*
681 * The local apic timer can be disabled via the kernel
682 * commandline or from the CPU detection code. Register the lapic
683 * timer as a dummy clock event source on SMP systems, so the
684 * broadcast mechanism is used. On UP systems simply ignore it.
685 */
686 if (disable_apic_timer) {
687 pr_info("Disabling APIC timer\n");
688 /* No broadcast on UP ! */
689 if (num_possible_cpus() > 1) {
690 lapic_clockevent.mult = 1;
691 setup_APIC_timer();
692 }
693 return;
694 }
695
696 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
697 "calibrating APIC timer ...\n");
698
699 if (calibrate_APIC_clock()) {
700 /* No broadcast on UP ! */
701 if (num_possible_cpus() > 1)
702 setup_APIC_timer();
703 return;
704 }
705
706 /*
707 * If nmi_watchdog is set to IO_APIC, we need the
708 * PIT/HPET going. Otherwise register lapic as a dummy
709 * device.
710 */
711 if (nmi_watchdog != NMI_IO_APIC)
712 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
713 else
714 pr_warning("APIC timer registered as dummy,"
715 " due to nmi_watchdog=%d!\n", nmi_watchdog);
716
717 /* Setup the lapic or request the broadcast */
718 setup_APIC_timer();
719}
720
721void __cpuinit setup_secondary_APIC_clock(void)
722{
723 setup_APIC_timer();
724}
725
726/*
727 * The guts of the apic timer interrupt
728 */
729static void local_apic_timer_interrupt(void)
730{
731 int cpu = smp_processor_id();
732 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
733
734 /*
735 * Normally we should not be here till LAPIC has been initialized but
736 * in some cases like kdump, its possible that there is a pending LAPIC
737 * timer interrupt from previous kernel's context and is delivered in
738 * new kernel the moment interrupts are enabled.
739 *
740 * Interrupts are enabled early and LAPIC is setup much later, hence
741 * its possible that when we get here evt->event_handler is NULL.
742 * Check for event_handler being NULL and discard the interrupt as
743 * spurious.
744 */
745 if (!evt->event_handler) {
746 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
747 /* Switch it off */
748 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
749 return;
750 }
751
752 /*
753 * the NMI deadlock-detector uses this.
754 */
755 inc_irq_stat(apic_timer_irqs);
756
757 evt->event_handler(evt);
758}
759
760/*
761 * Local APIC timer interrupt. This is the most natural way for doing
762 * local interrupts, but local timer interrupts can be emulated by
763 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
764 *
765 * [ if a single-CPU system runs an SMP kernel then we call the local
766 * interrupt as well. Thus we cannot inline the local irq ... ]
767 */
768void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
769{
770 struct pt_regs *old_regs = set_irq_regs(regs);
771
772 /*
773 * NOTE! We'd better ACK the irq immediately,
774 * because timer handling can be slow.
775 */
776 ack_APIC_irq();
777 /*
778 * update_process_times() expects us to have done irq_enter().
779 * Besides, if we don't timer interrupts ignore the global
780 * interrupt lock, which is the WrongThing (tm) to do.
781 */
782 exit_idle();
783 irq_enter();
784 local_apic_timer_interrupt();
785 irq_exit();
786
787 set_irq_regs(old_regs);
788}
789
790int setup_profiling_timer(unsigned int multiplier)
791{
792 return -EINVAL;
793}
794
795/*
796 * Local APIC start and shutdown
797 */
798
799/**
800 * clear_local_APIC - shutdown the local APIC
801 *
802 * This is called, when a CPU is disabled and before rebooting, so the state of
803 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
804 * leftovers during boot.
805 */
806void clear_local_APIC(void)
807{
808 int maxlvt;
809 u32 v;
810
811 /* APIC hasn't been mapped yet */
812 if (!apic_phys)
813 return;
814
815 maxlvt = lapic_get_maxlvt();
816 /*
817 * Masking an LVT entry can trigger a local APIC error
818 * if the vector is zero. Mask LVTERR first to prevent this.
819 */
820 if (maxlvt >= 3) {
821 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
822 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
823 }
824 /*
825 * Careful: we have to set masks only first to deassert
826 * any level-triggered sources.
827 */
828 v = apic_read(APIC_LVTT);
829 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
830 v = apic_read(APIC_LVT0);
831 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
832 v = apic_read(APIC_LVT1);
833 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
834 if (maxlvt >= 4) {
835 v = apic_read(APIC_LVTPC);
836 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
837 }
838
839 /* lets not touch this if we didn't frob it */
840#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
841 if (maxlvt >= 5) {
842 v = apic_read(APIC_LVTTHMR);
843 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
844 }
845#endif
846#ifdef CONFIG_X86_MCE_INTEL
847 if (maxlvt >= 6) {
848 v = apic_read(APIC_LVTCMCI);
849 if (!(v & APIC_LVT_MASKED))
850 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
851 }
852#endif
853
854 /*
855 * Clean APIC state for other OSs:
856 */
857 apic_write(APIC_LVTT, APIC_LVT_MASKED);
858 apic_write(APIC_LVT0, APIC_LVT_MASKED);
859 apic_write(APIC_LVT1, APIC_LVT_MASKED);
860 if (maxlvt >= 3)
861 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
862 if (maxlvt >= 4)
863 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
864
865 /* Integrated APIC (!82489DX) ? */
866 if (lapic_is_integrated()) {
867 if (maxlvt > 3)
868 /* Clear ESR due to Pentium errata 3AP and 11AP */
869 apic_write(APIC_ESR, 0);
870 apic_read(APIC_ESR);
871 }
872}
873
874/**
875 * disable_local_APIC - clear and disable the local APIC
876 */
877void disable_local_APIC(void)
878{
879 unsigned int value;
880
881 /* APIC hasn't been mapped yet */
882 if (!apic_phys)
883 return;
884
885 clear_local_APIC();
886
887 /*
888 * Disable APIC (implies clearing of registers
889 * for 82489DX!).
890 */
891 value = apic_read(APIC_SPIV);
892 value &= ~APIC_SPIV_APIC_ENABLED;
893 apic_write(APIC_SPIV, value);
894
895#ifdef CONFIG_X86_32
896 /*
897 * When LAPIC was disabled by the BIOS and enabled by the kernel,
898 * restore the disabled state.
899 */
900 if (enabled_via_apicbase) {
901 unsigned int l, h;
902
903 rdmsr(MSR_IA32_APICBASE, l, h);
904 l &= ~MSR_IA32_APICBASE_ENABLE;
905 wrmsr(MSR_IA32_APICBASE, l, h);
906 }
907#endif
908}
909
910/*
911 * If Linux enabled the LAPIC against the BIOS default disable it down before
912 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
913 * not power-off. Additionally clear all LVT entries before disable_local_APIC
914 * for the case where Linux didn't enable the LAPIC.
915 */
916void lapic_shutdown(void)
917{
918 unsigned long flags;
919
920 if (!cpu_has_apic)
921 return;
922
923 local_irq_save(flags);
924
925#ifdef CONFIG_X86_32
926 if (!enabled_via_apicbase)
927 clear_local_APIC();
928 else
929#endif
930 disable_local_APIC();
931
932
933 local_irq_restore(flags);
934}
935
936/*
937 * This is to verify that we're looking at a real local APIC.
938 * Check these against your board if the CPUs aren't getting
939 * started for no apparent reason.
940 */
941int __init verify_local_APIC(void)
942{
943 unsigned int reg0, reg1;
944
945 /*
946 * The version register is read-only in a real APIC.
947 */
948 reg0 = apic_read(APIC_LVR);
949 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
950 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
951 reg1 = apic_read(APIC_LVR);
952 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
953
954 /*
955 * The two version reads above should print the same
956 * numbers. If the second one is different, then we
957 * poke at a non-APIC.
958 */
959 if (reg1 != reg0)
960 return 0;
961
962 /*
963 * Check if the version looks reasonably.
964 */
965 reg1 = GET_APIC_VERSION(reg0);
966 if (reg1 == 0x00 || reg1 == 0xff)
967 return 0;
968 reg1 = lapic_get_maxlvt();
969 if (reg1 < 0x02 || reg1 == 0xff)
970 return 0;
971
972 /*
973 * The ID register is read/write in a real APIC.
974 */
975 reg0 = apic_read(APIC_ID);
976 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
977 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
978 reg1 = apic_read(APIC_ID);
979 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
980 apic_write(APIC_ID, reg0);
981 if (reg1 != (reg0 ^ apic->apic_id_mask))
982 return 0;
983
984 /*
985 * The next two are just to see if we have sane values.
986 * They're only really relevant if we're in Virtual Wire
987 * compatibility mode, but most boxes are anymore.
988 */
989 reg0 = apic_read(APIC_LVT0);
990 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
991 reg1 = apic_read(APIC_LVT1);
992 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
993
994 return 1;
995}
996
997/**
998 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
999 */
1000void __init sync_Arb_IDs(void)
1001{
1002 /*
1003 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1004 * needed on AMD.
1005 */
1006 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1007 return;
1008
1009 /*
1010 * Wait for idle.
1011 */
1012 apic_wait_icr_idle();
1013
1014 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1015 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1016 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1017}
1018
1019/*
1020 * An initial setup of the virtual wire mode.
1021 */
1022void __init init_bsp_APIC(void)
1023{
1024 unsigned int value;
1025
1026 /*
1027 * Don't do the setup now if we have a SMP BIOS as the
1028 * through-I/O-APIC virtual wire mode might be active.
1029 */
1030 if (smp_found_config || !cpu_has_apic)
1031 return;
1032
1033 /*
1034 * Do not trust the local APIC being empty at bootup.
1035 */
1036 clear_local_APIC();
1037
1038 /*
1039 * Enable APIC.
1040 */
1041 value = apic_read(APIC_SPIV);
1042 value &= ~APIC_VECTOR_MASK;
1043 value |= APIC_SPIV_APIC_ENABLED;
1044
1045#ifdef CONFIG_X86_32
1046 /* This bit is reserved on P4/Xeon and should be cleared */
1047 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1048 (boot_cpu_data.x86 == 15))
1049 value &= ~APIC_SPIV_FOCUS_DISABLED;
1050 else
1051#endif
1052 value |= APIC_SPIV_FOCUS_DISABLED;
1053 value |= SPURIOUS_APIC_VECTOR;
1054 apic_write(APIC_SPIV, value);
1055
1056 /*
1057 * Set up the virtual wire mode.
1058 */
1059 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1060 value = APIC_DM_NMI;
1061 if (!lapic_is_integrated()) /* 82489DX */
1062 value |= APIC_LVT_LEVEL_TRIGGER;
1063 apic_write(APIC_LVT1, value);
1064}
1065
1066static void __cpuinit lapic_setup_esr(void)
1067{
1068 unsigned int oldvalue, value, maxlvt;
1069
1070 if (!lapic_is_integrated()) {
1071 pr_info("No ESR for 82489DX.\n");
1072 return;
1073 }
1074
1075 if (apic->disable_esr) {
1076 /*
1077 * Something untraceable is creating bad interrupts on
1078 * secondary quads ... for the moment, just leave the
1079 * ESR disabled - we can't do anything useful with the
1080 * errors anyway - mbligh
1081 */
1082 pr_info("Leaving ESR disabled.\n");
1083 return;
1084 }
1085
1086 maxlvt = lapic_get_maxlvt();
1087 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1088 apic_write(APIC_ESR, 0);
1089 oldvalue = apic_read(APIC_ESR);
1090
1091 /* enables sending errors */
1092 value = ERROR_APIC_VECTOR;
1093 apic_write(APIC_LVTERR, value);
1094
1095 /*
1096 * spec says clear errors after enabling vector.
1097 */
1098 if (maxlvt > 3)
1099 apic_write(APIC_ESR, 0);
1100 value = apic_read(APIC_ESR);
1101 if (value != oldvalue)
1102 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1103 "vector: 0x%08x after: 0x%08x\n",
1104 oldvalue, value);
1105}
1106
1107
1108/**
1109 * setup_local_APIC - setup the local APIC
1110 */
1111void __cpuinit setup_local_APIC(void)
1112{
1113 unsigned int value;
1114 int i, j;
1115
1116 if (disable_apic) {
1117 arch_disable_smp_support();
1118 return;
1119 }
1120
1121#ifdef CONFIG_X86_32
1122 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1123 if (lapic_is_integrated() && apic->disable_esr) {
1124 apic_write(APIC_ESR, 0);
1125 apic_write(APIC_ESR, 0);
1126 apic_write(APIC_ESR, 0);
1127 apic_write(APIC_ESR, 0);
1128 }
1129#endif
1130
1131 preempt_disable();
1132
1133 /*
1134 * Double-check whether this APIC is really registered.
1135 * This is meaningless in clustered apic mode, so we skip it.
1136 */
1137 if (!apic->apic_id_registered())
1138 BUG();
1139
1140 /*
1141 * Intel recommends to set DFR, LDR and TPR before enabling
1142 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1143 * document number 292116). So here it goes...
1144 */
1145 apic->init_apic_ldr();
1146
1147 /*
1148 * Set Task Priority to 'accept all'. We never change this
1149 * later on.
1150 */
1151 value = apic_read(APIC_TASKPRI);
1152 value &= ~APIC_TPRI_MASK;
1153 apic_write(APIC_TASKPRI, value);
1154
1155 /*
1156 * After a crash, we no longer service the interrupts and a pending
1157 * interrupt from previous kernel might still have ISR bit set.
1158 *
1159 * Most probably by now CPU has serviced that pending interrupt and
1160 * it might not have done the ack_APIC_irq() because it thought,
1161 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1162 * does not clear the ISR bit and cpu thinks it has already serivced
1163 * the interrupt. Hence a vector might get locked. It was noticed
1164 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1165 */
1166 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1167 value = apic_read(APIC_ISR + i*0x10);
1168 for (j = 31; j >= 0; j--) {
1169 if (value & (1<<j))
1170 ack_APIC_irq();
1171 }
1172 }
1173
1174 /*
1175 * Now that we are all set up, enable the APIC
1176 */
1177 value = apic_read(APIC_SPIV);
1178 value &= ~APIC_VECTOR_MASK;
1179 /*
1180 * Enable APIC
1181 */
1182 value |= APIC_SPIV_APIC_ENABLED;
1183
1184#ifdef CONFIG_X86_32
1185 /*
1186 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1187 * certain networking cards. If high frequency interrupts are
1188 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1189 * entry is masked/unmasked at a high rate as well then sooner or
1190 * later IOAPIC line gets 'stuck', no more interrupts are received
1191 * from the device. If focus CPU is disabled then the hang goes
1192 * away, oh well :-(
1193 *
1194 * [ This bug can be reproduced easily with a level-triggered
1195 * PCI Ne2000 networking cards and PII/PIII processors, dual
1196 * BX chipset. ]
1197 */
1198 /*
1199 * Actually disabling the focus CPU check just makes the hang less
1200 * frequent as it makes the interrupt distributon model be more
1201 * like LRU than MRU (the short-term load is more even across CPUs).
1202 * See also the comment in end_level_ioapic_irq(). --macro
1203 */
1204
1205 /*
1206 * - enable focus processor (bit==0)
1207 * - 64bit mode always use processor focus
1208 * so no need to set it
1209 */
1210 value &= ~APIC_SPIV_FOCUS_DISABLED;
1211#endif
1212
1213 /*
1214 * Set spurious IRQ vector
1215 */
1216 value |= SPURIOUS_APIC_VECTOR;
1217 apic_write(APIC_SPIV, value);
1218
1219 /*
1220 * Set up LVT0, LVT1:
1221 *
1222 * set up through-local-APIC on the BP's LINT0. This is not
1223 * strictly necessary in pure symmetric-IO mode, but sometimes
1224 * we delegate interrupts to the 8259A.
1225 */
1226 /*
1227 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1228 */
1229 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1230 if (!smp_processor_id() && (pic_mode || !value)) {
1231 value = APIC_DM_EXTINT;
1232 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1233 smp_processor_id());
1234 } else {
1235 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1236 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1237 smp_processor_id());
1238 }
1239 apic_write(APIC_LVT0, value);
1240
1241 /*
1242 * only the BP should see the LINT1 NMI signal, obviously.
1243 */
1244 if (!smp_processor_id())
1245 value = APIC_DM_NMI;
1246 else
1247 value = APIC_DM_NMI | APIC_LVT_MASKED;
1248 if (!lapic_is_integrated()) /* 82489DX */
1249 value |= APIC_LVT_LEVEL_TRIGGER;
1250 apic_write(APIC_LVT1, value);
1251
1252 preempt_enable();
1253
1254#ifdef CONFIG_X86_MCE_INTEL
1255 /* Recheck CMCI information after local APIC is up on CPU #0 */
1256 if (smp_processor_id() == 0)
1257 cmci_recheck();
1258#endif
1259}
1260
1261void __cpuinit end_local_APIC_setup(void)
1262{
1263 lapic_setup_esr();
1264
1265#ifdef CONFIG_X86_32
1266 {
1267 unsigned int value;
1268 /* Disable the local apic timer */
1269 value = apic_read(APIC_LVTT);
1270 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1271 apic_write(APIC_LVTT, value);
1272 }
1273#endif
1274
1275 setup_apic_nmi_watchdog(NULL);
1276 apic_pm_activate();
1277}
1278
1279#ifdef CONFIG_X86_X2APIC
1280void check_x2apic(void)
1281{
1282 if (x2apic_enabled()) {
1283 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1284 x2apic_preenabled = x2apic = 1;
1285 }
1286}
1287
1288void enable_x2apic(void)
1289{
1290 int msr, msr2;
1291
1292 if (!x2apic)
1293 return;
1294
1295 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1296 if (!(msr & X2APIC_ENABLE)) {
1297 pr_info("Enabling x2apic\n");
1298 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1299 }
1300}
1301
1302void __init enable_IR_x2apic(void)
1303{
1304#ifdef CONFIG_INTR_REMAP
1305 int ret;
1306 unsigned long flags;
1307
1308 if (!cpu_has_x2apic)
1309 return;
1310
1311 if (!x2apic_preenabled && disable_x2apic) {
1312 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1313 "because of nox2apic\n");
1314 return;
1315 }
1316
1317 if (x2apic_preenabled && disable_x2apic)
1318 panic("Bios already enabled x2apic, can't enforce nox2apic");
1319
1320 if (!x2apic_preenabled && skip_ioapic_setup) {
1321 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1322 "because of skipping io-apic setup\n");
1323 return;
1324 }
1325
1326 ret = dmar_table_init();
1327 if (ret) {
1328 pr_info("dmar_table_init() failed with %d:\n", ret);
1329
1330 if (x2apic_preenabled)
1331 panic("x2apic enabled by bios. But IR enabling failed");
1332 else
1333 pr_info("Not enabling x2apic,Intr-remapping\n");
1334 return;
1335 }
1336
1337 local_irq_save(flags);
1338 mask_8259A();
1339
1340 ret = save_mask_IO_APIC_setup();
1341 if (ret) {
1342 pr_info("Saving IO-APIC state failed: %d\n", ret);
1343 goto end;
1344 }
1345
1346 ret = enable_intr_remapping(1);
1347
1348 if (ret && x2apic_preenabled) {
1349 local_irq_restore(flags);
1350 panic("x2apic enabled by bios. But IR enabling failed");
1351 }
1352
1353 if (ret)
1354 goto end_restore;
1355
1356 if (!x2apic) {
1357 x2apic = 1;
1358 enable_x2apic();
1359 }
1360
1361end_restore:
1362 if (ret)
1363 /*
1364 * IR enabling failed
1365 */
1366 restore_IO_APIC_setup();
1367 else
1368 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1369
1370end:
1371 unmask_8259A();
1372 local_irq_restore(flags);
1373
1374 if (!ret) {
1375 if (!x2apic_preenabled)
1376 pr_info("Enabled x2apic and interrupt-remapping\n");
1377 else
1378 pr_info("Enabled Interrupt-remapping\n");
1379 } else
1380 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1381#else
1382 if (!cpu_has_x2apic)
1383 return;
1384
1385 if (x2apic_preenabled)
1386 panic("x2apic enabled prior OS handover,"
1387 " enable CONFIG_INTR_REMAP");
1388
1389 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1390 " and x2apic\n");
1391#endif
1392
1393 return;
1394}
1395#endif /* CONFIG_X86_X2APIC */
1396
1397#ifdef CONFIG_X86_64
1398/*
1399 * Detect and enable local APICs on non-SMP boards.
1400 * Original code written by Keir Fraser.
1401 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1402 * not correctly set up (usually the APIC timer won't work etc.)
1403 */
1404static int __init detect_init_APIC(void)
1405{
1406 if (!cpu_has_apic) {
1407 pr_info("No local APIC present\n");
1408 return -1;
1409 }
1410
1411 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1412 boot_cpu_physical_apicid = 0;
1413 return 0;
1414}
1415#else
1416/*
1417 * Detect and initialize APIC
1418 */
1419static int __init detect_init_APIC(void)
1420{
1421 u32 h, l, features;
1422
1423 /* Disabled by kernel option? */
1424 if (disable_apic)
1425 return -1;
1426
1427 switch (boot_cpu_data.x86_vendor) {
1428 case X86_VENDOR_AMD:
1429 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1430 (boot_cpu_data.x86 >= 15))
1431 break;
1432 goto no_apic;
1433 case X86_VENDOR_INTEL:
1434 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1435 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1436 break;
1437 goto no_apic;
1438 default:
1439 goto no_apic;
1440 }
1441
1442 if (!cpu_has_apic) {
1443 /*
1444 * Over-ride BIOS and try to enable the local APIC only if
1445 * "lapic" specified.
1446 */
1447 if (!force_enable_local_apic) {
1448 pr_info("Local APIC disabled by BIOS -- "
1449 "you can enable it with \"lapic\"\n");
1450 return -1;
1451 }
1452 /*
1453 * Some BIOSes disable the local APIC in the APIC_BASE
1454 * MSR. This can only be done in software for Intel P6 or later
1455 * and AMD K7 (Model > 1) or later.
1456 */
1457 rdmsr(MSR_IA32_APICBASE, l, h);
1458 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1459 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1460 l &= ~MSR_IA32_APICBASE_BASE;
1461 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1462 wrmsr(MSR_IA32_APICBASE, l, h);
1463 enabled_via_apicbase = 1;
1464 }
1465 }
1466 /*
1467 * The APIC feature bit should now be enabled
1468 * in `cpuid'
1469 */
1470 features = cpuid_edx(1);
1471 if (!(features & (1 << X86_FEATURE_APIC))) {
1472 pr_warning("Could not enable APIC!\n");
1473 return -1;
1474 }
1475 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1476 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1477
1478 /* The BIOS may have set up the APIC at some other address */
1479 rdmsr(MSR_IA32_APICBASE, l, h);
1480 if (l & MSR_IA32_APICBASE_ENABLE)
1481 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1482
1483 pr_info("Found and enabled local APIC!\n");
1484
1485 apic_pm_activate();
1486
1487 return 0;
1488
1489no_apic:
1490 pr_info("No local APIC present or hardware disabled\n");
1491 return -1;
1492}
1493#endif
1494
1495#ifdef CONFIG_X86_64
1496void __init early_init_lapic_mapping(void)
1497{
1498 unsigned long phys_addr;
1499
1500 /*
1501 * If no local APIC can be found then go out
1502 * : it means there is no mpatable and MADT
1503 */
1504 if (!smp_found_config)
1505 return;
1506
1507 phys_addr = mp_lapic_addr;
1508
1509 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1510 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1511 APIC_BASE, phys_addr);
1512
1513 /*
1514 * Fetch the APIC ID of the BSP in case we have a
1515 * default configuration (or the MP table is broken).
1516 */
1517 boot_cpu_physical_apicid = read_apic_id();
1518}
1519#endif
1520
1521/**
1522 * init_apic_mappings - initialize APIC mappings
1523 */
1524void __init init_apic_mappings(void)
1525{
1526#ifdef CONFIG_X86_X2APIC
1527 if (x2apic) {
1528 boot_cpu_physical_apicid = read_apic_id();
1529 return;
1530 }
1531#endif
1532
1533 /*
1534 * If no local APIC can be found then set up a fake all
1535 * zeroes page to simulate the local APIC and another
1536 * one for the IO-APIC.
1537 */
1538 if (!smp_found_config && detect_init_APIC()) {
1539 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1540 apic_phys = __pa(apic_phys);
1541 } else
1542 apic_phys = mp_lapic_addr;
1543
1544 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1545 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1546 APIC_BASE, apic_phys);
1547
1548 /*
1549 * Fetch the APIC ID of the BSP in case we have a
1550 * default configuration (or the MP table is broken).
1551 */
1552 if (boot_cpu_physical_apicid == -1U)
1553 boot_cpu_physical_apicid = read_apic_id();
1554}
1555
1556/*
1557 * This initializes the IO-APIC and APIC hardware if this is
1558 * a UP kernel.
1559 */
1560int apic_version[MAX_APICS];
1561
1562int __init APIC_init_uniprocessor(void)
1563{
1564 if (disable_apic) {
1565 pr_info("Apic disabled\n");
1566 return -1;
1567 }
1568#ifdef CONFIG_X86_64
1569 if (!cpu_has_apic) {
1570 disable_apic = 1;
1571 pr_info("Apic disabled by BIOS\n");
1572 return -1;
1573 }
1574#else
1575 if (!smp_found_config && !cpu_has_apic)
1576 return -1;
1577
1578 /*
1579 * Complain if the BIOS pretends there is one.
1580 */
1581 if (!cpu_has_apic &&
1582 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1583 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1584 boot_cpu_physical_apicid);
1585 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1586 return -1;
1587 }
1588#endif
1589
1590 enable_IR_x2apic();
1591#ifdef CONFIG_X86_64
1592 default_setup_apic_routing();
1593#endif
1594
1595 verify_local_APIC();
1596 connect_bsp_APIC();
1597
1598#ifdef CONFIG_X86_64
1599 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1600#else
1601 /*
1602 * Hack: In case of kdump, after a crash, kernel might be booting
1603 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1604 * might be zero if read from MP tables. Get it from LAPIC.
1605 */
1606# ifdef CONFIG_CRASH_DUMP
1607 boot_cpu_physical_apicid = read_apic_id();
1608# endif
1609#endif
1610 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1611 setup_local_APIC();
1612
1613#ifdef CONFIG_X86_IO_APIC
1614 /*
1615 * Now enable IO-APICs, actually call clear_IO_APIC
1616 * We need clear_IO_APIC before enabling error vector
1617 */
1618 if (!skip_ioapic_setup && nr_ioapics)
1619 enable_IO_APIC();
1620#endif
1621
1622 end_local_APIC_setup();
1623
1624#ifdef CONFIG_X86_IO_APIC
1625 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1626 setup_IO_APIC();
1627 else {
1628 nr_ioapics = 0;
1629 localise_nmi_watchdog();
1630 }
1631#else
1632 localise_nmi_watchdog();
1633#endif
1634
1635 setup_boot_clock();
1636#ifdef CONFIG_X86_64
1637 check_nmi_watchdog();
1638#endif
1639
1640 return 0;
1641}
1642
1643/*
1644 * Local APIC interrupts
1645 */
1646
1647/*
1648 * This interrupt should _never_ happen with our APIC/SMP architecture
1649 */
1650void smp_spurious_interrupt(struct pt_regs *regs)
1651{
1652 u32 v;
1653
1654 exit_idle();
1655 irq_enter();
1656 /*
1657 * Check if this really is a spurious interrupt and ACK it
1658 * if it is a vectored one. Just in case...
1659 * Spurious interrupts should not be ACKed.
1660 */
1661 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1662 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1663 ack_APIC_irq();
1664
1665 inc_irq_stat(irq_spurious_count);
1666
1667 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1668 pr_info("spurious APIC interrupt on CPU#%d, "
1669 "should never happen.\n", smp_processor_id());
1670 irq_exit();
1671}
1672
1673/*
1674 * This interrupt should never happen with our APIC/SMP architecture
1675 */
1676void smp_error_interrupt(struct pt_regs *regs)
1677{
1678 u32 v, v1;
1679
1680 exit_idle();
1681 irq_enter();
1682 /* First tickle the hardware, only then report what went on. -- REW */
1683 v = apic_read(APIC_ESR);
1684 apic_write(APIC_ESR, 0);
1685 v1 = apic_read(APIC_ESR);
1686 ack_APIC_irq();
1687 atomic_inc(&irq_err_count);
1688
1689 /*
1690 * Here is what the APIC error bits mean:
1691 * 0: Send CS error
1692 * 1: Receive CS error
1693 * 2: Send accept error
1694 * 3: Receive accept error
1695 * 4: Reserved
1696 * 5: Send illegal vector
1697 * 6: Received illegal vector
1698 * 7: Illegal register address
1699 */
1700 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1701 smp_processor_id(), v , v1);
1702 irq_exit();
1703}
1704
1705/**
1706 * connect_bsp_APIC - attach the APIC to the interrupt system
1707 */
1708void __init connect_bsp_APIC(void)
1709{
1710#ifdef CONFIG_X86_32
1711 if (pic_mode) {
1712 /*
1713 * Do not trust the local APIC being empty at bootup.
1714 */
1715 clear_local_APIC();
1716 /*
1717 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1718 * local APIC to INT and NMI lines.
1719 */
1720 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1721 "enabling APIC mode.\n");
1722 outb(0x70, 0x22);
1723 outb(0x01, 0x23);
1724 }
1725#endif
1726 if (apic->enable_apic_mode)
1727 apic->enable_apic_mode();
1728}
1729
1730/**
1731 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1732 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1733 *
1734 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1735 * APIC is disabled.
1736 */
1737void disconnect_bsp_APIC(int virt_wire_setup)
1738{
1739 unsigned int value;
1740
1741#ifdef CONFIG_X86_32
1742 if (pic_mode) {
1743 /*
1744 * Put the board back into PIC mode (has an effect only on
1745 * certain older boards). Note that APIC interrupts, including
1746 * IPIs, won't work beyond this point! The only exception are
1747 * INIT IPIs.
1748 */
1749 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1750 "entering PIC mode.\n");
1751 outb(0x70, 0x22);
1752 outb(0x00, 0x23);
1753 return;
1754 }
1755#endif
1756
1757 /* Go back to Virtual Wire compatibility mode */
1758
1759 /* For the spurious interrupt use vector F, and enable it */
1760 value = apic_read(APIC_SPIV);
1761 value &= ~APIC_VECTOR_MASK;
1762 value |= APIC_SPIV_APIC_ENABLED;
1763 value |= 0xf;
1764 apic_write(APIC_SPIV, value);
1765
1766 if (!virt_wire_setup) {
1767 /*
1768 * For LVT0 make it edge triggered, active high,
1769 * external and enabled
1770 */
1771 value = apic_read(APIC_LVT0);
1772 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1773 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1774 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1775 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1776 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1777 apic_write(APIC_LVT0, value);
1778 } else {
1779 /* Disable LVT0 */
1780 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1781 }
1782
1783 /*
1784 * For LVT1 make it edge triggered, active high,
1785 * nmi and enabled
1786 */
1787 value = apic_read(APIC_LVT1);
1788 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1789 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1790 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1791 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1792 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1793 apic_write(APIC_LVT1, value);
1794}
1795
1796void __cpuinit generic_processor_info(int apicid, int version)
1797{
1798 int cpu;
1799
1800 /*
1801 * Validate version
1802 */
1803 if (version == 0x0) {
1804 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1805 "fixing up to 0x10. (tell your hw vendor)\n",
1806 version);
1807 version = 0x10;
1808 }
1809 apic_version[apicid] = version;
1810
1811 if (num_processors >= nr_cpu_ids) {
1812 int max = nr_cpu_ids;
1813 int thiscpu = max + disabled_cpus;
1814
1815 pr_warning(
1816 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1817 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1818
1819 disabled_cpus++;
1820 return;
1821 }
1822
1823 num_processors++;
1824 cpu = cpumask_next_zero(-1, cpu_present_mask);
1825
1826 if (version != apic_version[boot_cpu_physical_apicid])
1827 WARN_ONCE(1,
1828 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1829 apic_version[boot_cpu_physical_apicid], cpu, version);
1830
1831 physid_set(apicid, phys_cpu_present_map);
1832 if (apicid == boot_cpu_physical_apicid) {
1833 /*
1834 * x86_bios_cpu_apicid is required to have processors listed
1835 * in same order as logical cpu numbers. Hence the first
1836 * entry is BSP, and so on.
1837 */
1838 cpu = 0;
1839 }
1840 if (apicid > max_physical_apicid)
1841 max_physical_apicid = apicid;
1842
1843#ifdef CONFIG_X86_32
1844 /*
1845 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1846 * but we need to work other dependencies like SMP_SUSPEND etc
1847 * before this can be done without some confusion.
1848 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1849 * - Ashok Raj <ashok.raj@intel.com>
1850 */
1851 if (max_physical_apicid >= 8) {
1852 switch (boot_cpu_data.x86_vendor) {
1853 case X86_VENDOR_INTEL:
1854 if (!APIC_XAPIC(version)) {
1855 def_to_bigsmp = 0;
1856 break;
1857 }
1858 /* If P4 and above fall through */
1859 case X86_VENDOR_AMD:
1860 def_to_bigsmp = 1;
1861 }
1862 }
1863#endif
1864
1865#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1866 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1867 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1868#endif
1869
1870 set_cpu_possible(cpu, true);
1871 set_cpu_present(cpu, true);
1872}
1873
1874int hard_smp_processor_id(void)
1875{
1876 return read_apic_id();
1877}
1878
1879void default_init_apic_ldr(void)
1880{
1881 unsigned long val;
1882
1883 apic_write(APIC_DFR, APIC_DFR_VALUE);
1884 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1885 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1886 apic_write(APIC_LDR, val);
1887}
1888
1889#ifdef CONFIG_X86_32
1890int default_apicid_to_node(int logical_apicid)
1891{
1892#ifdef CONFIG_SMP
1893 return apicid_2_node[hard_smp_processor_id()];
1894#else
1895 return 0;
1896#endif
1897}
1898#endif
1899
1900/*
1901 * Power management
1902 */
1903#ifdef CONFIG_PM
1904
1905static struct {
1906 /*
1907 * 'active' is true if the local APIC was enabled by us and
1908 * not the BIOS; this signifies that we are also responsible
1909 * for disabling it before entering apm/acpi suspend
1910 */
1911 int active;
1912 /* r/w apic fields */
1913 unsigned int apic_id;
1914 unsigned int apic_taskpri;
1915 unsigned int apic_ldr;
1916 unsigned int apic_dfr;
1917 unsigned int apic_spiv;
1918 unsigned int apic_lvtt;
1919 unsigned int apic_lvtpc;
1920 unsigned int apic_lvt0;
1921 unsigned int apic_lvt1;
1922 unsigned int apic_lvterr;
1923 unsigned int apic_tmict;
1924 unsigned int apic_tdcr;
1925 unsigned int apic_thmr;
1926} apic_pm_state;
1927
1928static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1929{
1930 unsigned long flags;
1931 int maxlvt;
1932
1933 if (!apic_pm_state.active)
1934 return 0;
1935
1936 maxlvt = lapic_get_maxlvt();
1937
1938 apic_pm_state.apic_id = apic_read(APIC_ID);
1939 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1940 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1941 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1942 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1943 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1944 if (maxlvt >= 4)
1945 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1946 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1947 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1948 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1949 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1950 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1951#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1952 if (maxlvt >= 5)
1953 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1954#endif
1955
1956 local_irq_save(flags);
1957 disable_local_APIC();
1958 local_irq_restore(flags);
1959 return 0;
1960}
1961
1962static int lapic_resume(struct sys_device *dev)
1963{
1964 unsigned int l, h;
1965 unsigned long flags;
1966 int maxlvt;
1967
1968 if (!apic_pm_state.active)
1969 return 0;
1970
1971 maxlvt = lapic_get_maxlvt();
1972
1973 local_irq_save(flags);
1974
1975#ifdef CONFIG_X86_X2APIC
1976 if (x2apic)
1977 enable_x2apic();
1978 else
1979#endif
1980 {
1981 /*
1982 * Make sure the APICBASE points to the right address
1983 *
1984 * FIXME! This will be wrong if we ever support suspend on
1985 * SMP! We'll need to do this as part of the CPU restore!
1986 */
1987 rdmsr(MSR_IA32_APICBASE, l, h);
1988 l &= ~MSR_IA32_APICBASE_BASE;
1989 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1990 wrmsr(MSR_IA32_APICBASE, l, h);
1991 }
1992
1993 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1994 apic_write(APIC_ID, apic_pm_state.apic_id);
1995 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1996 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1997 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1998 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1999 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2000 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2001#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2002 if (maxlvt >= 5)
2003 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2004#endif
2005 if (maxlvt >= 4)
2006 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2007 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2008 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2009 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2010 apic_write(APIC_ESR, 0);
2011 apic_read(APIC_ESR);
2012 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2013 apic_write(APIC_ESR, 0);
2014 apic_read(APIC_ESR);
2015
2016 local_irq_restore(flags);
2017
2018 return 0;
2019}
2020
2021/*
2022 * This device has no shutdown method - fully functioning local APICs
2023 * are needed on every CPU up until machine_halt/restart/poweroff.
2024 */
2025
2026static struct sysdev_class lapic_sysclass = {
2027 .name = "lapic",
2028 .resume = lapic_resume,
2029 .suspend = lapic_suspend,
2030};
2031
2032static struct sys_device device_lapic = {
2033 .id = 0,
2034 .cls = &lapic_sysclass,
2035};
2036
2037static void __cpuinit apic_pm_activate(void)
2038{
2039 apic_pm_state.active = 1;
2040}
2041
2042static int __init init_lapic_sysfs(void)
2043{
2044 int error;
2045
2046 if (!cpu_has_apic)
2047 return 0;
2048 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2049
2050 error = sysdev_class_register(&lapic_sysclass);
2051 if (!error)
2052 error = sysdev_register(&device_lapic);
2053 return error;
2054}
2055device_initcall(init_lapic_sysfs);
2056
2057#else /* CONFIG_PM */
2058
2059static void apic_pm_activate(void) { }
2060
2061#endif /* CONFIG_PM */
2062
2063#ifdef CONFIG_X86_64
2064/*
2065 * apic_is_clustered_box() -- Check if we can expect good TSC
2066 *
2067 * Thus far, the major user of this is IBM's Summit2 series:
2068 *
2069 * Clustered boxes may have unsynced TSC problems if they are
2070 * multi-chassis. Use available data to take a good guess.
2071 * If in doubt, go HPET.
2072 */
2073__cpuinit int apic_is_clustered_box(void)
2074{
2075 int i, clusters, zeros;
2076 unsigned id;
2077 u16 *bios_cpu_apicid;
2078 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2079
2080 /*
2081 * there is not this kind of box with AMD CPU yet.
2082 * Some AMD box with quadcore cpu and 8 sockets apicid
2083 * will be [4, 0x23] or [8, 0x27] could be thought to
2084 * vsmp box still need checking...
2085 */
2086 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2087 return 0;
2088
2089 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2090 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2091
2092 for (i = 0; i < nr_cpu_ids; i++) {
2093 /* are we being called early in kernel startup? */
2094 if (bios_cpu_apicid) {
2095 id = bios_cpu_apicid[i];
2096 } else if (i < nr_cpu_ids) {
2097 if (cpu_present(i))
2098 id = per_cpu(x86_bios_cpu_apicid, i);
2099 else
2100 continue;
2101 } else
2102 break;
2103
2104 if (id != BAD_APICID)
2105 __set_bit(APIC_CLUSTERID(id), clustermap);
2106 }
2107
2108 /* Problem: Partially populated chassis may not have CPUs in some of
2109 * the APIC clusters they have been allocated. Only present CPUs have
2110 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2111 * Since clusters are allocated sequentially, count zeros only if
2112 * they are bounded by ones.
2113 */
2114 clusters = 0;
2115 zeros = 0;
2116 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2117 if (test_bit(i, clustermap)) {
2118 clusters += 1 + zeros;
2119 zeros = 0;
2120 } else
2121 ++zeros;
2122 }
2123
2124 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2125 * not guaranteed to be synced between boards
2126 */
2127 if (is_vsmp_box() && clusters > 1)
2128 return 1;
2129
2130 /*
2131 * If clusters > 2, then should be multi-chassis.
2132 * May have to revisit this when multi-core + hyperthreaded CPUs come
2133 * out, but AFAIK this will work even for them.
2134 */
2135 return (clusters > 2);
2136}
2137#endif
2138
2139/*
2140 * APIC command line parameters
2141 */
2142static int __init setup_disableapic(char *arg)
2143{
2144 disable_apic = 1;
2145 setup_clear_cpu_cap(X86_FEATURE_APIC);
2146 return 0;
2147}
2148early_param("disableapic", setup_disableapic);
2149
2150/* same as disableapic, for compatibility */
2151static int __init setup_nolapic(char *arg)
2152{
2153 return setup_disableapic(arg);
2154}
2155early_param("nolapic", setup_nolapic);
2156
2157static int __init parse_lapic_timer_c2_ok(char *arg)
2158{
2159 local_apic_timer_c2_ok = 1;
2160 return 0;
2161}
2162early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2163
2164static int __init parse_disable_apic_timer(char *arg)
2165{
2166 disable_apic_timer = 1;
2167 return 0;
2168}
2169early_param("noapictimer", parse_disable_apic_timer);
2170
2171static int __init parse_nolapic_timer(char *arg)
2172{
2173 disable_apic_timer = 1;
2174 return 0;
2175}
2176early_param("nolapic_timer", parse_nolapic_timer);
2177
2178static int __init apic_set_verbosity(char *arg)
2179{
2180 if (!arg) {
2181#ifdef CONFIG_X86_64
2182 skip_ioapic_setup = 0;
2183 return 0;
2184#endif
2185 return -EINVAL;
2186 }
2187
2188 if (strcmp("debug", arg) == 0)
2189 apic_verbosity = APIC_DEBUG;
2190 else if (strcmp("verbose", arg) == 0)
2191 apic_verbosity = APIC_VERBOSE;
2192 else {
2193 pr_warning("APIC Verbosity level %s not recognised"
2194 " use apic=verbose or apic=debug\n", arg);
2195 return -EINVAL;
2196 }
2197
2198 return 0;
2199}
2200early_param("apic", apic_set_verbosity);
2201
2202static int __init lapic_insert_resource(void)
2203{
2204 if (!apic_phys)
2205 return -1;
2206
2207 /* Put local APIC into the resource map. */
2208 lapic_resource.start = apic_phys;
2209 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2210 insert_resource(&iomem_resource, &lapic_resource);
2211
2212 return 0;
2213}
2214
2215/*
2216 * need call insert after e820_reserve_resources()
2217 * that is using request_resource
2218 */
2219late_initcall(lapic_insert_resource);
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
new file mode 100644
index 000000000000..f933822dba18
--- /dev/null
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -0,0 +1,387 @@
1/*
2 * Copyright 2004 James Cleverdon, IBM.
3 * Subject to the GNU Public License, v.2
4 *
5 * Flat APIC subarch code.
6 *
7 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
9 * James Cleverdon.
10 */
11#include <linux/errno.h>
12#include <linux/threads.h>
13#include <linux/cpumask.h>
14#include <linux/string.h>
15#include <linux/kernel.h>
16#include <linux/ctype.h>
17#include <linux/init.h>
18#include <linux/hardirq.h>
19#include <asm/smp.h>
20#include <asm/apic.h>
21#include <asm/ipi.h>
22
23#ifdef CONFIG_ACPI
24#include <acpi/acpi_bus.h>
25#endif
26
27static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
28{
29 return 1;
30}
31
32static const struct cpumask *flat_target_cpus(void)
33{
34 return cpu_online_mask;
35}
36
37static void flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
38{
39 /* Careful. Some cpus do not strictly honor the set of cpus
40 * specified in the interrupt destination when using lowest
41 * priority interrupt delivery mode.
42 *
43 * In particular there was a hyperthreading cpu observed to
44 * deliver interrupts to the wrong hyperthread when only one
45 * hyperthread was specified in the interrupt desitination.
46 */
47 cpumask_clear(retmask);
48 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
49}
50
51/*
52 * Set up the logical destination ID.
53 *
54 * Intel recommends to set DFR, LDR and TPR before enabling
55 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
56 * document number 292116). So here it goes...
57 */
58static void flat_init_apic_ldr(void)
59{
60 unsigned long val;
61 unsigned long num, id;
62
63 num = smp_processor_id();
64 id = 1UL << num;
65 apic_write(APIC_DFR, APIC_DFR_FLAT);
66 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
67 val |= SET_APIC_LOGICAL_ID(id);
68 apic_write(APIC_LDR, val);
69}
70
71static inline void _flat_send_IPI_mask(unsigned long mask, int vector)
72{
73 unsigned long flags;
74
75 local_irq_save(flags);
76 __default_send_IPI_dest_field(mask, vector, apic->dest_logical);
77 local_irq_restore(flags);
78}
79
80static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector)
81{
82 unsigned long mask = cpumask_bits(cpumask)[0];
83
84 _flat_send_IPI_mask(mask, vector);
85}
86
87static void
88 flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector)
89{
90 unsigned long mask = cpumask_bits(cpumask)[0];
91 int cpu = smp_processor_id();
92
93 if (cpu < BITS_PER_LONG)
94 clear_bit(cpu, &mask);
95
96 _flat_send_IPI_mask(mask, vector);
97}
98
99static void flat_send_IPI_allbutself(int vector)
100{
101 int cpu = smp_processor_id();
102#ifdef CONFIG_HOTPLUG_CPU
103 int hotplug = 1;
104#else
105 int hotplug = 0;
106#endif
107 if (hotplug || vector == NMI_VECTOR) {
108 if (!cpumask_equal(cpu_online_mask, cpumask_of(cpu))) {
109 unsigned long mask = cpumask_bits(cpu_online_mask)[0];
110
111 if (cpu < BITS_PER_LONG)
112 clear_bit(cpu, &mask);
113
114 _flat_send_IPI_mask(mask, vector);
115 }
116 } else if (num_online_cpus() > 1) {
117 __default_send_IPI_shortcut(APIC_DEST_ALLBUT,
118 vector, apic->dest_logical);
119 }
120}
121
122static void flat_send_IPI_all(int vector)
123{
124 if (vector == NMI_VECTOR) {
125 flat_send_IPI_mask(cpu_online_mask, vector);
126 } else {
127 __default_send_IPI_shortcut(APIC_DEST_ALLINC,
128 vector, apic->dest_logical);
129 }
130}
131
132static unsigned int flat_get_apic_id(unsigned long x)
133{
134 unsigned int id;
135
136 id = (((x)>>24) & 0xFFu);
137
138 return id;
139}
140
141static unsigned long set_apic_id(unsigned int id)
142{
143 unsigned long x;
144
145 x = ((id & 0xFFu)<<24);
146 return x;
147}
148
149static unsigned int read_xapic_id(void)
150{
151 unsigned int id;
152
153 id = flat_get_apic_id(apic_read(APIC_ID));
154 return id;
155}
156
157static int flat_apic_id_registered(void)
158{
159 return physid_isset(read_xapic_id(), phys_cpu_present_map);
160}
161
162static unsigned int flat_cpu_mask_to_apicid(const struct cpumask *cpumask)
163{
164 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
165}
166
167static unsigned int flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
168 const struct cpumask *andmask)
169{
170 unsigned long mask1 = cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
171 unsigned long mask2 = cpumask_bits(andmask)[0] & APIC_ALL_CPUS;
172
173 return mask1 & mask2;
174}
175
176static int flat_phys_pkg_id(int initial_apic_id, int index_msb)
177{
178 return hard_smp_processor_id() >> index_msb;
179}
180
181struct apic apic_flat = {
182 .name = "flat",
183 .probe = NULL,
184 .acpi_madt_oem_check = flat_acpi_madt_oem_check,
185 .apic_id_registered = flat_apic_id_registered,
186
187 .irq_delivery_mode = dest_LowestPrio,
188 .irq_dest_mode = 1, /* logical */
189
190 .target_cpus = flat_target_cpus,
191 .disable_esr = 0,
192 .dest_logical = APIC_DEST_LOGICAL,
193 .check_apicid_used = NULL,
194 .check_apicid_present = NULL,
195
196 .vector_allocation_domain = flat_vector_allocation_domain,
197 .init_apic_ldr = flat_init_apic_ldr,
198
199 .ioapic_phys_id_map = NULL,
200 .setup_apic_routing = NULL,
201 .multi_timer_check = NULL,
202 .apicid_to_node = NULL,
203 .cpu_to_logical_apicid = NULL,
204 .cpu_present_to_apicid = default_cpu_present_to_apicid,
205 .apicid_to_cpu_present = NULL,
206 .setup_portio_remap = NULL,
207 .check_phys_apicid_present = default_check_phys_apicid_present,
208 .enable_apic_mode = NULL,
209 .phys_pkg_id = flat_phys_pkg_id,
210 .mps_oem_check = NULL,
211
212 .get_apic_id = flat_get_apic_id,
213 .set_apic_id = set_apic_id,
214 .apic_id_mask = 0xFFu << 24,
215
216 .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
217 .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and,
218
219 .send_IPI_mask = flat_send_IPI_mask,
220 .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself,
221 .send_IPI_allbutself = flat_send_IPI_allbutself,
222 .send_IPI_all = flat_send_IPI_all,
223 .send_IPI_self = apic_send_IPI_self,
224
225 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
226 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
227 .wait_for_init_deassert = NULL,
228 .smp_callin_clear_local_apic = NULL,
229 .inquire_remote_apic = NULL,
230
231 .read = native_apic_mem_read,
232 .write = native_apic_mem_write,
233 .icr_read = native_apic_icr_read,
234 .icr_write = native_apic_icr_write,
235 .wait_icr_idle = native_apic_wait_icr_idle,
236 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
237};
238
239/*
240 * Physflat mode is used when there are more than 8 CPUs on a AMD system.
241 * We cannot use logical delivery in this case because the mask
242 * overflows, so use physical mode.
243 */
244static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
245{
246#ifdef CONFIG_ACPI
247 /*
248 * Quirk: some x86_64 machines can only use physical APIC mode
249 * regardless of how many processors are present (x86_64 ES7000
250 * is an example).
251 */
252 if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
253 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
254 printk(KERN_DEBUG "system APIC only can use physical flat");
255 return 1;
256 }
257#endif
258
259 return 0;
260}
261
262static const struct cpumask *physflat_target_cpus(void)
263{
264 return cpu_online_mask;
265}
266
267static void physflat_vector_allocation_domain(int cpu, struct cpumask *retmask)
268{
269 cpumask_clear(retmask);
270 cpumask_set_cpu(cpu, retmask);
271}
272
273static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector)
274{
275 default_send_IPI_mask_sequence_phys(cpumask, vector);
276}
277
278static void physflat_send_IPI_mask_allbutself(const struct cpumask *cpumask,
279 int vector)
280{
281 default_send_IPI_mask_allbutself_phys(cpumask, vector);
282}
283
284static void physflat_send_IPI_allbutself(int vector)
285{
286 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
287}
288
289static void physflat_send_IPI_all(int vector)
290{
291 physflat_send_IPI_mask(cpu_online_mask, vector);
292}
293
294static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask)
295{
296 int cpu;
297
298 /*
299 * We're using fixed IRQ delivery, can only return one phys APIC ID.
300 * May as well be the first.
301 */
302 cpu = cpumask_first(cpumask);
303 if ((unsigned)cpu < nr_cpu_ids)
304 return per_cpu(x86_cpu_to_apicid, cpu);
305 else
306 return BAD_APICID;
307}
308
309static unsigned int
310physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
311 const struct cpumask *andmask)
312{
313 int cpu;
314
315 /*
316 * We're using fixed IRQ delivery, can only return one phys APIC ID.
317 * May as well be the first.
318 */
319 for_each_cpu_and(cpu, cpumask, andmask) {
320 if (cpumask_test_cpu(cpu, cpu_online_mask))
321 break;
322 }
323 if (cpu < nr_cpu_ids)
324 return per_cpu(x86_cpu_to_apicid, cpu);
325
326 return BAD_APICID;
327}
328
329struct apic apic_physflat = {
330
331 .name = "physical flat",
332 .probe = NULL,
333 .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
334 .apic_id_registered = flat_apic_id_registered,
335
336 .irq_delivery_mode = dest_Fixed,
337 .irq_dest_mode = 0, /* physical */
338
339 .target_cpus = physflat_target_cpus,
340 .disable_esr = 0,
341 .dest_logical = 0,
342 .check_apicid_used = NULL,
343 .check_apicid_present = NULL,
344
345 .vector_allocation_domain = physflat_vector_allocation_domain,
346 /* not needed, but shouldn't hurt: */
347 .init_apic_ldr = flat_init_apic_ldr,
348
349 .ioapic_phys_id_map = NULL,
350 .setup_apic_routing = NULL,
351 .multi_timer_check = NULL,
352 .apicid_to_node = NULL,
353 .cpu_to_logical_apicid = NULL,
354 .cpu_present_to_apicid = default_cpu_present_to_apicid,
355 .apicid_to_cpu_present = NULL,
356 .setup_portio_remap = NULL,
357 .check_phys_apicid_present = default_check_phys_apicid_present,
358 .enable_apic_mode = NULL,
359 .phys_pkg_id = flat_phys_pkg_id,
360 .mps_oem_check = NULL,
361
362 .get_apic_id = flat_get_apic_id,
363 .set_apic_id = set_apic_id,
364 .apic_id_mask = 0xFFu << 24,
365
366 .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
367 .cpu_mask_to_apicid_and = physflat_cpu_mask_to_apicid_and,
368
369 .send_IPI_mask = physflat_send_IPI_mask,
370 .send_IPI_mask_allbutself = physflat_send_IPI_mask_allbutself,
371 .send_IPI_allbutself = physflat_send_IPI_allbutself,
372 .send_IPI_all = physflat_send_IPI_all,
373 .send_IPI_self = apic_send_IPI_self,
374
375 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
376 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
377 .wait_for_init_deassert = NULL,
378 .smp_callin_clear_local_apic = NULL,
379 .inquire_remote_apic = NULL,
380
381 .read = native_apic_mem_read,
382 .write = native_apic_mem_write,
383 .icr_read = native_apic_icr_read,
384 .icr_write = native_apic_icr_write,
385 .wait_icr_idle = native_apic_wait_icr_idle,
386 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
387};
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
new file mode 100644
index 000000000000..676cdac385c0
--- /dev/null
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -0,0 +1,267 @@
1/*
2 * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs.
3 *
4 * Drives the local APIC in "clustered mode".
5 */
6#include <linux/threads.h>
7#include <linux/cpumask.h>
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/dmi.h>
11#include <linux/smp.h>
12
13#include <asm/apicdef.h>
14#include <asm/fixmap.h>
15#include <asm/mpspec.h>
16#include <asm/apic.h>
17#include <asm/ipi.h>
18
19static unsigned bigsmp_get_apic_id(unsigned long x)
20{
21 return (x >> 24) & 0xFF;
22}
23
24static int bigsmp_apic_id_registered(void)
25{
26 return 1;
27}
28
29static const struct cpumask *bigsmp_target_cpus(void)
30{
31#ifdef CONFIG_SMP
32 return cpu_online_mask;
33#else
34 return cpumask_of(0);
35#endif
36}
37
38static unsigned long bigsmp_check_apicid_used(physid_mask_t bitmap, int apicid)
39{
40 return 0;
41}
42
43static unsigned long bigsmp_check_apicid_present(int bit)
44{
45 return 1;
46}
47
48static inline unsigned long calculate_ldr(int cpu)
49{
50 unsigned long val, id;
51
52 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
53 id = per_cpu(x86_bios_cpu_apicid, cpu);
54 val |= SET_APIC_LOGICAL_ID(id);
55
56 return val;
57}
58
59/*
60 * Set up the logical destination ID.
61 *
62 * Intel recommends to set DFR, LDR and TPR before enabling
63 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
64 * document number 292116). So here it goes...
65 */
66static void bigsmp_init_apic_ldr(void)
67{
68 unsigned long val;
69 int cpu = smp_processor_id();
70
71 apic_write(APIC_DFR, APIC_DFR_FLAT);
72 val = calculate_ldr(cpu);
73 apic_write(APIC_LDR, val);
74}
75
76static void bigsmp_setup_apic_routing(void)
77{
78 printk(KERN_INFO
79 "Enabling APIC mode: Physflat. Using %d I/O APICs\n",
80 nr_ioapics);
81}
82
83static int bigsmp_apicid_to_node(int logical_apicid)
84{
85 return apicid_2_node[hard_smp_processor_id()];
86}
87
88static int bigsmp_cpu_present_to_apicid(int mps_cpu)
89{
90 if (mps_cpu < nr_cpu_ids)
91 return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
92
93 return BAD_APICID;
94}
95
96static physid_mask_t bigsmp_apicid_to_cpu_present(int phys_apicid)
97{
98 return physid_mask_of_physid(phys_apicid);
99}
100
101/* Mapping from cpu number to logical apicid */
102static inline int bigsmp_cpu_to_logical_apicid(int cpu)
103{
104 if (cpu >= nr_cpu_ids)
105 return BAD_APICID;
106 return cpu_physical_id(cpu);
107}
108
109static physid_mask_t bigsmp_ioapic_phys_id_map(physid_mask_t phys_map)
110{
111 /* For clustered we don't have a good way to do this yet - hack */
112 return physids_promote(0xFFL);
113}
114
115static int bigsmp_check_phys_apicid_present(int boot_cpu_physical_apicid)
116{
117 return 1;
118}
119
120/* As we are using single CPU as destination, pick only one CPU here */
121static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask)
122{
123 return bigsmp_cpu_to_logical_apicid(cpumask_first(cpumask));
124}
125
126static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
127 const struct cpumask *andmask)
128{
129 int cpu;
130
131 /*
132 * We're using fixed IRQ delivery, can only return one phys APIC ID.
133 * May as well be the first.
134 */
135 for_each_cpu_and(cpu, cpumask, andmask) {
136 if (cpumask_test_cpu(cpu, cpu_online_mask))
137 break;
138 }
139 if (cpu < nr_cpu_ids)
140 return bigsmp_cpu_to_logical_apicid(cpu);
141
142 return BAD_APICID;
143}
144
145static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb)
146{
147 return cpuid_apic >> index_msb;
148}
149
150static inline void bigsmp_send_IPI_mask(const struct cpumask *mask, int vector)
151{
152 default_send_IPI_mask_sequence_phys(mask, vector);
153}
154
155static void bigsmp_send_IPI_allbutself(int vector)
156{
157 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
158}
159
160static void bigsmp_send_IPI_all(int vector)
161{
162 bigsmp_send_IPI_mask(cpu_online_mask, vector);
163}
164
165static int dmi_bigsmp; /* can be set by dmi scanners */
166
167static int hp_ht_bigsmp(const struct dmi_system_id *d)
168{
169 printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
170 dmi_bigsmp = 1;
171
172 return 0;
173}
174
175
176static const struct dmi_system_id bigsmp_dmi_table[] = {
177 { hp_ht_bigsmp, "HP ProLiant DL760 G2",
178 { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
179 DMI_MATCH(DMI_BIOS_VERSION, "P44-"),
180 }
181 },
182
183 { hp_ht_bigsmp, "HP ProLiant DL740",
184 { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
185 DMI_MATCH(DMI_BIOS_VERSION, "P47-"),
186 }
187 },
188 { } /* NULL entry stops DMI scanning */
189};
190
191static void bigsmp_vector_allocation_domain(int cpu, struct cpumask *retmask)
192{
193 cpumask_clear(retmask);
194 cpumask_set_cpu(cpu, retmask);
195}
196
197static int probe_bigsmp(void)
198{
199 if (def_to_bigsmp)
200 dmi_bigsmp = 1;
201 else
202 dmi_check_system(bigsmp_dmi_table);
203
204 return dmi_bigsmp;
205}
206
207struct apic apic_bigsmp = {
208
209 .name = "bigsmp",
210 .probe = probe_bigsmp,
211 .acpi_madt_oem_check = NULL,
212 .apic_id_registered = bigsmp_apic_id_registered,
213
214 .irq_delivery_mode = dest_Fixed,
215 /* phys delivery to target CPU: */
216 .irq_dest_mode = 0,
217
218 .target_cpus = bigsmp_target_cpus,
219 .disable_esr = 1,
220 .dest_logical = 0,
221 .check_apicid_used = bigsmp_check_apicid_used,
222 .check_apicid_present = bigsmp_check_apicid_present,
223
224 .vector_allocation_domain = bigsmp_vector_allocation_domain,
225 .init_apic_ldr = bigsmp_init_apic_ldr,
226
227 .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map,
228 .setup_apic_routing = bigsmp_setup_apic_routing,
229 .multi_timer_check = NULL,
230 .apicid_to_node = bigsmp_apicid_to_node,
231 .cpu_to_logical_apicid = bigsmp_cpu_to_logical_apicid,
232 .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid,
233 .apicid_to_cpu_present = bigsmp_apicid_to_cpu_present,
234 .setup_portio_remap = NULL,
235 .check_phys_apicid_present = bigsmp_check_phys_apicid_present,
236 .enable_apic_mode = NULL,
237 .phys_pkg_id = bigsmp_phys_pkg_id,
238 .mps_oem_check = NULL,
239
240 .get_apic_id = bigsmp_get_apic_id,
241 .set_apic_id = NULL,
242 .apic_id_mask = 0xFF << 24,
243
244 .cpu_mask_to_apicid = bigsmp_cpu_mask_to_apicid,
245 .cpu_mask_to_apicid_and = bigsmp_cpu_mask_to_apicid_and,
246
247 .send_IPI_mask = bigsmp_send_IPI_mask,
248 .send_IPI_mask_allbutself = NULL,
249 .send_IPI_allbutself = bigsmp_send_IPI_allbutself,
250 .send_IPI_all = bigsmp_send_IPI_all,
251 .send_IPI_self = default_send_IPI_self,
252
253 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
254 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
255
256 .wait_for_init_deassert = default_wait_for_init_deassert,
257
258 .smp_callin_clear_local_apic = NULL,
259 .inquire_remote_apic = default_inquire_remote_apic,
260
261 .read = native_apic_mem_read,
262 .write = native_apic_mem_write,
263 .icr_read = native_apic_icr_read,
264 .icr_write = native_apic_icr_write,
265 .wait_icr_idle = native_apic_wait_icr_idle,
266 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
267};
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
new file mode 100644
index 000000000000..1c11b819f245
--- /dev/null
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -0,0 +1,781 @@
1/*
2 * Written by: Garry Forsgren, Unisys Corporation
3 * Natalie Protasevich, Unisys Corporation
4 *
5 * This file contains the code to configure and interface
6 * with Unisys ES7000 series hardware system manager.
7 *
8 * Copyright (c) 2003 Unisys Corporation.
9 * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
10 *
11 * All Rights Reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it would be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 * Contact information: Unisys Corporation, Township Line & Union Meeting
26 * Roads-A, Unisys Way, Blue Bell, Pennsylvania, 19424, or:
27 *
28 * http://www.unisys.com
29 */
30#include <linux/notifier.h>
31#include <linux/spinlock.h>
32#include <linux/cpumask.h>
33#include <linux/threads.h>
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/reboot.h>
37#include <linux/string.h>
38#include <linux/types.h>
39#include <linux/errno.h>
40#include <linux/acpi.h>
41#include <linux/init.h>
42#include <linux/nmi.h>
43#include <linux/smp.h>
44#include <linux/io.h>
45
46#include <asm/apicdef.h>
47#include <asm/atomic.h>
48#include <asm/fixmap.h>
49#include <asm/mpspec.h>
50#include <asm/setup.h>
51#include <asm/apic.h>
52#include <asm/ipi.h>
53
54/*
55 * ES7000 chipsets
56 */
57
58#define NON_UNISYS 0
59#define ES7000_CLASSIC 1
60#define ES7000_ZORRO 2
61
62#define MIP_REG 1
63#define MIP_PSAI_REG 4
64
65#define MIP_BUSY 1
66#define MIP_SPIN 0xf0000
67#define MIP_VALID 0x0100000000000000ULL
68#define MIP_SW_APIC 0x1020b
69
70#define MIP_PORT(val) ((val >> 32) & 0xffff)
71
72#define MIP_RD_LO(val) (val & 0xffffffff)
73
74struct mip_reg {
75 unsigned long long off_0x00;
76 unsigned long long off_0x08;
77 unsigned long long off_0x10;
78 unsigned long long off_0x18;
79 unsigned long long off_0x20;
80 unsigned long long off_0x28;
81 unsigned long long off_0x30;
82 unsigned long long off_0x38;
83};
84
85struct mip_reg_info {
86 unsigned long long mip_info;
87 unsigned long long delivery_info;
88 unsigned long long host_reg;
89 unsigned long long mip_reg;
90};
91
92struct psai {
93 unsigned long long entry_type;
94 unsigned long long addr;
95 unsigned long long bep_addr;
96};
97
98#ifdef CONFIG_ACPI
99
100struct es7000_oem_table {
101 struct acpi_table_header Header;
102 u32 OEMTableAddr;
103 u32 OEMTableSize;
104};
105
106static unsigned long oem_addrX;
107static unsigned long oem_size;
108
109#endif
110
111/*
112 * ES7000 Globals
113 */
114
115static volatile unsigned long *psai;
116static struct mip_reg *mip_reg;
117static struct mip_reg *host_reg;
118static int mip_port;
119static unsigned long mip_addr;
120static unsigned long host_addr;
121
122int es7000_plat;
123
124/*
125 * GSI override for ES7000 platforms.
126 */
127
128static unsigned int base;
129
130static int
131es7000_rename_gsi(int ioapic, int gsi)
132{
133 if (es7000_plat == ES7000_ZORRO)
134 return gsi;
135
136 if (!base) {
137 int i;
138 for (i = 0; i < nr_ioapics; i++)
139 base += nr_ioapic_registers[i];
140 }
141
142 if (!ioapic && (gsi < 16))
143 gsi += base;
144
145 return gsi;
146}
147
148static int wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
149{
150 unsigned long vect = 0, psaival = 0;
151
152 if (psai == NULL)
153 return -1;
154
155 vect = ((unsigned long)__pa(eip)/0x1000) << 16;
156 psaival = (0x1000000 | vect | cpu);
157
158 while (*psai & 0x1000000)
159 ;
160
161 *psai = psaival;
162
163 return 0;
164}
165
166static int es7000_apic_is_cluster(void)
167{
168 /* MPENTIUMIII */
169 if (boot_cpu_data.x86 == 6 &&
170 (boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11))
171 return 1;
172
173 return 0;
174}
175
176static void setup_unisys(void)
177{
178 /*
179 * Determine the generation of the ES7000 currently running.
180 *
181 * es7000_plat = 1 if the machine is a 5xx ES7000 box
182 * es7000_plat = 2 if the machine is a x86_64 ES7000 box
183 *
184 */
185 if (!(boot_cpu_data.x86 <= 15 && boot_cpu_data.x86_model <= 2))
186 es7000_plat = ES7000_ZORRO;
187 else
188 es7000_plat = ES7000_CLASSIC;
189 ioapic_renumber_irq = es7000_rename_gsi;
190}
191
192/*
193 * Parse the OEM Table:
194 */
195static int parse_unisys_oem(char *oemptr)
196{
197 int i;
198 int success = 0;
199 unsigned char type, size;
200 unsigned long val;
201 char *tp = NULL;
202 struct psai *psaip = NULL;
203 struct mip_reg_info *mi;
204 struct mip_reg *host, *mip;
205
206 tp = oemptr;
207
208 tp += 8;
209
210 for (i = 0; i <= 6; i++) {
211 type = *tp++;
212 size = *tp++;
213 tp -= 2;
214 switch (type) {
215 case MIP_REG:
216 mi = (struct mip_reg_info *)tp;
217 val = MIP_RD_LO(mi->host_reg);
218 host_addr = val;
219 host = (struct mip_reg *)val;
220 host_reg = __va(host);
221 val = MIP_RD_LO(mi->mip_reg);
222 mip_port = MIP_PORT(mi->mip_info);
223 mip_addr = val;
224 mip = (struct mip_reg *)val;
225 mip_reg = __va(mip);
226 pr_debug("es7000_mipcfg: host_reg = 0x%lx \n",
227 (unsigned long)host_reg);
228 pr_debug("es7000_mipcfg: mip_reg = 0x%lx \n",
229 (unsigned long)mip_reg);
230 success++;
231 break;
232 case MIP_PSAI_REG:
233 psaip = (struct psai *)tp;
234 if (tp != NULL) {
235 if (psaip->addr)
236 psai = __va(psaip->addr);
237 else
238 psai = NULL;
239 success++;
240 }
241 break;
242 default:
243 break;
244 }
245 tp += size;
246 }
247
248 if (success < 2)
249 es7000_plat = NON_UNISYS;
250 else
251 setup_unisys();
252
253 return es7000_plat;
254}
255
256#ifdef CONFIG_ACPI
257static int find_unisys_acpi_oem_table(unsigned long *oem_addr)
258{
259 struct acpi_table_header *header = NULL;
260 struct es7000_oem_table *table;
261 acpi_size tbl_size;
262 acpi_status ret;
263 int i = 0;
264
265 for (;;) {
266 ret = acpi_get_table_with_size("OEM1", i++, &header, &tbl_size);
267 if (!ACPI_SUCCESS(ret))
268 return -1;
269
270 if (!memcmp((char *) &header->oem_id, "UNISYS", 6))
271 break;
272
273 early_acpi_os_unmap_memory(header, tbl_size);
274 }
275
276 table = (void *)header;
277
278 oem_addrX = table->OEMTableAddr;
279 oem_size = table->OEMTableSize;
280
281 early_acpi_os_unmap_memory(header, tbl_size);
282
283 *oem_addr = (unsigned long)__acpi_map_table(oem_addrX, oem_size);
284
285 return 0;
286}
287
288static void unmap_unisys_acpi_oem_table(unsigned long oem_addr)
289{
290 if (!oem_addr)
291 return;
292
293 __acpi_unmap_table((char *)oem_addr, oem_size);
294}
295
296static int es7000_check_dsdt(void)
297{
298 struct acpi_table_header header;
299
300 if (ACPI_SUCCESS(acpi_get_table_header(ACPI_SIG_DSDT, 0, &header)) &&
301 !strncmp(header.oem_id, "UNISYS", 6))
302 return 1;
303 return 0;
304}
305
306static int es7000_acpi_ret;
307
308/* Hook from generic ACPI tables.c */
309static int es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
310{
311 unsigned long oem_addr = 0;
312 int check_dsdt;
313 int ret = 0;
314
315 /* check dsdt at first to avoid clear fix_map for oem_addr */
316 check_dsdt = es7000_check_dsdt();
317
318 if (!find_unisys_acpi_oem_table(&oem_addr)) {
319 if (check_dsdt) {
320 ret = parse_unisys_oem((char *)oem_addr);
321 } else {
322 setup_unisys();
323 ret = 1;
324 }
325 /*
326 * we need to unmap it
327 */
328 unmap_unisys_acpi_oem_table(oem_addr);
329 }
330
331 es7000_acpi_ret = ret;
332
333 return ret && !es7000_apic_is_cluster();
334}
335
336static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
337{
338 int ret = es7000_acpi_ret;
339
340 return ret && es7000_apic_is_cluster();
341}
342
343#else /* !CONFIG_ACPI: */
344static int es7000_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
345{
346 return 0;
347}
348
349static int es7000_acpi_madt_oem_check_cluster(char *oem_id, char *oem_table_id)
350{
351 return 0;
352}
353#endif /* !CONFIG_ACPI */
354
355static void es7000_spin(int n)
356{
357 int i = 0;
358
359 while (i++ < n)
360 rep_nop();
361}
362
363static int es7000_mip_write(struct mip_reg *mip_reg)
364{
365 int status = 0;
366 int spin;
367
368 spin = MIP_SPIN;
369 while ((host_reg->off_0x38 & MIP_VALID) != 0) {
370 if (--spin <= 0) {
371 WARN(1, "Timeout waiting for Host Valid Flag\n");
372 return -1;
373 }
374 es7000_spin(MIP_SPIN);
375 }
376
377 memcpy(host_reg, mip_reg, sizeof(struct mip_reg));
378 outb(1, mip_port);
379
380 spin = MIP_SPIN;
381
382 while ((mip_reg->off_0x38 & MIP_VALID) == 0) {
383 if (--spin <= 0) {
384 WARN(1, "Timeout waiting for MIP Valid Flag\n");
385 return -1;
386 }
387 es7000_spin(MIP_SPIN);
388 }
389
390 status = (mip_reg->off_0x00 & 0xffff0000000000ULL) >> 48;
391 mip_reg->off_0x38 &= ~MIP_VALID;
392
393 return status;
394}
395
396static void es7000_enable_apic_mode(void)
397{
398 struct mip_reg es7000_mip_reg;
399 int mip_status;
400
401 if (!es7000_plat)
402 return;
403
404 printk(KERN_INFO "ES7000: Enabling APIC mode.\n");
405 memset(&es7000_mip_reg, 0, sizeof(struct mip_reg));
406 es7000_mip_reg.off_0x00 = MIP_SW_APIC;
407 es7000_mip_reg.off_0x38 = MIP_VALID;
408
409 while ((mip_status = es7000_mip_write(&es7000_mip_reg)) != 0)
410 WARN(1, "Command failed, status = %x\n", mip_status);
411}
412
413static void es7000_vector_allocation_domain(int cpu, struct cpumask *retmask)
414{
415 /* Careful. Some cpus do not strictly honor the set of cpus
416 * specified in the interrupt destination when using lowest
417 * priority interrupt delivery mode.
418 *
419 * In particular there was a hyperthreading cpu observed to
420 * deliver interrupts to the wrong hyperthread when only one
421 * hyperthread was specified in the interrupt desitination.
422 */
423 cpumask_clear(retmask);
424 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
425}
426
427
428static void es7000_wait_for_init_deassert(atomic_t *deassert)
429{
430 while (!atomic_read(deassert))
431 cpu_relax();
432}
433
434static unsigned int es7000_get_apic_id(unsigned long x)
435{
436 return (x >> 24) & 0xFF;
437}
438
439static void es7000_send_IPI_mask(const struct cpumask *mask, int vector)
440{
441 default_send_IPI_mask_sequence_phys(mask, vector);
442}
443
444static void es7000_send_IPI_allbutself(int vector)
445{
446 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
447}
448
449static void es7000_send_IPI_all(int vector)
450{
451 es7000_send_IPI_mask(cpu_online_mask, vector);
452}
453
454static int es7000_apic_id_registered(void)
455{
456 return 1;
457}
458
459static const struct cpumask *target_cpus_cluster(void)
460{
461 return cpu_all_mask;
462}
463
464static const struct cpumask *es7000_target_cpus(void)
465{
466 return cpumask_of(smp_processor_id());
467}
468
469static unsigned long
470es7000_check_apicid_used(physid_mask_t bitmap, int apicid)
471{
472 return 0;
473}
474static unsigned long es7000_check_apicid_present(int bit)
475{
476 return physid_isset(bit, phys_cpu_present_map);
477}
478
479static unsigned long calculate_ldr(int cpu)
480{
481 unsigned long id = per_cpu(x86_bios_cpu_apicid, cpu);
482
483 return SET_APIC_LOGICAL_ID(id);
484}
485
486/*
487 * Set up the logical destination ID.
488 *
489 * Intel recommends to set DFR, LdR and TPR before enabling
490 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
491 * document number 292116). So here it goes...
492 */
493static void es7000_init_apic_ldr_cluster(void)
494{
495 unsigned long val;
496 int cpu = smp_processor_id();
497
498 apic_write(APIC_DFR, APIC_DFR_CLUSTER);
499 val = calculate_ldr(cpu);
500 apic_write(APIC_LDR, val);
501}
502
503static void es7000_init_apic_ldr(void)
504{
505 unsigned long val;
506 int cpu = smp_processor_id();
507
508 apic_write(APIC_DFR, APIC_DFR_FLAT);
509 val = calculate_ldr(cpu);
510 apic_write(APIC_LDR, val);
511}
512
513static void es7000_setup_apic_routing(void)
514{
515 int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
516
517 printk(KERN_INFO
518 "Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
519 (apic_version[apic] == 0x14) ?
520 "Physical Cluster" : "Logical Cluster",
521 nr_ioapics, cpumask_bits(es7000_target_cpus())[0]);
522}
523
524static int es7000_apicid_to_node(int logical_apicid)
525{
526 return 0;
527}
528
529
530static int es7000_cpu_present_to_apicid(int mps_cpu)
531{
532 if (!mps_cpu)
533 return boot_cpu_physical_apicid;
534 else if (mps_cpu < nr_cpu_ids)
535 return per_cpu(x86_bios_cpu_apicid, mps_cpu);
536 else
537 return BAD_APICID;
538}
539
540static int cpu_id;
541
542static physid_mask_t es7000_apicid_to_cpu_present(int phys_apicid)
543{
544 physid_mask_t mask;
545
546 mask = physid_mask_of_physid(cpu_id);
547 ++cpu_id;
548
549 return mask;
550}
551
552/* Mapping from cpu number to logical apicid */
553static int es7000_cpu_to_logical_apicid(int cpu)
554{
555#ifdef CONFIG_SMP
556 if (cpu >= nr_cpu_ids)
557 return BAD_APICID;
558 return cpu_2_logical_apicid[cpu];
559#else
560 return logical_smp_processor_id();
561#endif
562}
563
564static physid_mask_t es7000_ioapic_phys_id_map(physid_mask_t phys_map)
565{
566 /* For clustered we don't have a good way to do this yet - hack */
567 return physids_promote(0xff);
568}
569
570static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
571{
572 boot_cpu_physical_apicid = read_apic_id();
573 return 1;
574}
575
576static unsigned int es7000_cpu_mask_to_apicid(const struct cpumask *cpumask)
577{
578 unsigned int round = 0;
579 int cpu, uninitialized_var(apicid);
580
581 /*
582 * The cpus in the mask must all be on the apic cluster.
583 */
584 for_each_cpu(cpu, cpumask) {
585 int new_apicid = es7000_cpu_to_logical_apicid(cpu);
586
587 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
588 WARN(1, "Not a valid mask!");
589
590 return BAD_APICID;
591 }
592 apicid = new_apicid;
593 round++;
594 }
595 return apicid;
596}
597
598static unsigned int
599es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask,
600 const struct cpumask *andmask)
601{
602 int apicid = es7000_cpu_to_logical_apicid(0);
603 cpumask_var_t cpumask;
604
605 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
606 return apicid;
607
608 cpumask_and(cpumask, inmask, andmask);
609 cpumask_and(cpumask, cpumask, cpu_online_mask);
610 apicid = es7000_cpu_mask_to_apicid(cpumask);
611
612 free_cpumask_var(cpumask);
613
614 return apicid;
615}
616
617static int es7000_phys_pkg_id(int cpuid_apic, int index_msb)
618{
619 return cpuid_apic >> index_msb;
620}
621
622static int probe_es7000(void)
623{
624 /* probed later in mptable/ACPI hooks */
625 return 0;
626}
627
628static int es7000_mps_ret;
629static int es7000_mps_oem_check(struct mpc_table *mpc, char *oem,
630 char *productid)
631{
632 int ret = 0;
633
634 if (mpc->oemptr) {
635 struct mpc_oemtable *oem_table =
636 (struct mpc_oemtable *)mpc->oemptr;
637
638 if (!strncmp(oem, "UNISYS", 6))
639 ret = parse_unisys_oem((char *)oem_table);
640 }
641
642 es7000_mps_ret = ret;
643
644 return ret && !es7000_apic_is_cluster();
645}
646
647static int es7000_mps_oem_check_cluster(struct mpc_table *mpc, char *oem,
648 char *productid)
649{
650 int ret = es7000_mps_ret;
651
652 return ret && es7000_apic_is_cluster();
653}
654
655struct apic apic_es7000_cluster = {
656
657 .name = "es7000",
658 .probe = probe_es7000,
659 .acpi_madt_oem_check = es7000_acpi_madt_oem_check_cluster,
660 .apic_id_registered = es7000_apic_id_registered,
661
662 .irq_delivery_mode = dest_LowestPrio,
663 /* logical delivery broadcast to all procs: */
664 .irq_dest_mode = 1,
665
666 .target_cpus = target_cpus_cluster,
667 .disable_esr = 1,
668 .dest_logical = 0,
669 .check_apicid_used = es7000_check_apicid_used,
670 .check_apicid_present = es7000_check_apicid_present,
671
672 .vector_allocation_domain = es7000_vector_allocation_domain,
673 .init_apic_ldr = es7000_init_apic_ldr_cluster,
674
675 .ioapic_phys_id_map = es7000_ioapic_phys_id_map,
676 .setup_apic_routing = es7000_setup_apic_routing,
677 .multi_timer_check = NULL,
678 .apicid_to_node = es7000_apicid_to_node,
679 .cpu_to_logical_apicid = es7000_cpu_to_logical_apicid,
680 .cpu_present_to_apicid = es7000_cpu_present_to_apicid,
681 .apicid_to_cpu_present = es7000_apicid_to_cpu_present,
682 .setup_portio_remap = NULL,
683 .check_phys_apicid_present = es7000_check_phys_apicid_present,
684 .enable_apic_mode = es7000_enable_apic_mode,
685 .phys_pkg_id = es7000_phys_pkg_id,
686 .mps_oem_check = es7000_mps_oem_check_cluster,
687
688 .get_apic_id = es7000_get_apic_id,
689 .set_apic_id = NULL,
690 .apic_id_mask = 0xFF << 24,
691
692 .cpu_mask_to_apicid = es7000_cpu_mask_to_apicid,
693 .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and,
694
695 .send_IPI_mask = es7000_send_IPI_mask,
696 .send_IPI_mask_allbutself = NULL,
697 .send_IPI_allbutself = es7000_send_IPI_allbutself,
698 .send_IPI_all = es7000_send_IPI_all,
699 .send_IPI_self = default_send_IPI_self,
700
701 .wakeup_secondary_cpu = wakeup_secondary_cpu_via_mip,
702
703 .trampoline_phys_low = 0x467,
704 .trampoline_phys_high = 0x469,
705
706 .wait_for_init_deassert = NULL,
707
708 /* Nothing to do for most platforms, since cleared by the INIT cycle: */
709 .smp_callin_clear_local_apic = NULL,
710 .inquire_remote_apic = default_inquire_remote_apic,
711
712 .read = native_apic_mem_read,
713 .write = native_apic_mem_write,
714 .icr_read = native_apic_icr_read,
715 .icr_write = native_apic_icr_write,
716 .wait_icr_idle = native_apic_wait_icr_idle,
717 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
718};
719
720struct apic apic_es7000 = {
721
722 .name = "es7000",
723 .probe = probe_es7000,
724 .acpi_madt_oem_check = es7000_acpi_madt_oem_check,
725 .apic_id_registered = es7000_apic_id_registered,
726
727 .irq_delivery_mode = dest_Fixed,
728 /* phys delivery to target CPUs: */
729 .irq_dest_mode = 0,
730
731 .target_cpus = es7000_target_cpus,
732 .disable_esr = 1,
733 .dest_logical = 0,
734 .check_apicid_used = es7000_check_apicid_used,
735 .check_apicid_present = es7000_check_apicid_present,
736
737 .vector_allocation_domain = es7000_vector_allocation_domain,
738 .init_apic_ldr = es7000_init_apic_ldr,
739
740 .ioapic_phys_id_map = es7000_ioapic_phys_id_map,
741 .setup_apic_routing = es7000_setup_apic_routing,
742 .multi_timer_check = NULL,
743 .apicid_to_node = es7000_apicid_to_node,
744 .cpu_to_logical_apicid = es7000_cpu_to_logical_apicid,
745 .cpu_present_to_apicid = es7000_cpu_present_to_apicid,
746 .apicid_to_cpu_present = es7000_apicid_to_cpu_present,
747 .setup_portio_remap = NULL,
748 .check_phys_apicid_present = es7000_check_phys_apicid_present,
749 .enable_apic_mode = es7000_enable_apic_mode,
750 .phys_pkg_id = es7000_phys_pkg_id,
751 .mps_oem_check = es7000_mps_oem_check,
752
753 .get_apic_id = es7000_get_apic_id,
754 .set_apic_id = NULL,
755 .apic_id_mask = 0xFF << 24,
756
757 .cpu_mask_to_apicid = es7000_cpu_mask_to_apicid,
758 .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and,
759
760 .send_IPI_mask = es7000_send_IPI_mask,
761 .send_IPI_mask_allbutself = NULL,
762 .send_IPI_allbutself = es7000_send_IPI_allbutself,
763 .send_IPI_all = es7000_send_IPI_all,
764 .send_IPI_self = default_send_IPI_self,
765
766 .trampoline_phys_low = 0x467,
767 .trampoline_phys_high = 0x469,
768
769 .wait_for_init_deassert = es7000_wait_for_init_deassert,
770
771 /* Nothing to do for most platforms, since cleared by the INIT cycle: */
772 .smp_callin_clear_local_apic = NULL,
773 .inquire_remote_apic = default_inquire_remote_apic,
774
775 .read = native_apic_mem_read,
776 .write = native_apic_mem_write,
777 .icr_read = native_apic_icr_read,
778 .icr_write = native_apic_icr_write,
779 .wait_icr_idle = native_apic_wait_icr_idle,
780 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
781};
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
new file mode 100644
index 000000000000..00e6071cefc4
--- /dev/null
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -0,0 +1,4160 @@
1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/sysdev.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
44#include <linux/hpet.h>
45
46#include <asm/idle.h>
47#include <asm/io.h>
48#include <asm/smp.h>
49#include <asm/cpu.h>
50#include <asm/desc.h>
51#include <asm/proto.h>
52#include <asm/acpi.h>
53#include <asm/dma.h>
54#include <asm/timer.h>
55#include <asm/i8259.h>
56#include <asm/nmi.h>
57#include <asm/msidef.h>
58#include <asm/hypertransport.h>
59#include <asm/setup.h>
60#include <asm/irq_remapping.h>
61#include <asm/hpet.h>
62#include <asm/uv/uv_hub.h>
63#include <asm/uv/uv_irq.h>
64
65#include <asm/apic.h>
66
67#define __apicdebuginit(type) static type __init
68
69/*
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
72 */
73int sis_apic_bug = -1;
74
75static DEFINE_SPINLOCK(ioapic_lock);
76static DEFINE_SPINLOCK(vector_lock);
77
78/*
79 * # of IRQ routing registers
80 */
81int nr_ioapic_registers[MAX_IO_APICS];
82
83/* I/O APIC entries */
84struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
85int nr_ioapics;
86
87/* MP IRQ source entries */
88struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
89
90/* # of MP IRQ source entries */
91int mp_irq_entries;
92
93#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94int mp_bus_id_to_type[MAX_MP_BUSSES];
95#endif
96
97DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
99int skip_ioapic_setup;
100
101void arch_disable_smp_support(void)
102{
103#ifdef CONFIG_PCI
104 noioapicquirk = 1;
105 noioapicreroute = -1;
106#endif
107 skip_ioapic_setup = 1;
108}
109
110static int __init parse_noapic(char *str)
111{
112 /* disable IO-APIC */
113 arch_disable_smp_support();
114 return 0;
115}
116early_param("noapic", parse_noapic);
117
118struct irq_pin_list;
119
120/*
121 * This is performance-critical, we want to do it O(1)
122 *
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
125 */
126
127struct irq_pin_list {
128 int apic, pin;
129 struct irq_pin_list *next;
130};
131
132static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
133{
134 struct irq_pin_list *pin;
135 int node;
136
137 node = cpu_to_node(cpu);
138
139 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
140
141 return pin;
142}
143
144struct irq_cfg {
145 struct irq_pin_list *irq_2_pin;
146 cpumask_var_t domain;
147 cpumask_var_t old_domain;
148 unsigned move_cleanup_count;
149 u8 vector;
150 u8 move_in_progress : 1;
151#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending : 1;
153#endif
154};
155
156/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157#ifdef CONFIG_SPARSE_IRQ
158static struct irq_cfg irq_cfgx[] = {
159#else
160static struct irq_cfg irq_cfgx[NR_IRQS] = {
161#endif
162 [0] = { .vector = IRQ0_VECTOR, },
163 [1] = { .vector = IRQ1_VECTOR, },
164 [2] = { .vector = IRQ2_VECTOR, },
165 [3] = { .vector = IRQ3_VECTOR, },
166 [4] = { .vector = IRQ4_VECTOR, },
167 [5] = { .vector = IRQ5_VECTOR, },
168 [6] = { .vector = IRQ6_VECTOR, },
169 [7] = { .vector = IRQ7_VECTOR, },
170 [8] = { .vector = IRQ8_VECTOR, },
171 [9] = { .vector = IRQ9_VECTOR, },
172 [10] = { .vector = IRQ10_VECTOR, },
173 [11] = { .vector = IRQ11_VECTOR, },
174 [12] = { .vector = IRQ12_VECTOR, },
175 [13] = { .vector = IRQ13_VECTOR, },
176 [14] = { .vector = IRQ14_VECTOR, },
177 [15] = { .vector = IRQ15_VECTOR, },
178};
179
180int __init arch_early_irq_init(void)
181{
182 struct irq_cfg *cfg;
183 struct irq_desc *desc;
184 int count;
185 int i;
186
187 cfg = irq_cfgx;
188 count = ARRAY_SIZE(irq_cfgx);
189
190 for (i = 0; i < count; i++) {
191 desc = irq_to_desc(i);
192 desc->chip_data = &cfg[i];
193 alloc_bootmem_cpumask_var(&cfg[i].domain);
194 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195 if (i < NR_IRQS_LEGACY)
196 cpumask_setall(cfg[i].domain);
197 }
198
199 return 0;
200}
201
202#ifdef CONFIG_SPARSE_IRQ
203static struct irq_cfg *irq_cfg(unsigned int irq)
204{
205 struct irq_cfg *cfg = NULL;
206 struct irq_desc *desc;
207
208 desc = irq_to_desc(irq);
209 if (desc)
210 cfg = desc->chip_data;
211
212 return cfg;
213}
214
215static struct irq_cfg *get_one_free_irq_cfg(int cpu)
216{
217 struct irq_cfg *cfg;
218 int node;
219
220 node = cpu_to_node(cpu);
221
222 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
223 if (cfg) {
224 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
225 kfree(cfg);
226 cfg = NULL;
227 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
228 GFP_ATOMIC, node)) {
229 free_cpumask_var(cfg->domain);
230 kfree(cfg);
231 cfg = NULL;
232 } else {
233 cpumask_clear(cfg->domain);
234 cpumask_clear(cfg->old_domain);
235 }
236 }
237
238 return cfg;
239}
240
241int arch_init_chip_data(struct irq_desc *desc, int cpu)
242{
243 struct irq_cfg *cfg;
244
245 cfg = desc->chip_data;
246 if (!cfg) {
247 desc->chip_data = get_one_free_irq_cfg(cpu);
248 if (!desc->chip_data) {
249 printk(KERN_ERR "can not alloc irq_cfg\n");
250 BUG_ON(1);
251 }
252 }
253
254 return 0;
255}
256
257#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
258
259static void
260init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
261{
262 struct irq_pin_list *old_entry, *head, *tail, *entry;
263
264 cfg->irq_2_pin = NULL;
265 old_entry = old_cfg->irq_2_pin;
266 if (!old_entry)
267 return;
268
269 entry = get_one_free_irq_2_pin(cpu);
270 if (!entry)
271 return;
272
273 entry->apic = old_entry->apic;
274 entry->pin = old_entry->pin;
275 head = entry;
276 tail = entry;
277 old_entry = old_entry->next;
278 while (old_entry) {
279 entry = get_one_free_irq_2_pin(cpu);
280 if (!entry) {
281 entry = head;
282 while (entry) {
283 head = entry->next;
284 kfree(entry);
285 entry = head;
286 }
287 /* still use the old one */
288 return;
289 }
290 entry->apic = old_entry->apic;
291 entry->pin = old_entry->pin;
292 tail->next = entry;
293 tail = entry;
294 old_entry = old_entry->next;
295 }
296
297 tail->next = NULL;
298 cfg->irq_2_pin = head;
299}
300
301static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
302{
303 struct irq_pin_list *entry, *next;
304
305 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
306 return;
307
308 entry = old_cfg->irq_2_pin;
309
310 while (entry) {
311 next = entry->next;
312 kfree(entry);
313 entry = next;
314 }
315 old_cfg->irq_2_pin = NULL;
316}
317
318void arch_init_copy_chip_data(struct irq_desc *old_desc,
319 struct irq_desc *desc, int cpu)
320{
321 struct irq_cfg *cfg;
322 struct irq_cfg *old_cfg;
323
324 cfg = get_one_free_irq_cfg(cpu);
325
326 if (!cfg)
327 return;
328
329 desc->chip_data = cfg;
330
331 old_cfg = old_desc->chip_data;
332
333 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
334
335 init_copy_irq_2_pin(old_cfg, cfg, cpu);
336}
337
338static void free_irq_cfg(struct irq_cfg *old_cfg)
339{
340 kfree(old_cfg);
341}
342
343void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
344{
345 struct irq_cfg *old_cfg, *cfg;
346
347 old_cfg = old_desc->chip_data;
348 cfg = desc->chip_data;
349
350 if (old_cfg == cfg)
351 return;
352
353 if (old_cfg) {
354 free_irq_2_pin(old_cfg, cfg);
355 free_irq_cfg(old_cfg);
356 old_desc->chip_data = NULL;
357 }
358}
359
360static void
361set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
362{
363 struct irq_cfg *cfg = desc->chip_data;
364
365 if (!cfg->move_in_progress) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc->affinity, mask))
368 cfg->move_desc_pending = 1;
369 }
370}
371#endif
372
373#else
374static struct irq_cfg *irq_cfg(unsigned int irq)
375{
376 return irq < nr_irqs ? irq_cfgx + irq : NULL;
377}
378
379#endif
380
381#ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
382static inline void
383set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
384{
385}
386#endif
387
388struct io_apic {
389 unsigned int index;
390 unsigned int unused[3];
391 unsigned int data;
392};
393
394static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
395{
396 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
397 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
398}
399
400static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
401{
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
403 writel(reg, &io_apic->index);
404 return readl(&io_apic->data);
405}
406
407static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
408{
409 struct io_apic __iomem *io_apic = io_apic_base(apic);
410 writel(reg, &io_apic->index);
411 writel(value, &io_apic->data);
412}
413
414/*
415 * Re-write a value: to be used for read-modify-write
416 * cycles where the read already set up the index register.
417 *
418 * Older SiS APIC requires we rewrite the index register
419 */
420static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
421{
422 struct io_apic __iomem *io_apic = io_apic_base(apic);
423
424 if (sis_apic_bug)
425 writel(reg, &io_apic->index);
426 writel(value, &io_apic->data);
427}
428
429static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
430{
431 struct irq_pin_list *entry;
432 unsigned long flags;
433
434 spin_lock_irqsave(&ioapic_lock, flags);
435 entry = cfg->irq_2_pin;
436 for (;;) {
437 unsigned int reg;
438 int pin;
439
440 if (!entry)
441 break;
442 pin = entry->pin;
443 reg = io_apic_read(entry->apic, 0x10 + pin*2);
444 /* Is the remote IRR bit set? */
445 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
446 spin_unlock_irqrestore(&ioapic_lock, flags);
447 return true;
448 }
449 if (!entry->next)
450 break;
451 entry = entry->next;
452 }
453 spin_unlock_irqrestore(&ioapic_lock, flags);
454
455 return false;
456}
457
458union entry_union {
459 struct { u32 w1, w2; };
460 struct IO_APIC_route_entry entry;
461};
462
463static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
464{
465 union entry_union eu;
466 unsigned long flags;
467 spin_lock_irqsave(&ioapic_lock, flags);
468 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
469 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
470 spin_unlock_irqrestore(&ioapic_lock, flags);
471 return eu.entry;
472}
473
474/*
475 * When we write a new IO APIC routing entry, we need to write the high
476 * word first! If the mask bit in the low word is clear, we will enable
477 * the interrupt, and we need to make sure the entry is fully populated
478 * before that happens.
479 */
480static void
481__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
482{
483 union entry_union eu;
484 eu.entry = e;
485 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
486 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
487}
488
489void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
490{
491 unsigned long flags;
492 spin_lock_irqsave(&ioapic_lock, flags);
493 __ioapic_write_entry(apic, pin, e);
494 spin_unlock_irqrestore(&ioapic_lock, flags);
495}
496
497/*
498 * When we mask an IO APIC routing entry, we need to write the low
499 * word first, in order to set the mask bit before we change the
500 * high bits!
501 */
502static void ioapic_mask_entry(int apic, int pin)
503{
504 unsigned long flags;
505 union entry_union eu = { .entry.mask = 1 };
506
507 spin_lock_irqsave(&ioapic_lock, flags);
508 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
509 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
510 spin_unlock_irqrestore(&ioapic_lock, flags);
511}
512
513#ifdef CONFIG_SMP
514static void send_cleanup_vector(struct irq_cfg *cfg)
515{
516 cpumask_var_t cleanup_mask;
517
518 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
519 unsigned int i;
520 cfg->move_cleanup_count = 0;
521 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
522 cfg->move_cleanup_count++;
523 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
524 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
525 } else {
526 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
527 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
528 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
529 free_cpumask_var(cleanup_mask);
530 }
531 cfg->move_in_progress = 0;
532}
533
534static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
535{
536 int apic, pin;
537 struct irq_pin_list *entry;
538 u8 vector = cfg->vector;
539
540 entry = cfg->irq_2_pin;
541 for (;;) {
542 unsigned int reg;
543
544 if (!entry)
545 break;
546
547 apic = entry->apic;
548 pin = entry->pin;
549#ifdef CONFIG_INTR_REMAP
550 /*
551 * With interrupt-remapping, destination information comes
552 * from interrupt-remapping table entry.
553 */
554 if (!irq_remapped(irq))
555 io_apic_write(apic, 0x11 + pin*2, dest);
556#else
557 io_apic_write(apic, 0x11 + pin*2, dest);
558#endif
559 reg = io_apic_read(apic, 0x10 + pin*2);
560 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
561 reg |= vector;
562 io_apic_modify(apic, 0x10 + pin*2, reg);
563 if (!entry->next)
564 break;
565 entry = entry->next;
566 }
567}
568
569static int
570assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
571
572/*
573 * Either sets desc->affinity to a valid value, and returns
574 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
575 * leaves desc->affinity untouched.
576 */
577static unsigned int
578set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
579{
580 struct irq_cfg *cfg;
581 unsigned int irq;
582
583 if (!cpumask_intersects(mask, cpu_online_mask))
584 return BAD_APICID;
585
586 irq = desc->irq;
587 cfg = desc->chip_data;
588 if (assign_irq_vector(irq, cfg, mask))
589 return BAD_APICID;
590
591 cpumask_and(desc->affinity, cfg->domain, mask);
592 set_extra_move_desc(desc, mask);
593
594 return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
595}
596
597static void
598set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
599{
600 struct irq_cfg *cfg;
601 unsigned long flags;
602 unsigned int dest;
603 unsigned int irq;
604
605 irq = desc->irq;
606 cfg = desc->chip_data;
607
608 spin_lock_irqsave(&ioapic_lock, flags);
609 dest = set_desc_affinity(desc, mask);
610 if (dest != BAD_APICID) {
611 /* Only the high 8 bits are valid. */
612 dest = SET_APIC_LOGICAL_ID(dest);
613 __target_IO_APIC_irq(irq, dest, cfg);
614 }
615 spin_unlock_irqrestore(&ioapic_lock, flags);
616}
617
618static void
619set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
620{
621 struct irq_desc *desc;
622
623 desc = irq_to_desc(irq);
624
625 set_ioapic_affinity_irq_desc(desc, mask);
626}
627#endif /* CONFIG_SMP */
628
629/*
630 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
631 * shared ISA-space IRQs, so we have to support them. We are super
632 * fast in the common case, and fast for shared ISA-space IRQs.
633 */
634static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
635{
636 struct irq_pin_list *entry;
637
638 entry = cfg->irq_2_pin;
639 if (!entry) {
640 entry = get_one_free_irq_2_pin(cpu);
641 if (!entry) {
642 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
643 apic, pin);
644 return;
645 }
646 cfg->irq_2_pin = entry;
647 entry->apic = apic;
648 entry->pin = pin;
649 return;
650 }
651
652 while (entry->next) {
653 /* not again, please */
654 if (entry->apic == apic && entry->pin == pin)
655 return;
656
657 entry = entry->next;
658 }
659
660 entry->next = get_one_free_irq_2_pin(cpu);
661 entry = entry->next;
662 entry->apic = apic;
663 entry->pin = pin;
664}
665
666/*
667 * Reroute an IRQ to a different pin.
668 */
669static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
670 int oldapic, int oldpin,
671 int newapic, int newpin)
672{
673 struct irq_pin_list *entry = cfg->irq_2_pin;
674 int replaced = 0;
675
676 while (entry) {
677 if (entry->apic == oldapic && entry->pin == oldpin) {
678 entry->apic = newapic;
679 entry->pin = newpin;
680 replaced = 1;
681 /* every one is different, right? */
682 break;
683 }
684 entry = entry->next;
685 }
686
687 /* why? call replace before add? */
688 if (!replaced)
689 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
690}
691
692static inline void io_apic_modify_irq(struct irq_cfg *cfg,
693 int mask_and, int mask_or,
694 void (*final)(struct irq_pin_list *entry))
695{
696 int pin;
697 struct irq_pin_list *entry;
698
699 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
700 unsigned int reg;
701 pin = entry->pin;
702 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
703 reg &= mask_and;
704 reg |= mask_or;
705 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
706 if (final)
707 final(entry);
708 }
709}
710
711static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
712{
713 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
714}
715
716#ifdef CONFIG_X86_64
717static void io_apic_sync(struct irq_pin_list *entry)
718{
719 /*
720 * Synchronize the IO-APIC and the CPU by doing
721 * a dummy read from the IO-APIC
722 */
723 struct io_apic __iomem *io_apic;
724 io_apic = io_apic_base(entry->apic);
725 readl(&io_apic->data);
726}
727
728static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
729{
730 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
731}
732#else /* CONFIG_X86_32 */
733static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
734{
735 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
736}
737
738static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
739{
740 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
741 IO_APIC_REDIR_MASKED, NULL);
742}
743
744static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
745{
746 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
747 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
748}
749#endif /* CONFIG_X86_32 */
750
751static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
752{
753 struct irq_cfg *cfg = desc->chip_data;
754 unsigned long flags;
755
756 BUG_ON(!cfg);
757
758 spin_lock_irqsave(&ioapic_lock, flags);
759 __mask_IO_APIC_irq(cfg);
760 spin_unlock_irqrestore(&ioapic_lock, flags);
761}
762
763static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
764{
765 struct irq_cfg *cfg = desc->chip_data;
766 unsigned long flags;
767
768 spin_lock_irqsave(&ioapic_lock, flags);
769 __unmask_IO_APIC_irq(cfg);
770 spin_unlock_irqrestore(&ioapic_lock, flags);
771}
772
773static void mask_IO_APIC_irq(unsigned int irq)
774{
775 struct irq_desc *desc = irq_to_desc(irq);
776
777 mask_IO_APIC_irq_desc(desc);
778}
779static void unmask_IO_APIC_irq(unsigned int irq)
780{
781 struct irq_desc *desc = irq_to_desc(irq);
782
783 unmask_IO_APIC_irq_desc(desc);
784}
785
786static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
787{
788 struct IO_APIC_route_entry entry;
789
790 /* Check delivery_mode to be sure we're not clearing an SMI pin */
791 entry = ioapic_read_entry(apic, pin);
792 if (entry.delivery_mode == dest_SMI)
793 return;
794 /*
795 * Disable it in the IO-APIC irq-routing table:
796 */
797 ioapic_mask_entry(apic, pin);
798}
799
800static void clear_IO_APIC (void)
801{
802 int apic, pin;
803
804 for (apic = 0; apic < nr_ioapics; apic++)
805 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
806 clear_IO_APIC_pin(apic, pin);
807}
808
809#ifdef CONFIG_X86_32
810/*
811 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
812 * specific CPU-side IRQs.
813 */
814
815#define MAX_PIRQS 8
816static int pirq_entries[MAX_PIRQS] = {
817 [0 ... MAX_PIRQS - 1] = -1
818};
819
820static int __init ioapic_pirq_setup(char *str)
821{
822 int i, max;
823 int ints[MAX_PIRQS+1];
824
825 get_options(str, ARRAY_SIZE(ints), ints);
826
827 apic_printk(APIC_VERBOSE, KERN_INFO
828 "PIRQ redirection, working around broken MP-BIOS.\n");
829 max = MAX_PIRQS;
830 if (ints[0] < MAX_PIRQS)
831 max = ints[0];
832
833 for (i = 0; i < max; i++) {
834 apic_printk(APIC_VERBOSE, KERN_DEBUG
835 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
836 /*
837 * PIRQs are mapped upside down, usually.
838 */
839 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
840 }
841 return 1;
842}
843
844__setup("pirq=", ioapic_pirq_setup);
845#endif /* CONFIG_X86_32 */
846
847#ifdef CONFIG_INTR_REMAP
848/* I/O APIC RTE contents at the OS boot up */
849static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
850
851/*
852 * Saves and masks all the unmasked IO-APIC RTE's
853 */
854int save_mask_IO_APIC_setup(void)
855{
856 union IO_APIC_reg_01 reg_01;
857 unsigned long flags;
858 int apic, pin;
859
860 /*
861 * The number of IO-APIC IRQ registers (== #pins):
862 */
863 for (apic = 0; apic < nr_ioapics; apic++) {
864 spin_lock_irqsave(&ioapic_lock, flags);
865 reg_01.raw = io_apic_read(apic, 1);
866 spin_unlock_irqrestore(&ioapic_lock, flags);
867 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
868 }
869
870 for (apic = 0; apic < nr_ioapics; apic++) {
871 early_ioapic_entries[apic] =
872 kzalloc(sizeof(struct IO_APIC_route_entry) *
873 nr_ioapic_registers[apic], GFP_KERNEL);
874 if (!early_ioapic_entries[apic])
875 goto nomem;
876 }
877
878 for (apic = 0; apic < nr_ioapics; apic++)
879 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
880 struct IO_APIC_route_entry entry;
881
882 entry = early_ioapic_entries[apic][pin] =
883 ioapic_read_entry(apic, pin);
884 if (!entry.mask) {
885 entry.mask = 1;
886 ioapic_write_entry(apic, pin, entry);
887 }
888 }
889
890 return 0;
891
892nomem:
893 while (apic >= 0)
894 kfree(early_ioapic_entries[apic--]);
895 memset(early_ioapic_entries, 0,
896 ARRAY_SIZE(early_ioapic_entries));
897
898 return -ENOMEM;
899}
900
901void restore_IO_APIC_setup(void)
902{
903 int apic, pin;
904
905 for (apic = 0; apic < nr_ioapics; apic++) {
906 if (!early_ioapic_entries[apic])
907 break;
908 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
909 ioapic_write_entry(apic, pin,
910 early_ioapic_entries[apic][pin]);
911 kfree(early_ioapic_entries[apic]);
912 early_ioapic_entries[apic] = NULL;
913 }
914}
915
916void reinit_intr_remapped_IO_APIC(int intr_remapping)
917{
918 /*
919 * for now plain restore of previous settings.
920 * TBD: In the case of OS enabling interrupt-remapping,
921 * IO-APIC RTE's need to be setup to point to interrupt-remapping
922 * table entries. for now, do a plain restore, and wait for
923 * the setup_IO_APIC_irqs() to do proper initialization.
924 */
925 restore_IO_APIC_setup();
926}
927#endif
928
929/*
930 * Find the IRQ entry number of a certain pin.
931 */
932static int find_irq_entry(int apic, int pin, int type)
933{
934 int i;
935
936 for (i = 0; i < mp_irq_entries; i++)
937 if (mp_irqs[i].irqtype == type &&
938 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
939 mp_irqs[i].dstapic == MP_APIC_ALL) &&
940 mp_irqs[i].dstirq == pin)
941 return i;
942
943 return -1;
944}
945
946/*
947 * Find the pin to which IRQ[irq] (ISA) is connected
948 */
949static int __init find_isa_irq_pin(int irq, int type)
950{
951 int i;
952
953 for (i = 0; i < mp_irq_entries; i++) {
954 int lbus = mp_irqs[i].srcbus;
955
956 if (test_bit(lbus, mp_bus_not_pci) &&
957 (mp_irqs[i].irqtype == type) &&
958 (mp_irqs[i].srcbusirq == irq))
959
960 return mp_irqs[i].dstirq;
961 }
962 return -1;
963}
964
965static int __init find_isa_irq_apic(int irq, int type)
966{
967 int i;
968
969 for (i = 0; i < mp_irq_entries; i++) {
970 int lbus = mp_irqs[i].srcbus;
971
972 if (test_bit(lbus, mp_bus_not_pci) &&
973 (mp_irqs[i].irqtype == type) &&
974 (mp_irqs[i].srcbusirq == irq))
975 break;
976 }
977 if (i < mp_irq_entries) {
978 int apic;
979 for(apic = 0; apic < nr_ioapics; apic++) {
980 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
981 return apic;
982 }
983 }
984
985 return -1;
986}
987
988/*
989 * Find a specific PCI IRQ entry.
990 * Not an __init, possibly needed by modules
991 */
992static int pin_2_irq(int idx, int apic, int pin);
993
994int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
995{
996 int apic, i, best_guess = -1;
997
998 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
999 bus, slot, pin);
1000 if (test_bit(bus, mp_bus_not_pci)) {
1001 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1002 return -1;
1003 }
1004 for (i = 0; i < mp_irq_entries; i++) {
1005 int lbus = mp_irqs[i].srcbus;
1006
1007 for (apic = 0; apic < nr_ioapics; apic++)
1008 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1009 mp_irqs[i].dstapic == MP_APIC_ALL)
1010 break;
1011
1012 if (!test_bit(lbus, mp_bus_not_pci) &&
1013 !mp_irqs[i].irqtype &&
1014 (bus == lbus) &&
1015 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1016 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1017
1018 if (!(apic || IO_APIC_IRQ(irq)))
1019 continue;
1020
1021 if (pin == (mp_irqs[i].srcbusirq & 3))
1022 return irq;
1023 /*
1024 * Use the first all-but-pin matching entry as a
1025 * best-guess fuzzy result for broken mptables.
1026 */
1027 if (best_guess < 0)
1028 best_guess = irq;
1029 }
1030 }
1031 return best_guess;
1032}
1033
1034EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1035
1036#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1037/*
1038 * EISA Edge/Level control register, ELCR
1039 */
1040static int EISA_ELCR(unsigned int irq)
1041{
1042 if (irq < NR_IRQS_LEGACY) {
1043 unsigned int port = 0x4d0 + (irq >> 3);
1044 return (inb(port) >> (irq & 7)) & 1;
1045 }
1046 apic_printk(APIC_VERBOSE, KERN_INFO
1047 "Broken MPtable reports ISA irq %d\n", irq);
1048 return 0;
1049}
1050
1051#endif
1052
1053/* ISA interrupts are always polarity zero edge triggered,
1054 * when listed as conforming in the MP table. */
1055
1056#define default_ISA_trigger(idx) (0)
1057#define default_ISA_polarity(idx) (0)
1058
1059/* EISA interrupts are always polarity zero and can be edge or level
1060 * trigger depending on the ELCR value. If an interrupt is listed as
1061 * EISA conforming in the MP table, that means its trigger type must
1062 * be read in from the ELCR */
1063
1064#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1065#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1066
1067/* PCI interrupts are always polarity one level triggered,
1068 * when listed as conforming in the MP table. */
1069
1070#define default_PCI_trigger(idx) (1)
1071#define default_PCI_polarity(idx) (1)
1072
1073/* MCA interrupts are always polarity zero level triggered,
1074 * when listed as conforming in the MP table. */
1075
1076#define default_MCA_trigger(idx) (1)
1077#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1078
1079static int MPBIOS_polarity(int idx)
1080{
1081 int bus = mp_irqs[idx].srcbus;
1082 int polarity;
1083
1084 /*
1085 * Determine IRQ line polarity (high active or low active):
1086 */
1087 switch (mp_irqs[idx].irqflag & 3)
1088 {
1089 case 0: /* conforms, ie. bus-type dependent polarity */
1090 if (test_bit(bus, mp_bus_not_pci))
1091 polarity = default_ISA_polarity(idx);
1092 else
1093 polarity = default_PCI_polarity(idx);
1094 break;
1095 case 1: /* high active */
1096 {
1097 polarity = 0;
1098 break;
1099 }
1100 case 2: /* reserved */
1101 {
1102 printk(KERN_WARNING "broken BIOS!!\n");
1103 polarity = 1;
1104 break;
1105 }
1106 case 3: /* low active */
1107 {
1108 polarity = 1;
1109 break;
1110 }
1111 default: /* invalid */
1112 {
1113 printk(KERN_WARNING "broken BIOS!!\n");
1114 polarity = 1;
1115 break;
1116 }
1117 }
1118 return polarity;
1119}
1120
1121static int MPBIOS_trigger(int idx)
1122{
1123 int bus = mp_irqs[idx].srcbus;
1124 int trigger;
1125
1126 /*
1127 * Determine IRQ trigger mode (edge or level sensitive):
1128 */
1129 switch ((mp_irqs[idx].irqflag>>2) & 3)
1130 {
1131 case 0: /* conforms, ie. bus-type dependent */
1132 if (test_bit(bus, mp_bus_not_pci))
1133 trigger = default_ISA_trigger(idx);
1134 else
1135 trigger = default_PCI_trigger(idx);
1136#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1137 switch (mp_bus_id_to_type[bus]) {
1138 case MP_BUS_ISA: /* ISA pin */
1139 {
1140 /* set before the switch */
1141 break;
1142 }
1143 case MP_BUS_EISA: /* EISA pin */
1144 {
1145 trigger = default_EISA_trigger(idx);
1146 break;
1147 }
1148 case MP_BUS_PCI: /* PCI pin */
1149 {
1150 /* set before the switch */
1151 break;
1152 }
1153 case MP_BUS_MCA: /* MCA pin */
1154 {
1155 trigger = default_MCA_trigger(idx);
1156 break;
1157 }
1158 default:
1159 {
1160 printk(KERN_WARNING "broken BIOS!!\n");
1161 trigger = 1;
1162 break;
1163 }
1164 }
1165#endif
1166 break;
1167 case 1: /* edge */
1168 {
1169 trigger = 0;
1170 break;
1171 }
1172 case 2: /* reserved */
1173 {
1174 printk(KERN_WARNING "broken BIOS!!\n");
1175 trigger = 1;
1176 break;
1177 }
1178 case 3: /* level */
1179 {
1180 trigger = 1;
1181 break;
1182 }
1183 default: /* invalid */
1184 {
1185 printk(KERN_WARNING "broken BIOS!!\n");
1186 trigger = 0;
1187 break;
1188 }
1189 }
1190 return trigger;
1191}
1192
1193static inline int irq_polarity(int idx)
1194{
1195 return MPBIOS_polarity(idx);
1196}
1197
1198static inline int irq_trigger(int idx)
1199{
1200 return MPBIOS_trigger(idx);
1201}
1202
1203int (*ioapic_renumber_irq)(int ioapic, int irq);
1204static int pin_2_irq(int idx, int apic, int pin)
1205{
1206 int irq, i;
1207 int bus = mp_irqs[idx].srcbus;
1208
1209 /*
1210 * Debugging check, we are in big trouble if this message pops up!
1211 */
1212 if (mp_irqs[idx].dstirq != pin)
1213 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1214
1215 if (test_bit(bus, mp_bus_not_pci)) {
1216 irq = mp_irqs[idx].srcbusirq;
1217 } else {
1218 /*
1219 * PCI IRQs are mapped in order
1220 */
1221 i = irq = 0;
1222 while (i < apic)
1223 irq += nr_ioapic_registers[i++];
1224 irq += pin;
1225 /*
1226 * For MPS mode, so far only needed by ES7000 platform
1227 */
1228 if (ioapic_renumber_irq)
1229 irq = ioapic_renumber_irq(apic, irq);
1230 }
1231
1232#ifdef CONFIG_X86_32
1233 /*
1234 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1235 */
1236 if ((pin >= 16) && (pin <= 23)) {
1237 if (pirq_entries[pin-16] != -1) {
1238 if (!pirq_entries[pin-16]) {
1239 apic_printk(APIC_VERBOSE, KERN_DEBUG
1240 "disabling PIRQ%d\n", pin-16);
1241 } else {
1242 irq = pirq_entries[pin-16];
1243 apic_printk(APIC_VERBOSE, KERN_DEBUG
1244 "using PIRQ%d -> IRQ %d\n",
1245 pin-16, irq);
1246 }
1247 }
1248 }
1249#endif
1250
1251 return irq;
1252}
1253
1254void lock_vector_lock(void)
1255{
1256 /* Used to the online set of cpus does not change
1257 * during assign_irq_vector.
1258 */
1259 spin_lock(&vector_lock);
1260}
1261
1262void unlock_vector_lock(void)
1263{
1264 spin_unlock(&vector_lock);
1265}
1266
1267static int
1268__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1269{
1270 /*
1271 * NOTE! The local APIC isn't very good at handling
1272 * multiple interrupts at the same interrupt level.
1273 * As the interrupt level is determined by taking the
1274 * vector number and shifting that right by 4, we
1275 * want to spread these out a bit so that they don't
1276 * all fall in the same interrupt level.
1277 *
1278 * Also, we've got to be careful not to trash gate
1279 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1280 */
1281 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1282 unsigned int old_vector;
1283 int cpu, err;
1284 cpumask_var_t tmp_mask;
1285
1286 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1287 return -EBUSY;
1288
1289 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1290 return -ENOMEM;
1291
1292 old_vector = cfg->vector;
1293 if (old_vector) {
1294 cpumask_and(tmp_mask, mask, cpu_online_mask);
1295 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1296 if (!cpumask_empty(tmp_mask)) {
1297 free_cpumask_var(tmp_mask);
1298 return 0;
1299 }
1300 }
1301
1302 /* Only try and allocate irqs on cpus that are present */
1303 err = -ENOSPC;
1304 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1305 int new_cpu;
1306 int vector, offset;
1307
1308 apic->vector_allocation_domain(cpu, tmp_mask);
1309
1310 vector = current_vector;
1311 offset = current_offset;
1312next:
1313 vector += 8;
1314 if (vector >= first_system_vector) {
1315 /* If out of vectors on large boxen, must share them. */
1316 offset = (offset + 1) % 8;
1317 vector = FIRST_DEVICE_VECTOR + offset;
1318 }
1319 if (unlikely(current_vector == vector))
1320 continue;
1321
1322 if (test_bit(vector, used_vectors))
1323 goto next;
1324
1325 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1326 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1327 goto next;
1328 /* Found one! */
1329 current_vector = vector;
1330 current_offset = offset;
1331 if (old_vector) {
1332 cfg->move_in_progress = 1;
1333 cpumask_copy(cfg->old_domain, cfg->domain);
1334 }
1335 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1336 per_cpu(vector_irq, new_cpu)[vector] = irq;
1337 cfg->vector = vector;
1338 cpumask_copy(cfg->domain, tmp_mask);
1339 err = 0;
1340 break;
1341 }
1342 free_cpumask_var(tmp_mask);
1343 return err;
1344}
1345
1346static int
1347assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1348{
1349 int err;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&vector_lock, flags);
1353 err = __assign_irq_vector(irq, cfg, mask);
1354 spin_unlock_irqrestore(&vector_lock, flags);
1355 return err;
1356}
1357
1358static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1359{
1360 int cpu, vector;
1361
1362 BUG_ON(!cfg->vector);
1363
1364 vector = cfg->vector;
1365 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1366 per_cpu(vector_irq, cpu)[vector] = -1;
1367
1368 cfg->vector = 0;
1369 cpumask_clear(cfg->domain);
1370
1371 if (likely(!cfg->move_in_progress))
1372 return;
1373 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1374 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1375 vector++) {
1376 if (per_cpu(vector_irq, cpu)[vector] != irq)
1377 continue;
1378 per_cpu(vector_irq, cpu)[vector] = -1;
1379 break;
1380 }
1381 }
1382 cfg->move_in_progress = 0;
1383}
1384
1385void __setup_vector_irq(int cpu)
1386{
1387 /* Initialize vector_irq on a new cpu */
1388 /* This function must be called with vector_lock held */
1389 int irq, vector;
1390 struct irq_cfg *cfg;
1391 struct irq_desc *desc;
1392
1393 /* Mark the inuse vectors */
1394 for_each_irq_desc(irq, desc) {
1395 cfg = desc->chip_data;
1396 if (!cpumask_test_cpu(cpu, cfg->domain))
1397 continue;
1398 vector = cfg->vector;
1399 per_cpu(vector_irq, cpu)[vector] = irq;
1400 }
1401 /* Mark the free vectors */
1402 for (vector = 0; vector < NR_VECTORS; ++vector) {
1403 irq = per_cpu(vector_irq, cpu)[vector];
1404 if (irq < 0)
1405 continue;
1406
1407 cfg = irq_cfg(irq);
1408 if (!cpumask_test_cpu(cpu, cfg->domain))
1409 per_cpu(vector_irq, cpu)[vector] = -1;
1410 }
1411}
1412
1413static struct irq_chip ioapic_chip;
1414#ifdef CONFIG_INTR_REMAP
1415static struct irq_chip ir_ioapic_chip;
1416#endif
1417
1418#define IOAPIC_AUTO -1
1419#define IOAPIC_EDGE 0
1420#define IOAPIC_LEVEL 1
1421
1422#ifdef CONFIG_X86_32
1423static inline int IO_APIC_irq_trigger(int irq)
1424{
1425 int apic, idx, pin;
1426
1427 for (apic = 0; apic < nr_ioapics; apic++) {
1428 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1429 idx = find_irq_entry(apic, pin, mp_INT);
1430 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1431 return irq_trigger(idx);
1432 }
1433 }
1434 /*
1435 * nonexistent IRQs are edge default
1436 */
1437 return 0;
1438}
1439#else
1440static inline int IO_APIC_irq_trigger(int irq)
1441{
1442 return 1;
1443}
1444#endif
1445
1446static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1447{
1448
1449 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1450 trigger == IOAPIC_LEVEL)
1451 desc->status |= IRQ_LEVEL;
1452 else
1453 desc->status &= ~IRQ_LEVEL;
1454
1455#ifdef CONFIG_INTR_REMAP
1456 if (irq_remapped(irq)) {
1457 desc->status |= IRQ_MOVE_PCNTXT;
1458 if (trigger)
1459 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1460 handle_fasteoi_irq,
1461 "fasteoi");
1462 else
1463 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1464 handle_edge_irq, "edge");
1465 return;
1466 }
1467#endif
1468 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1469 trigger == IOAPIC_LEVEL)
1470 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1471 handle_fasteoi_irq,
1472 "fasteoi");
1473 else
1474 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1475 handle_edge_irq, "edge");
1476}
1477
1478int setup_ioapic_entry(int apic_id, int irq,
1479 struct IO_APIC_route_entry *entry,
1480 unsigned int destination, int trigger,
1481 int polarity, int vector)
1482{
1483 /*
1484 * add it to the IO-APIC irq-routing table:
1485 */
1486 memset(entry,0,sizeof(*entry));
1487
1488#ifdef CONFIG_INTR_REMAP
1489 if (intr_remapping_enabled) {
1490 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1491 struct irte irte;
1492 struct IR_IO_APIC_route_entry *ir_entry =
1493 (struct IR_IO_APIC_route_entry *) entry;
1494 int index;
1495
1496 if (!iommu)
1497 panic("No mapping iommu for ioapic %d\n", apic_id);
1498
1499 index = alloc_irte(iommu, irq, 1);
1500 if (index < 0)
1501 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1502
1503 memset(&irte, 0, sizeof(irte));
1504
1505 irte.present = 1;
1506 irte.dst_mode = apic->irq_dest_mode;
1507 irte.trigger_mode = trigger;
1508 irte.dlvry_mode = apic->irq_delivery_mode;
1509 irte.vector = vector;
1510 irte.dest_id = IRTE_DEST(destination);
1511
1512 modify_irte(irq, &irte);
1513
1514 ir_entry->index2 = (index >> 15) & 0x1;
1515 ir_entry->zero = 0;
1516 ir_entry->format = 1;
1517 ir_entry->index = (index & 0x7fff);
1518 } else
1519#endif
1520 {
1521 entry->delivery_mode = apic->irq_delivery_mode;
1522 entry->dest_mode = apic->irq_dest_mode;
1523 entry->dest = destination;
1524 }
1525
1526 entry->mask = 0; /* enable IRQ */
1527 entry->trigger = trigger;
1528 entry->polarity = polarity;
1529 entry->vector = vector;
1530
1531 /* Mask level triggered irqs.
1532 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1533 */
1534 if (trigger)
1535 entry->mask = 1;
1536 return 0;
1537}
1538
1539static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1540 int trigger, int polarity)
1541{
1542 struct irq_cfg *cfg;
1543 struct IO_APIC_route_entry entry;
1544 unsigned int dest;
1545
1546 if (!IO_APIC_IRQ(irq))
1547 return;
1548
1549 cfg = desc->chip_data;
1550
1551 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1552 return;
1553
1554 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1555
1556 apic_printk(APIC_VERBOSE,KERN_DEBUG
1557 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1558 "IRQ %d Mode:%i Active:%i)\n",
1559 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1560 irq, trigger, polarity);
1561
1562
1563 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1564 dest, trigger, polarity, cfg->vector)) {
1565 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1566 mp_ioapics[apic_id].apicid, pin);
1567 __clear_irq_vector(irq, cfg);
1568 return;
1569 }
1570
1571 ioapic_register_intr(irq, desc, trigger);
1572 if (irq < NR_IRQS_LEGACY)
1573 disable_8259A_irq(irq);
1574
1575 ioapic_write_entry(apic_id, pin, entry);
1576}
1577
1578static void __init setup_IO_APIC_irqs(void)
1579{
1580 int apic_id, pin, idx, irq;
1581 int notcon = 0;
1582 struct irq_desc *desc;
1583 struct irq_cfg *cfg;
1584 int cpu = boot_cpu_id;
1585
1586 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1587
1588 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1589 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1590
1591 idx = find_irq_entry(apic_id, pin, mp_INT);
1592 if (idx == -1) {
1593 if (!notcon) {
1594 notcon = 1;
1595 apic_printk(APIC_VERBOSE,
1596 KERN_DEBUG " %d-%d",
1597 mp_ioapics[apic_id].apicid, pin);
1598 } else
1599 apic_printk(APIC_VERBOSE, " %d-%d",
1600 mp_ioapics[apic_id].apicid, pin);
1601 continue;
1602 }
1603 if (notcon) {
1604 apic_printk(APIC_VERBOSE,
1605 " (apicid-pin) not connected\n");
1606 notcon = 0;
1607 }
1608
1609 irq = pin_2_irq(idx, apic_id, pin);
1610
1611 /*
1612 * Skip the timer IRQ if there's a quirk handler
1613 * installed and if it returns 1:
1614 */
1615 if (apic->multi_timer_check &&
1616 apic->multi_timer_check(apic_id, irq))
1617 continue;
1618
1619 desc = irq_to_desc_alloc_cpu(irq, cpu);
1620 if (!desc) {
1621 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1622 continue;
1623 }
1624 cfg = desc->chip_data;
1625 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1626
1627 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1628 irq_trigger(idx), irq_polarity(idx));
1629 }
1630 }
1631
1632 if (notcon)
1633 apic_printk(APIC_VERBOSE,
1634 " (apicid-pin) not connected\n");
1635}
1636
1637/*
1638 * Set up the timer pin, possibly with the 8259A-master behind.
1639 */
1640static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1641 int vector)
1642{
1643 struct IO_APIC_route_entry entry;
1644
1645#ifdef CONFIG_INTR_REMAP
1646 if (intr_remapping_enabled)
1647 return;
1648#endif
1649
1650 memset(&entry, 0, sizeof(entry));
1651
1652 /*
1653 * We use logical delivery to get the timer IRQ
1654 * to the first CPU.
1655 */
1656 entry.dest_mode = apic->irq_dest_mode;
1657 entry.mask = 0; /* don't mask IRQ for edge */
1658 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1659 entry.delivery_mode = apic->irq_delivery_mode;
1660 entry.polarity = 0;
1661 entry.trigger = 0;
1662 entry.vector = vector;
1663
1664 /*
1665 * The timer IRQ doesn't have to know that behind the
1666 * scene we may have a 8259A-master in AEOI mode ...
1667 */
1668 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1669
1670 /*
1671 * Add it to the IO-APIC irq-routing table:
1672 */
1673 ioapic_write_entry(apic_id, pin, entry);
1674}
1675
1676
1677__apicdebuginit(void) print_IO_APIC(void)
1678{
1679 int apic, i;
1680 union IO_APIC_reg_00 reg_00;
1681 union IO_APIC_reg_01 reg_01;
1682 union IO_APIC_reg_02 reg_02;
1683 union IO_APIC_reg_03 reg_03;
1684 unsigned long flags;
1685 struct irq_cfg *cfg;
1686 struct irq_desc *desc;
1687 unsigned int irq;
1688
1689 if (apic_verbosity == APIC_QUIET)
1690 return;
1691
1692 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1693 for (i = 0; i < nr_ioapics; i++)
1694 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1695 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1696
1697 /*
1698 * We are a bit conservative about what we expect. We have to
1699 * know about every hardware change ASAP.
1700 */
1701 printk(KERN_INFO "testing the IO APIC.......................\n");
1702
1703 for (apic = 0; apic < nr_ioapics; apic++) {
1704
1705 spin_lock_irqsave(&ioapic_lock, flags);
1706 reg_00.raw = io_apic_read(apic, 0);
1707 reg_01.raw = io_apic_read(apic, 1);
1708 if (reg_01.bits.version >= 0x10)
1709 reg_02.raw = io_apic_read(apic, 2);
1710 if (reg_01.bits.version >= 0x20)
1711 reg_03.raw = io_apic_read(apic, 3);
1712 spin_unlock_irqrestore(&ioapic_lock, flags);
1713
1714 printk("\n");
1715 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1716 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1717 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1718 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1719 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1720
1721 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1722 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1723
1724 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1725 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1726
1727 /*
1728 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1729 * but the value of reg_02 is read as the previous read register
1730 * value, so ignore it if reg_02 == reg_01.
1731 */
1732 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1733 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1734 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1735 }
1736
1737 /*
1738 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1739 * or reg_03, but the value of reg_0[23] is read as the previous read
1740 * register value, so ignore it if reg_03 == reg_0[12].
1741 */
1742 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1743 reg_03.raw != reg_01.raw) {
1744 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1745 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1746 }
1747
1748 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1749
1750 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1751 " Stat Dmod Deli Vect: \n");
1752
1753 for (i = 0; i <= reg_01.bits.entries; i++) {
1754 struct IO_APIC_route_entry entry;
1755
1756 entry = ioapic_read_entry(apic, i);
1757
1758 printk(KERN_DEBUG " %02x %03X ",
1759 i,
1760 entry.dest
1761 );
1762
1763 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1764 entry.mask,
1765 entry.trigger,
1766 entry.irr,
1767 entry.polarity,
1768 entry.delivery_status,
1769 entry.dest_mode,
1770 entry.delivery_mode,
1771 entry.vector
1772 );
1773 }
1774 }
1775 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1776 for_each_irq_desc(irq, desc) {
1777 struct irq_pin_list *entry;
1778
1779 cfg = desc->chip_data;
1780 entry = cfg->irq_2_pin;
1781 if (!entry)
1782 continue;
1783 printk(KERN_DEBUG "IRQ%d ", irq);
1784 for (;;) {
1785 printk("-> %d:%d", entry->apic, entry->pin);
1786 if (!entry->next)
1787 break;
1788 entry = entry->next;
1789 }
1790 printk("\n");
1791 }
1792
1793 printk(KERN_INFO ".................................... done.\n");
1794
1795 return;
1796}
1797
1798__apicdebuginit(void) print_APIC_bitfield(int base)
1799{
1800 unsigned int v;
1801 int i, j;
1802
1803 if (apic_verbosity == APIC_QUIET)
1804 return;
1805
1806 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1807 for (i = 0; i < 8; i++) {
1808 v = apic_read(base + i*0x10);
1809 for (j = 0; j < 32; j++) {
1810 if (v & (1<<j))
1811 printk("1");
1812 else
1813 printk("0");
1814 }
1815 printk("\n");
1816 }
1817}
1818
1819__apicdebuginit(void) print_local_APIC(void *dummy)
1820{
1821 unsigned int v, ver, maxlvt;
1822 u64 icr;
1823
1824 if (apic_verbosity == APIC_QUIET)
1825 return;
1826
1827 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1828 smp_processor_id(), hard_smp_processor_id());
1829 v = apic_read(APIC_ID);
1830 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1831 v = apic_read(APIC_LVR);
1832 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1833 ver = GET_APIC_VERSION(v);
1834 maxlvt = lapic_get_maxlvt();
1835
1836 v = apic_read(APIC_TASKPRI);
1837 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1838
1839 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1840 if (!APIC_XAPIC(ver)) {
1841 v = apic_read(APIC_ARBPRI);
1842 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1843 v & APIC_ARBPRI_MASK);
1844 }
1845 v = apic_read(APIC_PROCPRI);
1846 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1847 }
1848
1849 /*
1850 * Remote read supported only in the 82489DX and local APIC for
1851 * Pentium processors.
1852 */
1853 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1854 v = apic_read(APIC_RRR);
1855 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1856 }
1857
1858 v = apic_read(APIC_LDR);
1859 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1860 if (!x2apic_enabled()) {
1861 v = apic_read(APIC_DFR);
1862 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1863 }
1864 v = apic_read(APIC_SPIV);
1865 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1866
1867 printk(KERN_DEBUG "... APIC ISR field:\n");
1868 print_APIC_bitfield(APIC_ISR);
1869 printk(KERN_DEBUG "... APIC TMR field:\n");
1870 print_APIC_bitfield(APIC_TMR);
1871 printk(KERN_DEBUG "... APIC IRR field:\n");
1872 print_APIC_bitfield(APIC_IRR);
1873
1874 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1875 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1876 apic_write(APIC_ESR, 0);
1877
1878 v = apic_read(APIC_ESR);
1879 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1880 }
1881
1882 icr = apic_icr_read();
1883 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1884 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1885
1886 v = apic_read(APIC_LVTT);
1887 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1888
1889 if (maxlvt > 3) { /* PC is LVT#4. */
1890 v = apic_read(APIC_LVTPC);
1891 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1892 }
1893 v = apic_read(APIC_LVT0);
1894 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1895 v = apic_read(APIC_LVT1);
1896 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1897
1898 if (maxlvt > 2) { /* ERR is LVT#3. */
1899 v = apic_read(APIC_LVTERR);
1900 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1901 }
1902
1903 v = apic_read(APIC_TMICT);
1904 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1905 v = apic_read(APIC_TMCCT);
1906 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1907 v = apic_read(APIC_TDCR);
1908 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1909 printk("\n");
1910}
1911
1912__apicdebuginit(void) print_all_local_APICs(void)
1913{
1914 int cpu;
1915
1916 preempt_disable();
1917 for_each_online_cpu(cpu)
1918 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1919 preempt_enable();
1920}
1921
1922__apicdebuginit(void) print_PIC(void)
1923{
1924 unsigned int v;
1925 unsigned long flags;
1926
1927 if (apic_verbosity == APIC_QUIET)
1928 return;
1929
1930 printk(KERN_DEBUG "\nprinting PIC contents\n");
1931
1932 spin_lock_irqsave(&i8259A_lock, flags);
1933
1934 v = inb(0xa1) << 8 | inb(0x21);
1935 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1936
1937 v = inb(0xa0) << 8 | inb(0x20);
1938 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1939
1940 outb(0x0b,0xa0);
1941 outb(0x0b,0x20);
1942 v = inb(0xa0) << 8 | inb(0x20);
1943 outb(0x0a,0xa0);
1944 outb(0x0a,0x20);
1945
1946 spin_unlock_irqrestore(&i8259A_lock, flags);
1947
1948 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1949
1950 v = inb(0x4d1) << 8 | inb(0x4d0);
1951 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1952}
1953
1954__apicdebuginit(int) print_all_ICs(void)
1955{
1956 print_PIC();
1957 print_all_local_APICs();
1958 print_IO_APIC();
1959
1960 return 0;
1961}
1962
1963fs_initcall(print_all_ICs);
1964
1965
1966/* Where if anywhere is the i8259 connect in external int mode */
1967static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1968
1969void __init enable_IO_APIC(void)
1970{
1971 union IO_APIC_reg_01 reg_01;
1972 int i8259_apic, i8259_pin;
1973 int apic;
1974 unsigned long flags;
1975
1976 /*
1977 * The number of IO-APIC IRQ registers (== #pins):
1978 */
1979 for (apic = 0; apic < nr_ioapics; apic++) {
1980 spin_lock_irqsave(&ioapic_lock, flags);
1981 reg_01.raw = io_apic_read(apic, 1);
1982 spin_unlock_irqrestore(&ioapic_lock, flags);
1983 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1984 }
1985 for(apic = 0; apic < nr_ioapics; apic++) {
1986 int pin;
1987 /* See if any of the pins is in ExtINT mode */
1988 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1989 struct IO_APIC_route_entry entry;
1990 entry = ioapic_read_entry(apic, pin);
1991
1992 /* If the interrupt line is enabled and in ExtInt mode
1993 * I have found the pin where the i8259 is connected.
1994 */
1995 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1996 ioapic_i8259.apic = apic;
1997 ioapic_i8259.pin = pin;
1998 goto found_i8259;
1999 }
2000 }
2001 }
2002 found_i8259:
2003 /* Look to see what if the MP table has reported the ExtINT */
2004 /* If we could not find the appropriate pin by looking at the ioapic
2005 * the i8259 probably is not connected the ioapic but give the
2006 * mptable a chance anyway.
2007 */
2008 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2009 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2010 /* Trust the MP table if nothing is setup in the hardware */
2011 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2012 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2013 ioapic_i8259.pin = i8259_pin;
2014 ioapic_i8259.apic = i8259_apic;
2015 }
2016 /* Complain if the MP table and the hardware disagree */
2017 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2018 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2019 {
2020 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2021 }
2022
2023 /*
2024 * Do not trust the IO-APIC being empty at bootup
2025 */
2026 clear_IO_APIC();
2027}
2028
2029/*
2030 * Not an __init, needed by the reboot code
2031 */
2032void disable_IO_APIC(void)
2033{
2034 /*
2035 * Clear the IO-APIC before rebooting:
2036 */
2037 clear_IO_APIC();
2038
2039 /*
2040 * If the i8259 is routed through an IOAPIC
2041 * Put that IOAPIC in virtual wire mode
2042 * so legacy interrupts can be delivered.
2043 */
2044 if (ioapic_i8259.pin != -1) {
2045 struct IO_APIC_route_entry entry;
2046
2047 memset(&entry, 0, sizeof(entry));
2048 entry.mask = 0; /* Enabled */
2049 entry.trigger = 0; /* Edge */
2050 entry.irr = 0;
2051 entry.polarity = 0; /* High */
2052 entry.delivery_status = 0;
2053 entry.dest_mode = 0; /* Physical */
2054 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2055 entry.vector = 0;
2056 entry.dest = read_apic_id();
2057
2058 /*
2059 * Add it to the IO-APIC irq-routing table:
2060 */
2061 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2062 }
2063
2064 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2065}
2066
2067#ifdef CONFIG_X86_32
2068/*
2069 * function to set the IO-APIC physical IDs based on the
2070 * values stored in the MPC table.
2071 *
2072 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2073 */
2074
2075static void __init setup_ioapic_ids_from_mpc(void)
2076{
2077 union IO_APIC_reg_00 reg_00;
2078 physid_mask_t phys_id_present_map;
2079 int apic_id;
2080 int i;
2081 unsigned char old_id;
2082 unsigned long flags;
2083
2084 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2085 return;
2086
2087 /*
2088 * Don't check I/O APIC IDs for xAPIC systems. They have
2089 * no meaning without the serial APIC bus.
2090 */
2091 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2092 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2093 return;
2094 /*
2095 * This is broken; anything with a real cpu count has to
2096 * circumvent this idiocy regardless.
2097 */
2098 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2099
2100 /*
2101 * Set the IOAPIC ID to the value stored in the MPC table.
2102 */
2103 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2104
2105 /* Read the register 0 value */
2106 spin_lock_irqsave(&ioapic_lock, flags);
2107 reg_00.raw = io_apic_read(apic_id, 0);
2108 spin_unlock_irqrestore(&ioapic_lock, flags);
2109
2110 old_id = mp_ioapics[apic_id].apicid;
2111
2112 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2113 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2114 apic_id, mp_ioapics[apic_id].apicid);
2115 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2116 reg_00.bits.ID);
2117 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2118 }
2119
2120 /*
2121 * Sanity check, is the ID really free? Every APIC in a
2122 * system must have a unique ID or we get lots of nice
2123 * 'stuck on smp_invalidate_needed IPI wait' messages.
2124 */
2125 if (apic->check_apicid_used(phys_id_present_map,
2126 mp_ioapics[apic_id].apicid)) {
2127 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2128 apic_id, mp_ioapics[apic_id].apicid);
2129 for (i = 0; i < get_physical_broadcast(); i++)
2130 if (!physid_isset(i, phys_id_present_map))
2131 break;
2132 if (i >= get_physical_broadcast())
2133 panic("Max APIC ID exceeded!\n");
2134 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2135 i);
2136 physid_set(i, phys_id_present_map);
2137 mp_ioapics[apic_id].apicid = i;
2138 } else {
2139 physid_mask_t tmp;
2140 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2141 apic_printk(APIC_VERBOSE, "Setting %d in the "
2142 "phys_id_present_map\n",
2143 mp_ioapics[apic_id].apicid);
2144 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2145 }
2146
2147
2148 /*
2149 * We need to adjust the IRQ routing table
2150 * if the ID changed.
2151 */
2152 if (old_id != mp_ioapics[apic_id].apicid)
2153 for (i = 0; i < mp_irq_entries; i++)
2154 if (mp_irqs[i].dstapic == old_id)
2155 mp_irqs[i].dstapic
2156 = mp_ioapics[apic_id].apicid;
2157
2158 /*
2159 * Read the right value from the MPC table and
2160 * write it into the ID register.
2161 */
2162 apic_printk(APIC_VERBOSE, KERN_INFO
2163 "...changing IO-APIC physical APIC ID to %d ...",
2164 mp_ioapics[apic_id].apicid);
2165
2166 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2167 spin_lock_irqsave(&ioapic_lock, flags);
2168 io_apic_write(apic_id, 0, reg_00.raw);
2169 spin_unlock_irqrestore(&ioapic_lock, flags);
2170
2171 /*
2172 * Sanity check
2173 */
2174 spin_lock_irqsave(&ioapic_lock, flags);
2175 reg_00.raw = io_apic_read(apic_id, 0);
2176 spin_unlock_irqrestore(&ioapic_lock, flags);
2177 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2178 printk("could not set ID!\n");
2179 else
2180 apic_printk(APIC_VERBOSE, " ok.\n");
2181 }
2182}
2183#endif
2184
2185int no_timer_check __initdata;
2186
2187static int __init notimercheck(char *s)
2188{
2189 no_timer_check = 1;
2190 return 1;
2191}
2192__setup("no_timer_check", notimercheck);
2193
2194/*
2195 * There is a nasty bug in some older SMP boards, their mptable lies
2196 * about the timer IRQ. We do the following to work around the situation:
2197 *
2198 * - timer IRQ defaults to IO-APIC IRQ
2199 * - if this function detects that timer IRQs are defunct, then we fall
2200 * back to ISA timer IRQs
2201 */
2202static int __init timer_irq_works(void)
2203{
2204 unsigned long t1 = jiffies;
2205 unsigned long flags;
2206
2207 if (no_timer_check)
2208 return 1;
2209
2210 local_save_flags(flags);
2211 local_irq_enable();
2212 /* Let ten ticks pass... */
2213 mdelay((10 * 1000) / HZ);
2214 local_irq_restore(flags);
2215
2216 /*
2217 * Expect a few ticks at least, to be sure some possible
2218 * glue logic does not lock up after one or two first
2219 * ticks in a non-ExtINT mode. Also the local APIC
2220 * might have cached one ExtINT interrupt. Finally, at
2221 * least one tick may be lost due to delays.
2222 */
2223
2224 /* jiffies wrap? */
2225 if (time_after(jiffies, t1 + 4))
2226 return 1;
2227 return 0;
2228}
2229
2230/*
2231 * In the SMP+IOAPIC case it might happen that there are an unspecified
2232 * number of pending IRQ events unhandled. These cases are very rare,
2233 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2234 * better to do it this way as thus we do not have to be aware of
2235 * 'pending' interrupts in the IRQ path, except at this point.
2236 */
2237/*
2238 * Edge triggered needs to resend any interrupt
2239 * that was delayed but this is now handled in the device
2240 * independent code.
2241 */
2242
2243/*
2244 * Starting up a edge-triggered IO-APIC interrupt is
2245 * nasty - we need to make sure that we get the edge.
2246 * If it is already asserted for some reason, we need
2247 * return 1 to indicate that is was pending.
2248 *
2249 * This is not complete - we should be able to fake
2250 * an edge even if it isn't on the 8259A...
2251 */
2252
2253static unsigned int startup_ioapic_irq(unsigned int irq)
2254{
2255 int was_pending = 0;
2256 unsigned long flags;
2257 struct irq_cfg *cfg;
2258
2259 spin_lock_irqsave(&ioapic_lock, flags);
2260 if (irq < NR_IRQS_LEGACY) {
2261 disable_8259A_irq(irq);
2262 if (i8259A_irq_pending(irq))
2263 was_pending = 1;
2264 }
2265 cfg = irq_cfg(irq);
2266 __unmask_IO_APIC_irq(cfg);
2267 spin_unlock_irqrestore(&ioapic_lock, flags);
2268
2269 return was_pending;
2270}
2271
2272#ifdef CONFIG_X86_64
2273static int ioapic_retrigger_irq(unsigned int irq)
2274{
2275
2276 struct irq_cfg *cfg = irq_cfg(irq);
2277 unsigned long flags;
2278
2279 spin_lock_irqsave(&vector_lock, flags);
2280 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2281 spin_unlock_irqrestore(&vector_lock, flags);
2282
2283 return 1;
2284}
2285#else
2286static int ioapic_retrigger_irq(unsigned int irq)
2287{
2288 apic->send_IPI_self(irq_cfg(irq)->vector);
2289
2290 return 1;
2291}
2292#endif
2293
2294/*
2295 * Level and edge triggered IO-APIC interrupts need different handling,
2296 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2297 * handled with the level-triggered descriptor, but that one has slightly
2298 * more overhead. Level-triggered interrupts cannot be handled with the
2299 * edge-triggered handler, without risking IRQ storms and other ugly
2300 * races.
2301 */
2302
2303#ifdef CONFIG_SMP
2304
2305#ifdef CONFIG_INTR_REMAP
2306static void ir_irq_migration(struct work_struct *work);
2307
2308static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2309
2310/*
2311 * Migrate the IO-APIC irq in the presence of intr-remapping.
2312 *
2313 * For edge triggered, irq migration is a simple atomic update(of vector
2314 * and cpu destination) of IRTE and flush the hardware cache.
2315 *
2316 * For level triggered, we need to modify the io-apic RTE aswell with the update
2317 * vector information, along with modifying IRTE with vector and destination.
2318 * So irq migration for level triggered is little bit more complex compared to
2319 * edge triggered migration. But the good news is, we use the same algorithm
2320 * for level triggered migration as we have today, only difference being,
2321 * we now initiate the irq migration from process context instead of the
2322 * interrupt context.
2323 *
2324 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2325 * suppression) to the IO-APIC, level triggered irq migration will also be
2326 * as simple as edge triggered migration and we can do the irq migration
2327 * with a simple atomic update to IO-APIC RTE.
2328 */
2329static void
2330migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2331{
2332 struct irq_cfg *cfg;
2333 struct irte irte;
2334 int modify_ioapic_rte;
2335 unsigned int dest;
2336 unsigned long flags;
2337 unsigned int irq;
2338
2339 if (!cpumask_intersects(mask, cpu_online_mask))
2340 return;
2341
2342 irq = desc->irq;
2343 if (get_irte(irq, &irte))
2344 return;
2345
2346 cfg = desc->chip_data;
2347 if (assign_irq_vector(irq, cfg, mask))
2348 return;
2349
2350 set_extra_move_desc(desc, mask);
2351
2352 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2353
2354 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2355 if (modify_ioapic_rte) {
2356 spin_lock_irqsave(&ioapic_lock, flags);
2357 __target_IO_APIC_irq(irq, dest, cfg);
2358 spin_unlock_irqrestore(&ioapic_lock, flags);
2359 }
2360
2361 irte.vector = cfg->vector;
2362 irte.dest_id = IRTE_DEST(dest);
2363
2364 /*
2365 * Modified the IRTE and flushes the Interrupt entry cache.
2366 */
2367 modify_irte(irq, &irte);
2368
2369 if (cfg->move_in_progress)
2370 send_cleanup_vector(cfg);
2371
2372 cpumask_copy(desc->affinity, mask);
2373}
2374
2375static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2376{
2377 int ret = -1;
2378 struct irq_cfg *cfg = desc->chip_data;
2379
2380 mask_IO_APIC_irq_desc(desc);
2381
2382 if (io_apic_level_ack_pending(cfg)) {
2383 /*
2384 * Interrupt in progress. Migrating irq now will change the
2385 * vector information in the IO-APIC RTE and that will confuse
2386 * the EOI broadcast performed by cpu.
2387 * So, delay the irq migration to the next instance.
2388 */
2389 schedule_delayed_work(&ir_migration_work, 1);
2390 goto unmask;
2391 }
2392
2393 /* everthing is clear. we have right of way */
2394 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2395
2396 ret = 0;
2397 desc->status &= ~IRQ_MOVE_PENDING;
2398 cpumask_clear(desc->pending_mask);
2399
2400unmask:
2401 unmask_IO_APIC_irq_desc(desc);
2402
2403 return ret;
2404}
2405
2406static void ir_irq_migration(struct work_struct *work)
2407{
2408 unsigned int irq;
2409 struct irq_desc *desc;
2410
2411 for_each_irq_desc(irq, desc) {
2412 if (desc->status & IRQ_MOVE_PENDING) {
2413 unsigned long flags;
2414
2415 spin_lock_irqsave(&desc->lock, flags);
2416 if (!desc->chip->set_affinity ||
2417 !(desc->status & IRQ_MOVE_PENDING)) {
2418 desc->status &= ~IRQ_MOVE_PENDING;
2419 spin_unlock_irqrestore(&desc->lock, flags);
2420 continue;
2421 }
2422
2423 desc->chip->set_affinity(irq, desc->pending_mask);
2424 spin_unlock_irqrestore(&desc->lock, flags);
2425 }
2426 }
2427}
2428
2429/*
2430 * Migrates the IRQ destination in the process context.
2431 */
2432static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2433 const struct cpumask *mask)
2434{
2435 if (desc->status & IRQ_LEVEL) {
2436 desc->status |= IRQ_MOVE_PENDING;
2437 cpumask_copy(desc->pending_mask, mask);
2438 migrate_irq_remapped_level_desc(desc);
2439 return;
2440 }
2441
2442 migrate_ioapic_irq_desc(desc, mask);
2443}
2444static void set_ir_ioapic_affinity_irq(unsigned int irq,
2445 const struct cpumask *mask)
2446{
2447 struct irq_desc *desc = irq_to_desc(irq);
2448
2449 set_ir_ioapic_affinity_irq_desc(desc, mask);
2450}
2451#endif
2452
2453asmlinkage void smp_irq_move_cleanup_interrupt(void)
2454{
2455 unsigned vector, me;
2456
2457 ack_APIC_irq();
2458 exit_idle();
2459 irq_enter();
2460
2461 me = smp_processor_id();
2462 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2463 unsigned int irq;
2464 struct irq_desc *desc;
2465 struct irq_cfg *cfg;
2466 irq = __get_cpu_var(vector_irq)[vector];
2467
2468 if (irq == -1)
2469 continue;
2470
2471 desc = irq_to_desc(irq);
2472 if (!desc)
2473 continue;
2474
2475 cfg = irq_cfg(irq);
2476 spin_lock(&desc->lock);
2477 if (!cfg->move_cleanup_count)
2478 goto unlock;
2479
2480 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2481 goto unlock;
2482
2483 __get_cpu_var(vector_irq)[vector] = -1;
2484 cfg->move_cleanup_count--;
2485unlock:
2486 spin_unlock(&desc->lock);
2487 }
2488
2489 irq_exit();
2490}
2491
2492static void irq_complete_move(struct irq_desc **descp)
2493{
2494 struct irq_desc *desc = *descp;
2495 struct irq_cfg *cfg = desc->chip_data;
2496 unsigned vector, me;
2497
2498 if (likely(!cfg->move_in_progress)) {
2499#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2500 if (likely(!cfg->move_desc_pending))
2501 return;
2502
2503 /* domain has not changed, but affinity did */
2504 me = smp_processor_id();
2505 if (cpumask_test_cpu(me, desc->affinity)) {
2506 *descp = desc = move_irq_desc(desc, me);
2507 /* get the new one */
2508 cfg = desc->chip_data;
2509 cfg->move_desc_pending = 0;
2510 }
2511#endif
2512 return;
2513 }
2514
2515 vector = ~get_irq_regs()->orig_ax;
2516 me = smp_processor_id();
2517
2518 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2519#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2520 *descp = desc = move_irq_desc(desc, me);
2521 /* get the new one */
2522 cfg = desc->chip_data;
2523#endif
2524 send_cleanup_vector(cfg);
2525 }
2526}
2527#else
2528static inline void irq_complete_move(struct irq_desc **descp) {}
2529#endif
2530
2531#ifdef CONFIG_INTR_REMAP
2532static void ack_x2apic_level(unsigned int irq)
2533{
2534 ack_x2APIC_irq();
2535}
2536
2537static void ack_x2apic_edge(unsigned int irq)
2538{
2539 ack_x2APIC_irq();
2540}
2541
2542#endif
2543
2544static void ack_apic_edge(unsigned int irq)
2545{
2546 struct irq_desc *desc = irq_to_desc(irq);
2547
2548 irq_complete_move(&desc);
2549 move_native_irq(irq);
2550 ack_APIC_irq();
2551}
2552
2553atomic_t irq_mis_count;
2554
2555static void ack_apic_level(unsigned int irq)
2556{
2557 struct irq_desc *desc = irq_to_desc(irq);
2558
2559#ifdef CONFIG_X86_32
2560 unsigned long v;
2561 int i;
2562#endif
2563 struct irq_cfg *cfg;
2564 int do_unmask_irq = 0;
2565
2566 irq_complete_move(&desc);
2567#ifdef CONFIG_GENERIC_PENDING_IRQ
2568 /* If we are moving the irq we need to mask it */
2569 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2570 do_unmask_irq = 1;
2571 mask_IO_APIC_irq_desc(desc);
2572 }
2573#endif
2574
2575#ifdef CONFIG_X86_32
2576 /*
2577 * It appears there is an erratum which affects at least version 0x11
2578 * of I/O APIC (that's the 82093AA and cores integrated into various
2579 * chipsets). Under certain conditions a level-triggered interrupt is
2580 * erroneously delivered as edge-triggered one but the respective IRR
2581 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2582 * message but it will never arrive and further interrupts are blocked
2583 * from the source. The exact reason is so far unknown, but the
2584 * phenomenon was observed when two consecutive interrupt requests
2585 * from a given source get delivered to the same CPU and the source is
2586 * temporarily disabled in between.
2587 *
2588 * A workaround is to simulate an EOI message manually. We achieve it
2589 * by setting the trigger mode to edge and then to level when the edge
2590 * trigger mode gets detected in the TMR of a local APIC for a
2591 * level-triggered interrupt. We mask the source for the time of the
2592 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2593 * The idea is from Manfred Spraul. --macro
2594 */
2595 cfg = desc->chip_data;
2596 i = cfg->vector;
2597
2598 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2599#endif
2600
2601 /*
2602 * We must acknowledge the irq before we move it or the acknowledge will
2603 * not propagate properly.
2604 */
2605 ack_APIC_irq();
2606
2607 /* Now we can move and renable the irq */
2608 if (unlikely(do_unmask_irq)) {
2609 /* Only migrate the irq if the ack has been received.
2610 *
2611 * On rare occasions the broadcast level triggered ack gets
2612 * delayed going to ioapics, and if we reprogram the
2613 * vector while Remote IRR is still set the irq will never
2614 * fire again.
2615 *
2616 * To prevent this scenario we read the Remote IRR bit
2617 * of the ioapic. This has two effects.
2618 * - On any sane system the read of the ioapic will
2619 * flush writes (and acks) going to the ioapic from
2620 * this cpu.
2621 * - We get to see if the ACK has actually been delivered.
2622 *
2623 * Based on failed experiments of reprogramming the
2624 * ioapic entry from outside of irq context starting
2625 * with masking the ioapic entry and then polling until
2626 * Remote IRR was clear before reprogramming the
2627 * ioapic I don't trust the Remote IRR bit to be
2628 * completey accurate.
2629 *
2630 * However there appears to be no other way to plug
2631 * this race, so if the Remote IRR bit is not
2632 * accurate and is causing problems then it is a hardware bug
2633 * and you can go talk to the chipset vendor about it.
2634 */
2635 cfg = desc->chip_data;
2636 if (!io_apic_level_ack_pending(cfg))
2637 move_masked_irq(irq);
2638 unmask_IO_APIC_irq_desc(desc);
2639 }
2640
2641#ifdef CONFIG_X86_32
2642 if (!(v & (1 << (i & 0x1f)))) {
2643 atomic_inc(&irq_mis_count);
2644 spin_lock(&ioapic_lock);
2645 __mask_and_edge_IO_APIC_irq(cfg);
2646 __unmask_and_level_IO_APIC_irq(cfg);
2647 spin_unlock(&ioapic_lock);
2648 }
2649#endif
2650}
2651
2652static struct irq_chip ioapic_chip __read_mostly = {
2653 .name = "IO-APIC",
2654 .startup = startup_ioapic_irq,
2655 .mask = mask_IO_APIC_irq,
2656 .unmask = unmask_IO_APIC_irq,
2657 .ack = ack_apic_edge,
2658 .eoi = ack_apic_level,
2659#ifdef CONFIG_SMP
2660 .set_affinity = set_ioapic_affinity_irq,
2661#endif
2662 .retrigger = ioapic_retrigger_irq,
2663};
2664
2665#ifdef CONFIG_INTR_REMAP
2666static struct irq_chip ir_ioapic_chip __read_mostly = {
2667 .name = "IR-IO-APIC",
2668 .startup = startup_ioapic_irq,
2669 .mask = mask_IO_APIC_irq,
2670 .unmask = unmask_IO_APIC_irq,
2671 .ack = ack_x2apic_edge,
2672 .eoi = ack_x2apic_level,
2673#ifdef CONFIG_SMP
2674 .set_affinity = set_ir_ioapic_affinity_irq,
2675#endif
2676 .retrigger = ioapic_retrigger_irq,
2677};
2678#endif
2679
2680static inline void init_IO_APIC_traps(void)
2681{
2682 int irq;
2683 struct irq_desc *desc;
2684 struct irq_cfg *cfg;
2685
2686 /*
2687 * NOTE! The local APIC isn't very good at handling
2688 * multiple interrupts at the same interrupt level.
2689 * As the interrupt level is determined by taking the
2690 * vector number and shifting that right by 4, we
2691 * want to spread these out a bit so that they don't
2692 * all fall in the same interrupt level.
2693 *
2694 * Also, we've got to be careful not to trash gate
2695 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2696 */
2697 for_each_irq_desc(irq, desc) {
2698 cfg = desc->chip_data;
2699 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2700 /*
2701 * Hmm.. We don't have an entry for this,
2702 * so default to an old-fashioned 8259
2703 * interrupt if we can..
2704 */
2705 if (irq < NR_IRQS_LEGACY)
2706 make_8259A_irq(irq);
2707 else
2708 /* Strange. Oh, well.. */
2709 desc->chip = &no_irq_chip;
2710 }
2711 }
2712}
2713
2714/*
2715 * The local APIC irq-chip implementation:
2716 */
2717
2718static void mask_lapic_irq(unsigned int irq)
2719{
2720 unsigned long v;
2721
2722 v = apic_read(APIC_LVT0);
2723 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2724}
2725
2726static void unmask_lapic_irq(unsigned int irq)
2727{
2728 unsigned long v;
2729
2730 v = apic_read(APIC_LVT0);
2731 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2732}
2733
2734static void ack_lapic_irq(unsigned int irq)
2735{
2736 ack_APIC_irq();
2737}
2738
2739static struct irq_chip lapic_chip __read_mostly = {
2740 .name = "local-APIC",
2741 .mask = mask_lapic_irq,
2742 .unmask = unmask_lapic_irq,
2743 .ack = ack_lapic_irq,
2744};
2745
2746static void lapic_register_intr(int irq, struct irq_desc *desc)
2747{
2748 desc->status &= ~IRQ_LEVEL;
2749 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2750 "edge");
2751}
2752
2753static void __init setup_nmi(void)
2754{
2755 /*
2756 * Dirty trick to enable the NMI watchdog ...
2757 * We put the 8259A master into AEOI mode and
2758 * unmask on all local APICs LVT0 as NMI.
2759 *
2760 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2761 * is from Maciej W. Rozycki - so we do not have to EOI from
2762 * the NMI handler or the timer interrupt.
2763 */
2764 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2765
2766 enable_NMI_through_LVT0();
2767
2768 apic_printk(APIC_VERBOSE, " done.\n");
2769}
2770
2771/*
2772 * This looks a bit hackish but it's about the only one way of sending
2773 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2774 * not support the ExtINT mode, unfortunately. We need to send these
2775 * cycles as some i82489DX-based boards have glue logic that keeps the
2776 * 8259A interrupt line asserted until INTA. --macro
2777 */
2778static inline void __init unlock_ExtINT_logic(void)
2779{
2780 int apic, pin, i;
2781 struct IO_APIC_route_entry entry0, entry1;
2782 unsigned char save_control, save_freq_select;
2783
2784 pin = find_isa_irq_pin(8, mp_INT);
2785 if (pin == -1) {
2786 WARN_ON_ONCE(1);
2787 return;
2788 }
2789 apic = find_isa_irq_apic(8, mp_INT);
2790 if (apic == -1) {
2791 WARN_ON_ONCE(1);
2792 return;
2793 }
2794
2795 entry0 = ioapic_read_entry(apic, pin);
2796 clear_IO_APIC_pin(apic, pin);
2797
2798 memset(&entry1, 0, sizeof(entry1));
2799
2800 entry1.dest_mode = 0; /* physical delivery */
2801 entry1.mask = 0; /* unmask IRQ now */
2802 entry1.dest = hard_smp_processor_id();
2803 entry1.delivery_mode = dest_ExtINT;
2804 entry1.polarity = entry0.polarity;
2805 entry1.trigger = 0;
2806 entry1.vector = 0;
2807
2808 ioapic_write_entry(apic, pin, entry1);
2809
2810 save_control = CMOS_READ(RTC_CONTROL);
2811 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2812 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2813 RTC_FREQ_SELECT);
2814 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2815
2816 i = 100;
2817 while (i-- > 0) {
2818 mdelay(10);
2819 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2820 i -= 10;
2821 }
2822
2823 CMOS_WRITE(save_control, RTC_CONTROL);
2824 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2825 clear_IO_APIC_pin(apic, pin);
2826
2827 ioapic_write_entry(apic, pin, entry0);
2828}
2829
2830static int disable_timer_pin_1 __initdata;
2831/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2832static int __init disable_timer_pin_setup(char *arg)
2833{
2834 disable_timer_pin_1 = 1;
2835 return 0;
2836}
2837early_param("disable_timer_pin_1", disable_timer_pin_setup);
2838
2839int timer_through_8259 __initdata;
2840
2841/*
2842 * This code may look a bit paranoid, but it's supposed to cooperate with
2843 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2844 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2845 * fanatically on his truly buggy board.
2846 *
2847 * FIXME: really need to revamp this for all platforms.
2848 */
2849static inline void __init check_timer(void)
2850{
2851 struct irq_desc *desc = irq_to_desc(0);
2852 struct irq_cfg *cfg = desc->chip_data;
2853 int cpu = boot_cpu_id;
2854 int apic1, pin1, apic2, pin2;
2855 unsigned long flags;
2856 int no_pin1 = 0;
2857
2858 local_irq_save(flags);
2859
2860 /*
2861 * get/set the timer IRQ vector:
2862 */
2863 disable_8259A_irq(0);
2864 assign_irq_vector(0, cfg, apic->target_cpus());
2865
2866 /*
2867 * As IRQ0 is to be enabled in the 8259A, the virtual
2868 * wire has to be disabled in the local APIC. Also
2869 * timer interrupts need to be acknowledged manually in
2870 * the 8259A for the i82489DX when using the NMI
2871 * watchdog as that APIC treats NMIs as level-triggered.
2872 * The AEOI mode will finish them in the 8259A
2873 * automatically.
2874 */
2875 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2876 init_8259A(1);
2877#ifdef CONFIG_X86_32
2878 {
2879 unsigned int ver;
2880
2881 ver = apic_read(APIC_LVR);
2882 ver = GET_APIC_VERSION(ver);
2883 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2884 }
2885#endif
2886
2887 pin1 = find_isa_irq_pin(0, mp_INT);
2888 apic1 = find_isa_irq_apic(0, mp_INT);
2889 pin2 = ioapic_i8259.pin;
2890 apic2 = ioapic_i8259.apic;
2891
2892 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2893 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2894 cfg->vector, apic1, pin1, apic2, pin2);
2895
2896 /*
2897 * Some BIOS writers are clueless and report the ExtINTA
2898 * I/O APIC input from the cascaded 8259A as the timer
2899 * interrupt input. So just in case, if only one pin
2900 * was found above, try it both directly and through the
2901 * 8259A.
2902 */
2903 if (pin1 == -1) {
2904#ifdef CONFIG_INTR_REMAP
2905 if (intr_remapping_enabled)
2906 panic("BIOS bug: timer not connected to IO-APIC");
2907#endif
2908 pin1 = pin2;
2909 apic1 = apic2;
2910 no_pin1 = 1;
2911 } else if (pin2 == -1) {
2912 pin2 = pin1;
2913 apic2 = apic1;
2914 }
2915
2916 if (pin1 != -1) {
2917 /*
2918 * Ok, does IRQ0 through the IOAPIC work?
2919 */
2920 if (no_pin1) {
2921 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2922 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2923 } else {
2924 /* for edge trigger, setup_IO_APIC_irq already
2925 * leave it unmasked.
2926 * so only need to unmask if it is level-trigger
2927 * do we really have level trigger timer?
2928 */
2929 int idx;
2930 idx = find_irq_entry(apic1, pin1, mp_INT);
2931 if (idx != -1 && irq_trigger(idx))
2932 unmask_IO_APIC_irq_desc(desc);
2933 }
2934 if (timer_irq_works()) {
2935 if (nmi_watchdog == NMI_IO_APIC) {
2936 setup_nmi();
2937 enable_8259A_irq(0);
2938 }
2939 if (disable_timer_pin_1 > 0)
2940 clear_IO_APIC_pin(0, pin1);
2941 goto out;
2942 }
2943#ifdef CONFIG_INTR_REMAP
2944 if (intr_remapping_enabled)
2945 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2946#endif
2947 local_irq_disable();
2948 clear_IO_APIC_pin(apic1, pin1);
2949 if (!no_pin1)
2950 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2951 "8254 timer not connected to IO-APIC\n");
2952
2953 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2954 "(IRQ0) through the 8259A ...\n");
2955 apic_printk(APIC_QUIET, KERN_INFO
2956 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2957 /*
2958 * legacy devices should be connected to IO APIC #0
2959 */
2960 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2961 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2962 enable_8259A_irq(0);
2963 if (timer_irq_works()) {
2964 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2965 timer_through_8259 = 1;
2966 if (nmi_watchdog == NMI_IO_APIC) {
2967 disable_8259A_irq(0);
2968 setup_nmi();
2969 enable_8259A_irq(0);
2970 }
2971 goto out;
2972 }
2973 /*
2974 * Cleanup, just in case ...
2975 */
2976 local_irq_disable();
2977 disable_8259A_irq(0);
2978 clear_IO_APIC_pin(apic2, pin2);
2979 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2980 }
2981
2982 if (nmi_watchdog == NMI_IO_APIC) {
2983 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2984 "through the IO-APIC - disabling NMI Watchdog!\n");
2985 nmi_watchdog = NMI_NONE;
2986 }
2987#ifdef CONFIG_X86_32
2988 timer_ack = 0;
2989#endif
2990
2991 apic_printk(APIC_QUIET, KERN_INFO
2992 "...trying to set up timer as Virtual Wire IRQ...\n");
2993
2994 lapic_register_intr(0, desc);
2995 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2996 enable_8259A_irq(0);
2997
2998 if (timer_irq_works()) {
2999 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3000 goto out;
3001 }
3002 local_irq_disable();
3003 disable_8259A_irq(0);
3004 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3005 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3006
3007 apic_printk(APIC_QUIET, KERN_INFO
3008 "...trying to set up timer as ExtINT IRQ...\n");
3009
3010 init_8259A(0);
3011 make_8259A_irq(0);
3012 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3013
3014 unlock_ExtINT_logic();
3015
3016 if (timer_irq_works()) {
3017 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3018 goto out;
3019 }
3020 local_irq_disable();
3021 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3022 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3023 "report. Then try booting with the 'noapic' option.\n");
3024out:
3025 local_irq_restore(flags);
3026}
3027
3028/*
3029 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3030 * to devices. However there may be an I/O APIC pin available for
3031 * this interrupt regardless. The pin may be left unconnected, but
3032 * typically it will be reused as an ExtINT cascade interrupt for
3033 * the master 8259A. In the MPS case such a pin will normally be
3034 * reported as an ExtINT interrupt in the MP table. With ACPI
3035 * there is no provision for ExtINT interrupts, and in the absence
3036 * of an override it would be treated as an ordinary ISA I/O APIC
3037 * interrupt, that is edge-triggered and unmasked by default. We
3038 * used to do this, but it caused problems on some systems because
3039 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3040 * the same ExtINT cascade interrupt to drive the local APIC of the
3041 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3042 * the I/O APIC in all cases now. No actual device should request
3043 * it anyway. --macro
3044 */
3045#define PIC_IRQS (1 << PIC_CASCADE_IR)
3046
3047void __init setup_IO_APIC(void)
3048{
3049
3050 /*
3051 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3052 */
3053
3054 io_apic_irqs = ~PIC_IRQS;
3055
3056 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3057 /*
3058 * Set up IO-APIC IRQ routing.
3059 */
3060#ifdef CONFIG_X86_32
3061 if (!acpi_ioapic)
3062 setup_ioapic_ids_from_mpc();
3063#endif
3064 sync_Arb_IDs();
3065 setup_IO_APIC_irqs();
3066 init_IO_APIC_traps();
3067 check_timer();
3068}
3069
3070/*
3071 * Called after all the initialization is done. If we didnt find any
3072 * APIC bugs then we can allow the modify fast path
3073 */
3074
3075static int __init io_apic_bug_finalize(void)
3076{
3077 if (sis_apic_bug == -1)
3078 sis_apic_bug = 0;
3079 return 0;
3080}
3081
3082late_initcall(io_apic_bug_finalize);
3083
3084struct sysfs_ioapic_data {
3085 struct sys_device dev;
3086 struct IO_APIC_route_entry entry[0];
3087};
3088static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3089
3090static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3091{
3092 struct IO_APIC_route_entry *entry;
3093 struct sysfs_ioapic_data *data;
3094 int i;
3095
3096 data = container_of(dev, struct sysfs_ioapic_data, dev);
3097 entry = data->entry;
3098 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3099 *entry = ioapic_read_entry(dev->id, i);
3100
3101 return 0;
3102}
3103
3104static int ioapic_resume(struct sys_device *dev)
3105{
3106 struct IO_APIC_route_entry *entry;
3107 struct sysfs_ioapic_data *data;
3108 unsigned long flags;
3109 union IO_APIC_reg_00 reg_00;
3110 int i;
3111
3112 data = container_of(dev, struct sysfs_ioapic_data, dev);
3113 entry = data->entry;
3114
3115 spin_lock_irqsave(&ioapic_lock, flags);
3116 reg_00.raw = io_apic_read(dev->id, 0);
3117 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3118 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3119 io_apic_write(dev->id, 0, reg_00.raw);
3120 }
3121 spin_unlock_irqrestore(&ioapic_lock, flags);
3122 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3123 ioapic_write_entry(dev->id, i, entry[i]);
3124
3125 return 0;
3126}
3127
3128static struct sysdev_class ioapic_sysdev_class = {
3129 .name = "ioapic",
3130 .suspend = ioapic_suspend,
3131 .resume = ioapic_resume,
3132};
3133
3134static int __init ioapic_init_sysfs(void)
3135{
3136 struct sys_device * dev;
3137 int i, size, error;
3138
3139 error = sysdev_class_register(&ioapic_sysdev_class);
3140 if (error)
3141 return error;
3142
3143 for (i = 0; i < nr_ioapics; i++ ) {
3144 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3145 * sizeof(struct IO_APIC_route_entry);
3146 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3147 if (!mp_ioapic_data[i]) {
3148 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3149 continue;
3150 }
3151 dev = &mp_ioapic_data[i]->dev;
3152 dev->id = i;
3153 dev->cls = &ioapic_sysdev_class;
3154 error = sysdev_register(dev);
3155 if (error) {
3156 kfree(mp_ioapic_data[i]);
3157 mp_ioapic_data[i] = NULL;
3158 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3159 continue;
3160 }
3161 }
3162
3163 return 0;
3164}
3165
3166device_initcall(ioapic_init_sysfs);
3167
3168static int nr_irqs_gsi = NR_IRQS_LEGACY;
3169/*
3170 * Dynamic irq allocate and deallocation
3171 */
3172unsigned int create_irq_nr(unsigned int irq_want)
3173{
3174 /* Allocate an unused irq */
3175 unsigned int irq;
3176 unsigned int new;
3177 unsigned long flags;
3178 struct irq_cfg *cfg_new = NULL;
3179 int cpu = boot_cpu_id;
3180 struct irq_desc *desc_new = NULL;
3181
3182 irq = 0;
3183 if (irq_want < nr_irqs_gsi)
3184 irq_want = nr_irqs_gsi;
3185
3186 spin_lock_irqsave(&vector_lock, flags);
3187 for (new = irq_want; new < nr_irqs; new++) {
3188 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3189 if (!desc_new) {
3190 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3191 continue;
3192 }
3193 cfg_new = desc_new->chip_data;
3194
3195 if (cfg_new->vector != 0)
3196 continue;
3197 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3198 irq = new;
3199 break;
3200 }
3201 spin_unlock_irqrestore(&vector_lock, flags);
3202
3203 if (irq > 0) {
3204 dynamic_irq_init(irq);
3205 /* restore it, in case dynamic_irq_init clear it */
3206 if (desc_new)
3207 desc_new->chip_data = cfg_new;
3208 }
3209 return irq;
3210}
3211
3212int create_irq(void)
3213{
3214 unsigned int irq_want;
3215 int irq;
3216
3217 irq_want = nr_irqs_gsi;
3218 irq = create_irq_nr(irq_want);
3219
3220 if (irq == 0)
3221 irq = -1;
3222
3223 return irq;
3224}
3225
3226void destroy_irq(unsigned int irq)
3227{
3228 unsigned long flags;
3229 struct irq_cfg *cfg;
3230 struct irq_desc *desc;
3231
3232 /* store it, in case dynamic_irq_cleanup clear it */
3233 desc = irq_to_desc(irq);
3234 cfg = desc->chip_data;
3235 dynamic_irq_cleanup(irq);
3236 /* connect back irq_cfg */
3237 if (desc)
3238 desc->chip_data = cfg;
3239
3240#ifdef CONFIG_INTR_REMAP
3241 free_irte(irq);
3242#endif
3243 spin_lock_irqsave(&vector_lock, flags);
3244 __clear_irq_vector(irq, cfg);
3245 spin_unlock_irqrestore(&vector_lock, flags);
3246}
3247
3248/*
3249 * MSI message composition
3250 */
3251#ifdef CONFIG_PCI_MSI
3252static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3253{
3254 struct irq_cfg *cfg;
3255 int err;
3256 unsigned dest;
3257
3258 if (disable_apic)
3259 return -ENXIO;
3260
3261 cfg = irq_cfg(irq);
3262 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3263 if (err)
3264 return err;
3265
3266 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3267
3268#ifdef CONFIG_INTR_REMAP
3269 if (irq_remapped(irq)) {
3270 struct irte irte;
3271 int ir_index;
3272 u16 sub_handle;
3273
3274 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3275 BUG_ON(ir_index == -1);
3276
3277 memset (&irte, 0, sizeof(irte));
3278
3279 irte.present = 1;
3280 irte.dst_mode = apic->irq_dest_mode;
3281 irte.trigger_mode = 0; /* edge */
3282 irte.dlvry_mode = apic->irq_delivery_mode;
3283 irte.vector = cfg->vector;
3284 irte.dest_id = IRTE_DEST(dest);
3285
3286 modify_irte(irq, &irte);
3287
3288 msg->address_hi = MSI_ADDR_BASE_HI;
3289 msg->data = sub_handle;
3290 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3291 MSI_ADDR_IR_SHV |
3292 MSI_ADDR_IR_INDEX1(ir_index) |
3293 MSI_ADDR_IR_INDEX2(ir_index);
3294 } else
3295#endif
3296 {
3297 msg->address_hi = MSI_ADDR_BASE_HI;
3298 msg->address_lo =
3299 MSI_ADDR_BASE_LO |
3300 ((apic->irq_dest_mode == 0) ?
3301 MSI_ADDR_DEST_MODE_PHYSICAL:
3302 MSI_ADDR_DEST_MODE_LOGICAL) |
3303 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3304 MSI_ADDR_REDIRECTION_CPU:
3305 MSI_ADDR_REDIRECTION_LOWPRI) |
3306 MSI_ADDR_DEST_ID(dest);
3307
3308 msg->data =
3309 MSI_DATA_TRIGGER_EDGE |
3310 MSI_DATA_LEVEL_ASSERT |
3311 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3312 MSI_DATA_DELIVERY_FIXED:
3313 MSI_DATA_DELIVERY_LOWPRI) |
3314 MSI_DATA_VECTOR(cfg->vector);
3315 }
3316 return err;
3317}
3318
3319#ifdef CONFIG_SMP
3320static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3321{
3322 struct irq_desc *desc = irq_to_desc(irq);
3323 struct irq_cfg *cfg;
3324 struct msi_msg msg;
3325 unsigned int dest;
3326
3327 dest = set_desc_affinity(desc, mask);
3328 if (dest == BAD_APICID)
3329 return;
3330
3331 cfg = desc->chip_data;
3332
3333 read_msi_msg_desc(desc, &msg);
3334
3335 msg.data &= ~MSI_DATA_VECTOR_MASK;
3336 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3337 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3338 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3339
3340 write_msi_msg_desc(desc, &msg);
3341}
3342#ifdef CONFIG_INTR_REMAP
3343/*
3344 * Migrate the MSI irq to another cpumask. This migration is
3345 * done in the process context using interrupt-remapping hardware.
3346 */
3347static void
3348ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3349{
3350 struct irq_desc *desc = irq_to_desc(irq);
3351 struct irq_cfg *cfg = desc->chip_data;
3352 unsigned int dest;
3353 struct irte irte;
3354
3355 if (get_irte(irq, &irte))
3356 return;
3357
3358 dest = set_desc_affinity(desc, mask);
3359 if (dest == BAD_APICID)
3360 return;
3361
3362 irte.vector = cfg->vector;
3363 irte.dest_id = IRTE_DEST(dest);
3364
3365 /*
3366 * atomically update the IRTE with the new destination and vector.
3367 */
3368 modify_irte(irq, &irte);
3369
3370 /*
3371 * After this point, all the interrupts will start arriving
3372 * at the new destination. So, time to cleanup the previous
3373 * vector allocation.
3374 */
3375 if (cfg->move_in_progress)
3376 send_cleanup_vector(cfg);
3377}
3378
3379#endif
3380#endif /* CONFIG_SMP */
3381
3382/*
3383 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3384 * which implement the MSI or MSI-X Capability Structure.
3385 */
3386static struct irq_chip msi_chip = {
3387 .name = "PCI-MSI",
3388 .unmask = unmask_msi_irq,
3389 .mask = mask_msi_irq,
3390 .ack = ack_apic_edge,
3391#ifdef CONFIG_SMP
3392 .set_affinity = set_msi_irq_affinity,
3393#endif
3394 .retrigger = ioapic_retrigger_irq,
3395};
3396
3397#ifdef CONFIG_INTR_REMAP
3398static struct irq_chip msi_ir_chip = {
3399 .name = "IR-PCI-MSI",
3400 .unmask = unmask_msi_irq,
3401 .mask = mask_msi_irq,
3402 .ack = ack_x2apic_edge,
3403#ifdef CONFIG_SMP
3404 .set_affinity = ir_set_msi_irq_affinity,
3405#endif
3406 .retrigger = ioapic_retrigger_irq,
3407};
3408
3409/*
3410 * Map the PCI dev to the corresponding remapping hardware unit
3411 * and allocate 'nvec' consecutive interrupt-remapping table entries
3412 * in it.
3413 */
3414static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3415{
3416 struct intel_iommu *iommu;
3417 int index;
3418
3419 iommu = map_dev_to_ir(dev);
3420 if (!iommu) {
3421 printk(KERN_ERR
3422 "Unable to map PCI %s to iommu\n", pci_name(dev));
3423 return -ENOENT;
3424 }
3425
3426 index = alloc_irte(iommu, irq, nvec);
3427 if (index < 0) {
3428 printk(KERN_ERR
3429 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3430 pci_name(dev));
3431 return -ENOSPC;
3432 }
3433 return index;
3434}
3435#endif
3436
3437static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3438{
3439 int ret;
3440 struct msi_msg msg;
3441
3442 ret = msi_compose_msg(dev, irq, &msg);
3443 if (ret < 0)
3444 return ret;
3445
3446 set_irq_msi(irq, msidesc);
3447 write_msi_msg(irq, &msg);
3448
3449#ifdef CONFIG_INTR_REMAP
3450 if (irq_remapped(irq)) {
3451 struct irq_desc *desc = irq_to_desc(irq);
3452 /*
3453 * irq migration in process context
3454 */
3455 desc->status |= IRQ_MOVE_PCNTXT;
3456 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3457 } else
3458#endif
3459 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3460
3461 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3462
3463 return 0;
3464}
3465
3466int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3467{
3468 unsigned int irq;
3469 int ret, sub_handle;
3470 struct msi_desc *msidesc;
3471 unsigned int irq_want;
3472
3473#ifdef CONFIG_INTR_REMAP
3474 struct intel_iommu *iommu = 0;
3475 int index = 0;
3476#endif
3477
3478 irq_want = nr_irqs_gsi;
3479 sub_handle = 0;
3480 list_for_each_entry(msidesc, &dev->msi_list, list) {
3481 irq = create_irq_nr(irq_want);
3482 if (irq == 0)
3483 return -1;
3484 irq_want = irq + 1;
3485#ifdef CONFIG_INTR_REMAP
3486 if (!intr_remapping_enabled)
3487 goto no_ir;
3488
3489 if (!sub_handle) {
3490 /*
3491 * allocate the consecutive block of IRTE's
3492 * for 'nvec'
3493 */
3494 index = msi_alloc_irte(dev, irq, nvec);
3495 if (index < 0) {
3496 ret = index;
3497 goto error;
3498 }
3499 } else {
3500 iommu = map_dev_to_ir(dev);
3501 if (!iommu) {
3502 ret = -ENOENT;
3503 goto error;
3504 }
3505 /*
3506 * setup the mapping between the irq and the IRTE
3507 * base index, the sub_handle pointing to the
3508 * appropriate interrupt remap table entry.
3509 */
3510 set_irte_irq(irq, iommu, index, sub_handle);
3511 }
3512no_ir:
3513#endif
3514 ret = setup_msi_irq(dev, msidesc, irq);
3515 if (ret < 0)
3516 goto error;
3517 sub_handle++;
3518 }
3519 return 0;
3520
3521error:
3522 destroy_irq(irq);
3523 return ret;
3524}
3525
3526void arch_teardown_msi_irq(unsigned int irq)
3527{
3528 destroy_irq(irq);
3529}
3530
3531#ifdef CONFIG_DMAR
3532#ifdef CONFIG_SMP
3533static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3534{
3535 struct irq_desc *desc = irq_to_desc(irq);
3536 struct irq_cfg *cfg;
3537 struct msi_msg msg;
3538 unsigned int dest;
3539
3540 dest = set_desc_affinity(desc, mask);
3541 if (dest == BAD_APICID)
3542 return;
3543
3544 cfg = desc->chip_data;
3545
3546 dmar_msi_read(irq, &msg);
3547
3548 msg.data &= ~MSI_DATA_VECTOR_MASK;
3549 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3550 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3551 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3552
3553 dmar_msi_write(irq, &msg);
3554}
3555
3556#endif /* CONFIG_SMP */
3557
3558struct irq_chip dmar_msi_type = {
3559 .name = "DMAR_MSI",
3560 .unmask = dmar_msi_unmask,
3561 .mask = dmar_msi_mask,
3562 .ack = ack_apic_edge,
3563#ifdef CONFIG_SMP
3564 .set_affinity = dmar_msi_set_affinity,
3565#endif
3566 .retrigger = ioapic_retrigger_irq,
3567};
3568
3569int arch_setup_dmar_msi(unsigned int irq)
3570{
3571 int ret;
3572 struct msi_msg msg;
3573
3574 ret = msi_compose_msg(NULL, irq, &msg);
3575 if (ret < 0)
3576 return ret;
3577 dmar_msi_write(irq, &msg);
3578 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3579 "edge");
3580 return 0;
3581}
3582#endif
3583
3584#ifdef CONFIG_HPET_TIMER
3585
3586#ifdef CONFIG_SMP
3587static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3588{
3589 struct irq_desc *desc = irq_to_desc(irq);
3590 struct irq_cfg *cfg;
3591 struct msi_msg msg;
3592 unsigned int dest;
3593
3594 dest = set_desc_affinity(desc, mask);
3595 if (dest == BAD_APICID)
3596 return;
3597
3598 cfg = desc->chip_data;
3599
3600 hpet_msi_read(irq, &msg);
3601
3602 msg.data &= ~MSI_DATA_VECTOR_MASK;
3603 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3604 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3605 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3606
3607 hpet_msi_write(irq, &msg);
3608}
3609
3610#endif /* CONFIG_SMP */
3611
3612struct irq_chip hpet_msi_type = {
3613 .name = "HPET_MSI",
3614 .unmask = hpet_msi_unmask,
3615 .mask = hpet_msi_mask,
3616 .ack = ack_apic_edge,
3617#ifdef CONFIG_SMP
3618 .set_affinity = hpet_msi_set_affinity,
3619#endif
3620 .retrigger = ioapic_retrigger_irq,
3621};
3622
3623int arch_setup_hpet_msi(unsigned int irq)
3624{
3625 int ret;
3626 struct msi_msg msg;
3627
3628 ret = msi_compose_msg(NULL, irq, &msg);
3629 if (ret < 0)
3630 return ret;
3631
3632 hpet_msi_write(irq, &msg);
3633 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3634 "edge");
3635
3636 return 0;
3637}
3638#endif
3639
3640#endif /* CONFIG_PCI_MSI */
3641/*
3642 * Hypertransport interrupt support
3643 */
3644#ifdef CONFIG_HT_IRQ
3645
3646#ifdef CONFIG_SMP
3647
3648static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3649{
3650 struct ht_irq_msg msg;
3651 fetch_ht_irq_msg(irq, &msg);
3652
3653 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3654 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3655
3656 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3657 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3658
3659 write_ht_irq_msg(irq, &msg);
3660}
3661
3662static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3663{
3664 struct irq_desc *desc = irq_to_desc(irq);
3665 struct irq_cfg *cfg;
3666 unsigned int dest;
3667
3668 dest = set_desc_affinity(desc, mask);
3669 if (dest == BAD_APICID)
3670 return;
3671
3672 cfg = desc->chip_data;
3673
3674 target_ht_irq(irq, dest, cfg->vector);
3675}
3676
3677#endif
3678
3679static struct irq_chip ht_irq_chip = {
3680 .name = "PCI-HT",
3681 .mask = mask_ht_irq,
3682 .unmask = unmask_ht_irq,
3683 .ack = ack_apic_edge,
3684#ifdef CONFIG_SMP
3685 .set_affinity = set_ht_irq_affinity,
3686#endif
3687 .retrigger = ioapic_retrigger_irq,
3688};
3689
3690int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3691{
3692 struct irq_cfg *cfg;
3693 int err;
3694
3695 if (disable_apic)
3696 return -ENXIO;
3697
3698 cfg = irq_cfg(irq);
3699 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3700 if (!err) {
3701 struct ht_irq_msg msg;
3702 unsigned dest;
3703
3704 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3705 apic->target_cpus());
3706
3707 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3708
3709 msg.address_lo =
3710 HT_IRQ_LOW_BASE |
3711 HT_IRQ_LOW_DEST_ID(dest) |
3712 HT_IRQ_LOW_VECTOR(cfg->vector) |
3713 ((apic->irq_dest_mode == 0) ?
3714 HT_IRQ_LOW_DM_PHYSICAL :
3715 HT_IRQ_LOW_DM_LOGICAL) |
3716 HT_IRQ_LOW_RQEOI_EDGE |
3717 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3718 HT_IRQ_LOW_MT_FIXED :
3719 HT_IRQ_LOW_MT_ARBITRATED) |
3720 HT_IRQ_LOW_IRQ_MASKED;
3721
3722 write_ht_irq_msg(irq, &msg);
3723
3724 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3725 handle_edge_irq, "edge");
3726
3727 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3728 }
3729 return err;
3730}
3731#endif /* CONFIG_HT_IRQ */
3732
3733#ifdef CONFIG_X86_UV
3734/*
3735 * Re-target the irq to the specified CPU and enable the specified MMR located
3736 * on the specified blade to allow the sending of MSIs to the specified CPU.
3737 */
3738int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3739 unsigned long mmr_offset)
3740{
3741 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3742 struct irq_cfg *cfg;
3743 int mmr_pnode;
3744 unsigned long mmr_value;
3745 struct uv_IO_APIC_route_entry *entry;
3746 unsigned long flags;
3747 int err;
3748
3749 cfg = irq_cfg(irq);
3750
3751 err = assign_irq_vector(irq, cfg, eligible_cpu);
3752 if (err != 0)
3753 return err;
3754
3755 spin_lock_irqsave(&vector_lock, flags);
3756 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3757 irq_name);
3758 spin_unlock_irqrestore(&vector_lock, flags);
3759
3760 mmr_value = 0;
3761 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3762 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3763
3764 entry->vector = cfg->vector;
3765 entry->delivery_mode = apic->irq_delivery_mode;
3766 entry->dest_mode = apic->irq_dest_mode;
3767 entry->polarity = 0;
3768 entry->trigger = 0;
3769 entry->mask = 0;
3770 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3771
3772 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3773 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3774
3775 return irq;
3776}
3777
3778/*
3779 * Disable the specified MMR located on the specified blade so that MSIs are
3780 * longer allowed to be sent.
3781 */
3782void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3783{
3784 unsigned long mmr_value;
3785 struct uv_IO_APIC_route_entry *entry;
3786 int mmr_pnode;
3787
3788 mmr_value = 0;
3789 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3790 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3791
3792 entry->mask = 1;
3793
3794 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3795 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3796}
3797#endif /* CONFIG_X86_64 */
3798
3799int __init io_apic_get_redir_entries (int ioapic)
3800{
3801 union IO_APIC_reg_01 reg_01;
3802 unsigned long flags;
3803
3804 spin_lock_irqsave(&ioapic_lock, flags);
3805 reg_01.raw = io_apic_read(ioapic, 1);
3806 spin_unlock_irqrestore(&ioapic_lock, flags);
3807
3808 return reg_01.bits.entries;
3809}
3810
3811void __init probe_nr_irqs_gsi(void)
3812{
3813 int nr = 0;
3814
3815 nr = acpi_probe_gsi();
3816 if (nr > nr_irqs_gsi) {
3817 nr_irqs_gsi = nr;
3818 } else {
3819 /* for acpi=off or acpi is not compiled in */
3820 int idx;
3821
3822 nr = 0;
3823 for (idx = 0; idx < nr_ioapics; idx++)
3824 nr += io_apic_get_redir_entries(idx) + 1;
3825
3826 if (nr > nr_irqs_gsi)
3827 nr_irqs_gsi = nr;
3828 }
3829
3830 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3831}
3832
3833#ifdef CONFIG_SPARSE_IRQ
3834int __init arch_probe_nr_irqs(void)
3835{
3836 int nr;
3837
3838 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3839 nr_irqs = NR_VECTORS * nr_cpu_ids;
3840
3841 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3842#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3843 /*
3844 * for MSI and HT dyn irq
3845 */
3846 nr += nr_irqs_gsi * 16;
3847#endif
3848 if (nr < nr_irqs)
3849 nr_irqs = nr;
3850
3851 return 0;
3852}
3853#endif
3854
3855/* --------------------------------------------------------------------------
3856 ACPI-based IOAPIC Configuration
3857 -------------------------------------------------------------------------- */
3858
3859#ifdef CONFIG_ACPI
3860
3861#ifdef CONFIG_X86_32
3862int __init io_apic_get_unique_id(int ioapic, int apic_id)
3863{
3864 union IO_APIC_reg_00 reg_00;
3865 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3866 physid_mask_t tmp;
3867 unsigned long flags;
3868 int i = 0;
3869
3870 /*
3871 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873 * supports up to 16 on one shared APIC bus.
3874 *
3875 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876 * advantage of new APIC bus architecture.
3877 */
3878
3879 if (physids_empty(apic_id_map))
3880 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3881
3882 spin_lock_irqsave(&ioapic_lock, flags);
3883 reg_00.raw = io_apic_read(ioapic, 0);
3884 spin_unlock_irqrestore(&ioapic_lock, flags);
3885
3886 if (apic_id >= get_physical_broadcast()) {
3887 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3888 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3889 apic_id = reg_00.bits.ID;
3890 }
3891
3892 /*
3893 * Every APIC in a system must have a unique ID or we get lots of nice
3894 * 'stuck on smp_invalidate_needed IPI wait' messages.
3895 */
3896 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3897
3898 for (i = 0; i < get_physical_broadcast(); i++) {
3899 if (!apic->check_apicid_used(apic_id_map, i))
3900 break;
3901 }
3902
3903 if (i == get_physical_broadcast())
3904 panic("Max apic_id exceeded!\n");
3905
3906 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3907 "trying %d\n", ioapic, apic_id, i);
3908
3909 apic_id = i;
3910 }
3911
3912 tmp = apic->apicid_to_cpu_present(apic_id);
3913 physids_or(apic_id_map, apic_id_map, tmp);
3914
3915 if (reg_00.bits.ID != apic_id) {
3916 reg_00.bits.ID = apic_id;
3917
3918 spin_lock_irqsave(&ioapic_lock, flags);
3919 io_apic_write(ioapic, 0, reg_00.raw);
3920 reg_00.raw = io_apic_read(ioapic, 0);
3921 spin_unlock_irqrestore(&ioapic_lock, flags);
3922
3923 /* Sanity check */
3924 if (reg_00.bits.ID != apic_id) {
3925 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3926 return -1;
3927 }
3928 }
3929
3930 apic_printk(APIC_VERBOSE, KERN_INFO
3931 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932
3933 return apic_id;
3934}
3935
3936int __init io_apic_get_version(int ioapic)
3937{
3938 union IO_APIC_reg_01 reg_01;
3939 unsigned long flags;
3940
3941 spin_lock_irqsave(&ioapic_lock, flags);
3942 reg_01.raw = io_apic_read(ioapic, 1);
3943 spin_unlock_irqrestore(&ioapic_lock, flags);
3944
3945 return reg_01.bits.version;
3946}
3947#endif
3948
3949int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3950{
3951 struct irq_desc *desc;
3952 struct irq_cfg *cfg;
3953 int cpu = boot_cpu_id;
3954
3955 if (!IO_APIC_IRQ(irq)) {
3956 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3957 ioapic);
3958 return -EINVAL;
3959 }
3960
3961 desc = irq_to_desc_alloc_cpu(irq, cpu);
3962 if (!desc) {
3963 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3964 return 0;
3965 }
3966
3967 /*
3968 * IRQs < 16 are already in the irq_2_pin[] map
3969 */
3970 if (irq >= NR_IRQS_LEGACY) {
3971 cfg = desc->chip_data;
3972 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3973 }
3974
3975 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3976
3977 return 0;
3978}
3979
3980
3981int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3982{
3983 int i;
3984
3985 if (skip_ioapic_setup)
3986 return -1;
3987
3988 for (i = 0; i < mp_irq_entries; i++)
3989 if (mp_irqs[i].irqtype == mp_INT &&
3990 mp_irqs[i].srcbusirq == bus_irq)
3991 break;
3992 if (i >= mp_irq_entries)
3993 return -1;
3994
3995 *trigger = irq_trigger(i);
3996 *polarity = irq_polarity(i);
3997 return 0;
3998}
3999
4000#endif /* CONFIG_ACPI */
4001
4002/*
4003 * This function currently is only a helper for the i386 smp boot process where
4004 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4005 * so mask in all cases should simply be apic->target_cpus()
4006 */
4007#ifdef CONFIG_SMP
4008void __init setup_ioapic_dest(void)
4009{
4010 int pin, ioapic, irq, irq_entry;
4011 struct irq_desc *desc;
4012 struct irq_cfg *cfg;
4013 const struct cpumask *mask;
4014
4015 if (skip_ioapic_setup == 1)
4016 return;
4017
4018 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4019 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4020 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4021 if (irq_entry == -1)
4022 continue;
4023 irq = pin_2_irq(irq_entry, ioapic, pin);
4024
4025 /* setup_IO_APIC_irqs could fail to get vector for some device
4026 * when you have too many devices, because at that time only boot
4027 * cpu is online.
4028 */
4029 desc = irq_to_desc(irq);
4030 cfg = desc->chip_data;
4031 if (!cfg->vector) {
4032 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4033 irq_trigger(irq_entry),
4034 irq_polarity(irq_entry));
4035 continue;
4036
4037 }
4038
4039 /*
4040 * Honour affinities which have been set in early boot
4041 */
4042 if (desc->status &
4043 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4044 mask = desc->affinity;
4045 else
4046 mask = apic->target_cpus();
4047
4048#ifdef CONFIG_INTR_REMAP
4049 if (intr_remapping_enabled)
4050 set_ir_ioapic_affinity_irq_desc(desc, mask);
4051 else
4052#endif
4053 set_ioapic_affinity_irq_desc(desc, mask);
4054 }
4055
4056 }
4057}
4058#endif
4059
4060#define IOAPIC_RESOURCE_NAME_SIZE 11
4061
4062static struct resource *ioapic_resources;
4063
4064static struct resource * __init ioapic_setup_resources(void)
4065{
4066 unsigned long n;
4067 struct resource *res;
4068 char *mem;
4069 int i;
4070
4071 if (nr_ioapics <= 0)
4072 return NULL;
4073
4074 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4075 n *= nr_ioapics;
4076
4077 mem = alloc_bootmem(n);
4078 res = (void *)mem;
4079
4080 if (mem != NULL) {
4081 mem += sizeof(struct resource) * nr_ioapics;
4082
4083 for (i = 0; i < nr_ioapics; i++) {
4084 res[i].name = mem;
4085 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4086 sprintf(mem, "IOAPIC %u", i);
4087 mem += IOAPIC_RESOURCE_NAME_SIZE;
4088 }
4089 }
4090
4091 ioapic_resources = res;
4092
4093 return res;
4094}
4095
4096void __init ioapic_init_mappings(void)
4097{
4098 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4099 struct resource *ioapic_res;
4100 int i;
4101
4102 ioapic_res = ioapic_setup_resources();
4103 for (i = 0; i < nr_ioapics; i++) {
4104 if (smp_found_config) {
4105 ioapic_phys = mp_ioapics[i].apicaddr;
4106#ifdef CONFIG_X86_32
4107 if (!ioapic_phys) {
4108 printk(KERN_ERR
4109 "WARNING: bogus zero IO-APIC "
4110 "address found in MPTABLE, "
4111 "disabling IO/APIC support!\n");
4112 smp_found_config = 0;
4113 skip_ioapic_setup = 1;
4114 goto fake_ioapic_page;
4115 }
4116#endif
4117 } else {
4118#ifdef CONFIG_X86_32
4119fake_ioapic_page:
4120#endif
4121 ioapic_phys = (unsigned long)
4122 alloc_bootmem_pages(PAGE_SIZE);
4123 ioapic_phys = __pa(ioapic_phys);
4124 }
4125 set_fixmap_nocache(idx, ioapic_phys);
4126 apic_printk(APIC_VERBOSE,
4127 "mapped IOAPIC to %08lx (%08lx)\n",
4128 __fix_to_virt(idx), ioapic_phys);
4129 idx++;
4130
4131 if (ioapic_res != NULL) {
4132 ioapic_res->start = ioapic_phys;
4133 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4134 ioapic_res++;
4135 }
4136 }
4137}
4138
4139static int __init ioapic_insert_resources(void)
4140{
4141 int i;
4142 struct resource *r = ioapic_resources;
4143
4144 if (!r) {
4145 printk(KERN_ERR
4146 "IO APIC resources could be not be allocated.\n");
4147 return -1;
4148 }
4149
4150 for (i = 0; i < nr_ioapics; i++) {
4151 insert_resource(&iomem_resource, r);
4152 r++;
4153 }
4154
4155 return 0;
4156}
4157
4158/* Insert the IO APIC resources after PCI initialization has occured to handle
4159 * IO APICS that are mapped in on a BAR in PCI space. */
4160late_initcall(ioapic_insert_resources);
diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c
new file mode 100644
index 000000000000..dbf5445727a9
--- /dev/null
+++ b/arch/x86/kernel/apic/ipi.c
@@ -0,0 +1,164 @@
1#include <linux/cpumask.h>
2#include <linux/interrupt.h>
3#include <linux/init.h>
4
5#include <linux/mm.h>
6#include <linux/delay.h>
7#include <linux/spinlock.h>
8#include <linux/kernel_stat.h>
9#include <linux/mc146818rtc.h>
10#include <linux/cache.h>
11#include <linux/cpu.h>
12#include <linux/module.h>
13
14#include <asm/smp.h>
15#include <asm/mtrr.h>
16#include <asm/tlbflush.h>
17#include <asm/mmu_context.h>
18#include <asm/apic.h>
19#include <asm/proto.h>
20#include <asm/ipi.h>
21
22void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector)
23{
24 unsigned long query_cpu;
25 unsigned long flags;
26
27 /*
28 * Hack. The clustered APIC addressing mode doesn't allow us to send
29 * to an arbitrary mask, so I do a unicast to each CPU instead.
30 * - mbligh
31 */
32 local_irq_save(flags);
33 for_each_cpu(query_cpu, mask) {
34 __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
35 query_cpu), vector, APIC_DEST_PHYSICAL);
36 }
37 local_irq_restore(flags);
38}
39
40void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask,
41 int vector)
42{
43 unsigned int this_cpu = smp_processor_id();
44 unsigned int query_cpu;
45 unsigned long flags;
46
47 /* See Hack comment above */
48
49 local_irq_save(flags);
50 for_each_cpu(query_cpu, mask) {
51 if (query_cpu == this_cpu)
52 continue;
53 __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
54 query_cpu), vector, APIC_DEST_PHYSICAL);
55 }
56 local_irq_restore(flags);
57}
58
59void default_send_IPI_mask_sequence_logical(const struct cpumask *mask,
60 int vector)
61{
62 unsigned long flags;
63 unsigned int query_cpu;
64
65 /*
66 * Hack. The clustered APIC addressing mode doesn't allow us to send
67 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
68 * should be modified to do 1 message per cluster ID - mbligh
69 */
70
71 local_irq_save(flags);
72 for_each_cpu(query_cpu, mask)
73 __default_send_IPI_dest_field(
74 apic->cpu_to_logical_apicid(query_cpu), vector,
75 apic->dest_logical);
76 local_irq_restore(flags);
77}
78
79void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask,
80 int vector)
81{
82 unsigned long flags;
83 unsigned int query_cpu;
84 unsigned int this_cpu = smp_processor_id();
85
86 /* See Hack comment above */
87
88 local_irq_save(flags);
89 for_each_cpu(query_cpu, mask) {
90 if (query_cpu == this_cpu)
91 continue;
92 __default_send_IPI_dest_field(
93 apic->cpu_to_logical_apicid(query_cpu), vector,
94 apic->dest_logical);
95 }
96 local_irq_restore(flags);
97}
98
99#ifdef CONFIG_X86_32
100
101/*
102 * This is only used on smaller machines.
103 */
104void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vector)
105{
106 unsigned long mask = cpumask_bits(cpumask)[0];
107 unsigned long flags;
108
109 local_irq_save(flags);
110 WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]);
111 __default_send_IPI_dest_field(mask, vector, apic->dest_logical);
112 local_irq_restore(flags);
113}
114
115void default_send_IPI_allbutself(int vector)
116{
117 /*
118 * if there are no other CPUs in the system then we get an APIC send
119 * error if we try to broadcast, thus avoid sending IPIs in this case.
120 */
121 if (!(num_online_cpus() > 1))
122 return;
123
124 __default_local_send_IPI_allbutself(vector);
125}
126
127void default_send_IPI_all(int vector)
128{
129 __default_local_send_IPI_all(vector);
130}
131
132void default_send_IPI_self(int vector)
133{
134 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, apic->dest_logical);
135}
136
137/* must come after the send_IPI functions above for inlining */
138static int convert_apicid_to_cpu(int apic_id)
139{
140 int i;
141
142 for_each_possible_cpu(i) {
143 if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
144 return i;
145 }
146 return -1;
147}
148
149int safe_smp_processor_id(void)
150{
151 int apicid, cpuid;
152
153 if (!boot_cpu_has(X86_FEATURE_APIC))
154 return 0;
155
156 apicid = hard_smp_processor_id();
157 if (apicid == BAD_APICID)
158 return 0;
159
160 cpuid = convert_apicid_to_cpu(apicid);
161
162 return cpuid >= 0 ? cpuid : 0;
163}
164#endif
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
new file mode 100644
index 000000000000..d6bd62407152
--- /dev/null
+++ b/arch/x86/kernel/apic/nmi.c
@@ -0,0 +1,565 @@
1/*
2 * NMI watchdog support on APIC systems
3 *
4 * Started by Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes:
7 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
8 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
9 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
10 * Pavel Machek and
11 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
12 */
13
14#include <asm/apic.h>
15
16#include <linux/nmi.h>
17#include <linux/mm.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/sysdev.h>
22#include <linux/sysctl.h>
23#include <linux/percpu.h>
24#include <linux/kprobes.h>
25#include <linux/cpumask.h>
26#include <linux/kernel_stat.h>
27#include <linux/kdebug.h>
28#include <linux/smp.h>
29
30#include <asm/i8259.h>
31#include <asm/io_apic.h>
32#include <asm/proto.h>
33#include <asm/timer.h>
34
35#include <asm/mce.h>
36
37#include <asm/mach_traps.h>
38
39int unknown_nmi_panic;
40int nmi_watchdog_enabled;
41
42static cpumask_var_t backtrace_mask;
43
44/* nmi_active:
45 * >0: the lapic NMI watchdog is active, but can be disabled
46 * <0: the lapic NMI watchdog has not been set up, and cannot
47 * be enabled
48 * 0: the lapic NMI watchdog is disabled, but can be enabled
49 */
50atomic_t nmi_active = ATOMIC_INIT(0); /* oprofile uses this */
51EXPORT_SYMBOL(nmi_active);
52
53unsigned int nmi_watchdog = NMI_NONE;
54EXPORT_SYMBOL(nmi_watchdog);
55
56static int panic_on_timeout;
57
58static unsigned int nmi_hz = HZ;
59static DEFINE_PER_CPU(short, wd_enabled);
60static int endflag __initdata;
61
62static inline unsigned int get_nmi_count(int cpu)
63{
64 return per_cpu(irq_stat, cpu).__nmi_count;
65}
66
67static inline int mce_in_progress(void)
68{
69#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE)
70 return atomic_read(&mce_entry) > 0;
71#endif
72 return 0;
73}
74
75/*
76 * Take the local apic timer and PIT/HPET into account. We don't
77 * know which one is active, when we have highres/dyntick on
78 */
79static inline unsigned int get_timer_irqs(int cpu)
80{
81 return per_cpu(irq_stat, cpu).apic_timer_irqs +
82 per_cpu(irq_stat, cpu).irq0_irqs;
83}
84
85#ifdef CONFIG_SMP
86/*
87 * The performance counters used by NMI_LOCAL_APIC don't trigger when
88 * the CPU is idle. To make sure the NMI watchdog really ticks on all
89 * CPUs during the test make them busy.
90 */
91static __init void nmi_cpu_busy(void *data)
92{
93 local_irq_enable_in_hardirq();
94 /*
95 * Intentionally don't use cpu_relax here. This is
96 * to make sure that the performance counter really ticks,
97 * even if there is a simulator or similar that catches the
98 * pause instruction. On a real HT machine this is fine because
99 * all other CPUs are busy with "useless" delay loops and don't
100 * care if they get somewhat less cycles.
101 */
102 while (endflag == 0)
103 mb();
104}
105#endif
106
107static void report_broken_nmi(int cpu, int *prev_nmi_count)
108{
109 printk(KERN_CONT "\n");
110
111 printk(KERN_WARNING
112 "WARNING: CPU#%d: NMI appears to be stuck (%d->%d)!\n",
113 cpu, prev_nmi_count[cpu], get_nmi_count(cpu));
114
115 printk(KERN_WARNING
116 "Please report this to bugzilla.kernel.org,\n");
117 printk(KERN_WARNING
118 "and attach the output of the 'dmesg' command.\n");
119
120 per_cpu(wd_enabled, cpu) = 0;
121 atomic_dec(&nmi_active);
122}
123
124static void __acpi_nmi_disable(void *__unused)
125{
126 apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
127}
128
129int __init check_nmi_watchdog(void)
130{
131 unsigned int *prev_nmi_count;
132 int cpu;
133
134 if (!nmi_watchdog_active() || !atomic_read(&nmi_active))
135 return 0;
136
137 prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(int), GFP_KERNEL);
138 if (!prev_nmi_count)
139 goto error;
140
141 alloc_cpumask_var(&backtrace_mask, GFP_KERNEL);
142 printk(KERN_INFO "Testing NMI watchdog ... ");
143
144#ifdef CONFIG_SMP
145 if (nmi_watchdog == NMI_LOCAL_APIC)
146 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0);
147#endif
148
149 for_each_possible_cpu(cpu)
150 prev_nmi_count[cpu] = get_nmi_count(cpu);
151 local_irq_enable();
152 mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */
153
154 for_each_online_cpu(cpu) {
155 if (!per_cpu(wd_enabled, cpu))
156 continue;
157 if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
158 report_broken_nmi(cpu, prev_nmi_count);
159 }
160 endflag = 1;
161 if (!atomic_read(&nmi_active)) {
162 kfree(prev_nmi_count);
163 atomic_set(&nmi_active, -1);
164 goto error;
165 }
166 printk("OK.\n");
167
168 /*
169 * now that we know it works we can reduce NMI frequency to
170 * something more reasonable; makes a difference in some configs
171 */
172 if (nmi_watchdog == NMI_LOCAL_APIC)
173 nmi_hz = lapic_adjust_nmi_hz(1);
174
175 kfree(prev_nmi_count);
176 return 0;
177error:
178 if (nmi_watchdog == NMI_IO_APIC) {
179 if (!timer_through_8259)
180 disable_8259A_irq(0);
181 on_each_cpu(__acpi_nmi_disable, NULL, 1);
182 }
183
184#ifdef CONFIG_X86_32
185 timer_ack = 0;
186#endif
187 return -1;
188}
189
190static int __init setup_nmi_watchdog(char *str)
191{
192 unsigned int nmi;
193
194 if (!strncmp(str, "panic", 5)) {
195 panic_on_timeout = 1;
196 str = strchr(str, ',');
197 if (!str)
198 return 1;
199 ++str;
200 }
201
202 if (!strncmp(str, "lapic", 5))
203 nmi_watchdog = NMI_LOCAL_APIC;
204 else if (!strncmp(str, "ioapic", 6))
205 nmi_watchdog = NMI_IO_APIC;
206 else {
207 get_option(&str, &nmi);
208 if (nmi >= NMI_INVALID)
209 return 0;
210 nmi_watchdog = nmi;
211 }
212
213 return 1;
214}
215__setup("nmi_watchdog=", setup_nmi_watchdog);
216
217/*
218 * Suspend/resume support
219 */
220#ifdef CONFIG_PM
221
222static int nmi_pm_active; /* nmi_active before suspend */
223
224static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
225{
226 /* only CPU0 goes here, other CPUs should be offline */
227 nmi_pm_active = atomic_read(&nmi_active);
228 stop_apic_nmi_watchdog(NULL);
229 BUG_ON(atomic_read(&nmi_active) != 0);
230 return 0;
231}
232
233static int lapic_nmi_resume(struct sys_device *dev)
234{
235 /* only CPU0 goes here, other CPUs should be offline */
236 if (nmi_pm_active > 0) {
237 setup_apic_nmi_watchdog(NULL);
238 touch_nmi_watchdog();
239 }
240 return 0;
241}
242
243static struct sysdev_class nmi_sysclass = {
244 .name = "lapic_nmi",
245 .resume = lapic_nmi_resume,
246 .suspend = lapic_nmi_suspend,
247};
248
249static struct sys_device device_lapic_nmi = {
250 .id = 0,
251 .cls = &nmi_sysclass,
252};
253
254static int __init init_lapic_nmi_sysfs(void)
255{
256 int error;
257
258 /*
259 * should really be a BUG_ON but b/c this is an
260 * init call, it just doesn't work. -dcz
261 */
262 if (nmi_watchdog != NMI_LOCAL_APIC)
263 return 0;
264
265 if (atomic_read(&nmi_active) < 0)
266 return 0;
267
268 error = sysdev_class_register(&nmi_sysclass);
269 if (!error)
270 error = sysdev_register(&device_lapic_nmi);
271 return error;
272}
273
274/* must come after the local APIC's device_initcall() */
275late_initcall(init_lapic_nmi_sysfs);
276
277#endif /* CONFIG_PM */
278
279static void __acpi_nmi_enable(void *__unused)
280{
281 apic_write(APIC_LVT0, APIC_DM_NMI);
282}
283
284/*
285 * Enable timer based NMIs on all CPUs:
286 */
287void acpi_nmi_enable(void)
288{
289 if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
290 on_each_cpu(__acpi_nmi_enable, NULL, 1);
291}
292
293/*
294 * Disable timer based NMIs on all CPUs:
295 */
296void acpi_nmi_disable(void)
297{
298 if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
299 on_each_cpu(__acpi_nmi_disable, NULL, 1);
300}
301
302/*
303 * This function is called as soon the LAPIC NMI watchdog driver has everything
304 * in place and it's ready to check if the NMIs belong to the NMI watchdog
305 */
306void cpu_nmi_set_wd_enabled(void)
307{
308 __get_cpu_var(wd_enabled) = 1;
309}
310
311void setup_apic_nmi_watchdog(void *unused)
312{
313 if (__get_cpu_var(wd_enabled))
314 return;
315
316 /* cheap hack to support suspend/resume */
317 /* if cpu0 is not active neither should the other cpus */
318 if (smp_processor_id() != 0 && atomic_read(&nmi_active) <= 0)
319 return;
320
321 switch (nmi_watchdog) {
322 case NMI_LOCAL_APIC:
323 if (lapic_watchdog_init(nmi_hz) < 0) {
324 __get_cpu_var(wd_enabled) = 0;
325 return;
326 }
327 /* FALL THROUGH */
328 case NMI_IO_APIC:
329 __get_cpu_var(wd_enabled) = 1;
330 atomic_inc(&nmi_active);
331 }
332}
333
334void stop_apic_nmi_watchdog(void *unused)
335{
336 /* only support LOCAL and IO APICs for now */
337 if (!nmi_watchdog_active())
338 return;
339 if (__get_cpu_var(wd_enabled) == 0)
340 return;
341 if (nmi_watchdog == NMI_LOCAL_APIC)
342 lapic_watchdog_stop();
343 else
344 __acpi_nmi_disable(NULL);
345 __get_cpu_var(wd_enabled) = 0;
346 atomic_dec(&nmi_active);
347}
348
349/*
350 * the best way to detect whether a CPU has a 'hard lockup' problem
351 * is to check it's local APIC timer IRQ counts. If they are not
352 * changing then that CPU has some problem.
353 *
354 * as these watchdog NMI IRQs are generated on every CPU, we only
355 * have to check the current processor.
356 *
357 * since NMIs don't listen to _any_ locks, we have to be extremely
358 * careful not to rely on unsafe variables. The printk might lock
359 * up though, so we have to break up any console locks first ...
360 * [when there will be more tty-related locks, break them up here too!]
361 */
362
363static DEFINE_PER_CPU(unsigned, last_irq_sum);
364static DEFINE_PER_CPU(local_t, alert_counter);
365static DEFINE_PER_CPU(int, nmi_touch);
366
367void touch_nmi_watchdog(void)
368{
369 if (nmi_watchdog_active()) {
370 unsigned cpu;
371
372 /*
373 * Tell other CPUs to reset their alert counters. We cannot
374 * do it ourselves because the alert count increase is not
375 * atomic.
376 */
377 for_each_present_cpu(cpu) {
378 if (per_cpu(nmi_touch, cpu) != 1)
379 per_cpu(nmi_touch, cpu) = 1;
380 }
381 }
382
383 /*
384 * Tickle the softlockup detector too:
385 */
386 touch_softlockup_watchdog();
387}
388EXPORT_SYMBOL(touch_nmi_watchdog);
389
390notrace __kprobes int
391nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
392{
393 /*
394 * Since current_thread_info()-> is always on the stack, and we
395 * always switch the stack NMI-atomically, it's safe to use
396 * smp_processor_id().
397 */
398 unsigned int sum;
399 int touched = 0;
400 int cpu = smp_processor_id();
401 int rc = 0;
402
403 /* check for other users first */
404 if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
405 == NOTIFY_STOP) {
406 rc = 1;
407 touched = 1;
408 }
409
410 sum = get_timer_irqs(cpu);
411
412 if (__get_cpu_var(nmi_touch)) {
413 __get_cpu_var(nmi_touch) = 0;
414 touched = 1;
415 }
416
417 if (cpumask_test_cpu(cpu, backtrace_mask)) {
418 static DEFINE_SPINLOCK(lock); /* Serialise the printks */
419
420 spin_lock(&lock);
421 printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
422 dump_stack();
423 spin_unlock(&lock);
424 cpumask_clear_cpu(cpu, backtrace_mask);
425 }
426
427 /* Could check oops_in_progress here too, but it's safer not to */
428 if (mce_in_progress())
429 touched = 1;
430
431 /* if the none of the timers isn't firing, this cpu isn't doing much */
432 if (!touched && __get_cpu_var(last_irq_sum) == sum) {
433 /*
434 * Ayiee, looks like this CPU is stuck ...
435 * wait a few IRQs (5 seconds) before doing the oops ...
436 */
437 local_inc(&__get_cpu_var(alert_counter));
438 if (local_read(&__get_cpu_var(alert_counter)) == 5 * nmi_hz)
439 /*
440 * die_nmi will return ONLY if NOTIFY_STOP happens..
441 */
442 die_nmi("BUG: NMI Watchdog detected LOCKUP",
443 regs, panic_on_timeout);
444 } else {
445 __get_cpu_var(last_irq_sum) = sum;
446 local_set(&__get_cpu_var(alert_counter), 0);
447 }
448
449 /* see if the nmi watchdog went off */
450 if (!__get_cpu_var(wd_enabled))
451 return rc;
452 switch (nmi_watchdog) {
453 case NMI_LOCAL_APIC:
454 rc |= lapic_wd_event(nmi_hz);
455 break;
456 case NMI_IO_APIC:
457 /*
458 * don't know how to accurately check for this.
459 * just assume it was a watchdog timer interrupt
460 * This matches the old behaviour.
461 */
462 rc = 1;
463 break;
464 }
465 return rc;
466}
467
468#ifdef CONFIG_SYSCTL
469
470static void enable_ioapic_nmi_watchdog_single(void *unused)
471{
472 __get_cpu_var(wd_enabled) = 1;
473 atomic_inc(&nmi_active);
474 __acpi_nmi_enable(NULL);
475}
476
477static void enable_ioapic_nmi_watchdog(void)
478{
479 on_each_cpu(enable_ioapic_nmi_watchdog_single, NULL, 1);
480 touch_nmi_watchdog();
481}
482
483static void disable_ioapic_nmi_watchdog(void)
484{
485 on_each_cpu(stop_apic_nmi_watchdog, NULL, 1);
486}
487
488static int __init setup_unknown_nmi_panic(char *str)
489{
490 unknown_nmi_panic = 1;
491 return 1;
492}
493__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
494
495static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
496{
497 unsigned char reason = get_nmi_reason();
498 char buf[64];
499
500 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
501 die_nmi(buf, regs, 1); /* Always panic here */
502 return 0;
503}
504
505/*
506 * proc handler for /proc/sys/kernel/nmi
507 */
508int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
509 void __user *buffer, size_t *length, loff_t *ppos)
510{
511 int old_state;
512
513 nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
514 old_state = nmi_watchdog_enabled;
515 proc_dointvec(table, write, file, buffer, length, ppos);
516 if (!!old_state == !!nmi_watchdog_enabled)
517 return 0;
518
519 if (atomic_read(&nmi_active) < 0 || !nmi_watchdog_active()) {
520 printk(KERN_WARNING
521 "NMI watchdog is permanently disabled\n");
522 return -EIO;
523 }
524
525 if (nmi_watchdog == NMI_LOCAL_APIC) {
526 if (nmi_watchdog_enabled)
527 enable_lapic_nmi_watchdog();
528 else
529 disable_lapic_nmi_watchdog();
530 } else if (nmi_watchdog == NMI_IO_APIC) {
531 if (nmi_watchdog_enabled)
532 enable_ioapic_nmi_watchdog();
533 else
534 disable_ioapic_nmi_watchdog();
535 } else {
536 printk(KERN_WARNING
537 "NMI watchdog doesn't know what hardware to touch\n");
538 return -EIO;
539 }
540 return 0;
541}
542
543#endif /* CONFIG_SYSCTL */
544
545int do_nmi_callback(struct pt_regs *regs, int cpu)
546{
547#ifdef CONFIG_SYSCTL
548 if (unknown_nmi_panic)
549 return unknown_nmi_panic_callback(regs, cpu);
550#endif
551 return 0;
552}
553
554void __trigger_all_cpu_backtrace(void)
555{
556 int i;
557
558 cpumask_copy(backtrace_mask, cpu_online_mask);
559 /* Wait for up to 10 seconds for all CPUs to do the backtrace */
560 for (i = 0; i < 10 * 1000; i++) {
561 if (cpumask_empty(backtrace_mask))
562 break;
563 mdelay(1);
564 }
565}
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
new file mode 100644
index 000000000000..533e59c6fc82
--- /dev/null
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -0,0 +1,558 @@
1/*
2 * Written by: Patricia Gaughen, IBM Corporation
3 *
4 * Copyright (C) 2002, IBM Corp.
5 * Copyright (C) 2009, Red Hat, Inc., Ingo Molnar
6 *
7 * All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
17 * NON INFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 * Send feedback to <gone@us.ibm.com>
25 */
26#include <linux/nodemask.h>
27#include <linux/topology.h>
28#include <linux/bootmem.h>
29#include <linux/threads.h>
30#include <linux/cpumask.h>
31#include <linux/kernel.h>
32#include <linux/mmzone.h>
33#include <linux/module.h>
34#include <linux/string.h>
35#include <linux/init.h>
36#include <linux/numa.h>
37#include <linux/smp.h>
38#include <linux/io.h>
39#include <linux/mm.h>
40
41#include <asm/processor.h>
42#include <asm/fixmap.h>
43#include <asm/mpspec.h>
44#include <asm/numaq.h>
45#include <asm/setup.h>
46#include <asm/apic.h>
47#include <asm/e820.h>
48#include <asm/ipi.h>
49
50#define MB_TO_PAGES(addr) ((addr) << (20 - PAGE_SHIFT))
51
52int found_numaq;
53
54/*
55 * Have to match translation table entries to main table entries by counter
56 * hence the mpc_record variable .... can't see a less disgusting way of
57 * doing this ....
58 */
59struct mpc_trans {
60 unsigned char mpc_type;
61 unsigned char trans_len;
62 unsigned char trans_type;
63 unsigned char trans_quad;
64 unsigned char trans_global;
65 unsigned char trans_local;
66 unsigned short trans_reserved;
67};
68
69/* x86_quirks member */
70static int mpc_record;
71
72static struct mpc_trans *translation_table[MAX_MPC_ENTRY];
73
74int mp_bus_id_to_node[MAX_MP_BUSSES];
75int mp_bus_id_to_local[MAX_MP_BUSSES];
76int quad_local_to_mp_bus_id[NR_CPUS/4][4];
77
78
79static inline void numaq_register_node(int node, struct sys_cfg_data *scd)
80{
81 struct eachquadmem *eq = scd->eq + node;
82
83 node_set_online(node);
84
85 /* Convert to pages */
86 node_start_pfn[node] =
87 MB_TO_PAGES(eq->hi_shrd_mem_start - eq->priv_mem_size);
88
89 node_end_pfn[node] =
90 MB_TO_PAGES(eq->hi_shrd_mem_start + eq->hi_shrd_mem_size);
91
92 e820_register_active_regions(node, node_start_pfn[node],
93 node_end_pfn[node]);
94
95 memory_present(node, node_start_pfn[node], node_end_pfn[node]);
96
97 node_remap_size[node] = node_memmap_size_bytes(node,
98 node_start_pfn[node],
99 node_end_pfn[node]);
100}
101
102/*
103 * Function: smp_dump_qct()
104 *
105 * Description: gets memory layout from the quad config table. This
106 * function also updates node_online_map with the nodes (quads) present.
107 */
108static void __init smp_dump_qct(void)
109{
110 struct sys_cfg_data *scd;
111 int node;
112
113 scd = (void *)__va(SYS_CFG_DATA_PRIV_ADDR);
114
115 nodes_clear(node_online_map);
116 for_each_node(node) {
117 if (scd->quads_present31_0 & (1 << node))
118 numaq_register_node(node, scd);
119 }
120}
121
122void __cpuinit numaq_tsc_disable(void)
123{
124 if (!found_numaq)
125 return;
126
127 if (num_online_nodes() > 1) {
128 printk(KERN_DEBUG "NUMAQ: disabling TSC\n");
129 setup_clear_cpu_cap(X86_FEATURE_TSC);
130 }
131}
132
133static int __init numaq_pre_time_init(void)
134{
135 numaq_tsc_disable();
136 return 0;
137}
138
139static inline int generate_logical_apicid(int quad, int phys_apicid)
140{
141 return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
142}
143
144/* x86_quirks member */
145static int mpc_apic_id(struct mpc_cpu *m)
146{
147 int quad = translation_table[mpc_record]->trans_quad;
148 int logical_apicid = generate_logical_apicid(quad, m->apicid);
149
150 printk(KERN_DEBUG
151 "Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
152 m->apicid, (m->cpufeature & CPU_FAMILY_MASK) >> 8,
153 (m->cpufeature & CPU_MODEL_MASK) >> 4,
154 m->apicver, quad, logical_apicid);
155
156 return logical_apicid;
157}
158
159/* x86_quirks member */
160static void mpc_oem_bus_info(struct mpc_bus *m, char *name)
161{
162 int quad = translation_table[mpc_record]->trans_quad;
163 int local = translation_table[mpc_record]->trans_local;
164
165 mp_bus_id_to_node[m->busid] = quad;
166 mp_bus_id_to_local[m->busid] = local;
167
168 printk(KERN_INFO "Bus #%d is %s (node %d)\n", m->busid, name, quad);
169}
170
171/* x86_quirks member */
172static void mpc_oem_pci_bus(struct mpc_bus *m)
173{
174 int quad = translation_table[mpc_record]->trans_quad;
175 int local = translation_table[mpc_record]->trans_local;
176
177 quad_local_to_mp_bus_id[quad][local] = m->busid;
178}
179
180static void __init MP_translation_info(struct mpc_trans *m)
181{
182 printk(KERN_INFO
183 "Translation: record %d, type %d, quad %d, global %d, local %d\n",
184 mpc_record, m->trans_type, m->trans_quad, m->trans_global,
185 m->trans_local);
186
187 if (mpc_record >= MAX_MPC_ENTRY)
188 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
189 else
190 translation_table[mpc_record] = m; /* stash this for later */
191
192 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
193 node_set_online(m->trans_quad);
194}
195
196static int __init mpf_checksum(unsigned char *mp, int len)
197{
198 int sum = 0;
199
200 while (len--)
201 sum += *mp++;
202
203 return sum & 0xFF;
204}
205
206/*
207 * Read/parse the MPC oem tables
208 */
209static void __init
210 smp_read_mpc_oem(struct mpc_oemtable *oemtable, unsigned short oemsize)
211{
212 int count = sizeof(*oemtable); /* the header size */
213 unsigned char *oemptr = ((unsigned char *)oemtable) + count;
214
215 mpc_record = 0;
216 printk(KERN_INFO
217 "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
218
219 if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
220 printk(KERN_WARNING
221 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
222 oemtable->signature[0], oemtable->signature[1],
223 oemtable->signature[2], oemtable->signature[3]);
224 return;
225 }
226
227 if (mpf_checksum((unsigned char *)oemtable, oemtable->length)) {
228 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
229 return;
230 }
231
232 while (count < oemtable->length) {
233 switch (*oemptr) {
234 case MP_TRANSLATION:
235 {
236 struct mpc_trans *m = (void *)oemptr;
237
238 MP_translation_info(m);
239 oemptr += sizeof(*m);
240 count += sizeof(*m);
241 ++mpc_record;
242 break;
243 }
244 default:
245 printk(KERN_WARNING
246 "Unrecognised OEM table entry type! - %d\n",
247 (int)*oemptr);
248 return;
249 }
250 }
251}
252
253static int __init numaq_setup_ioapic_ids(void)
254{
255 /* so can skip it */
256 return 1;
257}
258
259static struct x86_quirks numaq_x86_quirks __initdata = {
260 .arch_pre_time_init = numaq_pre_time_init,
261 .arch_time_init = NULL,
262 .arch_pre_intr_init = NULL,
263 .arch_memory_setup = NULL,
264 .arch_intr_init = NULL,
265 .arch_trap_init = NULL,
266 .mach_get_smp_config = NULL,
267 .mach_find_smp_config = NULL,
268 .mpc_record = &mpc_record,
269 .mpc_apic_id = mpc_apic_id,
270 .mpc_oem_bus_info = mpc_oem_bus_info,
271 .mpc_oem_pci_bus = mpc_oem_pci_bus,
272 .smp_read_mpc_oem = smp_read_mpc_oem,
273 .setup_ioapic_ids = numaq_setup_ioapic_ids,
274};
275
276static __init void early_check_numaq(void)
277{
278 /*
279 * Find possible boot-time SMP configuration:
280 */
281 early_find_smp_config();
282
283 /*
284 * get boot-time SMP configuration:
285 */
286 if (smp_found_config)
287 early_get_smp_config();
288
289 if (found_numaq)
290 x86_quirks = &numaq_x86_quirks;
291}
292
293int __init get_memcfg_numaq(void)
294{
295 early_check_numaq();
296 if (!found_numaq)
297 return 0;
298 smp_dump_qct();
299
300 return 1;
301}
302
303#define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
304
305static inline unsigned int numaq_get_apic_id(unsigned long x)
306{
307 return (x >> 24) & 0x0F;
308}
309
310static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
311{
312 default_send_IPI_mask_sequence_logical(mask, vector);
313}
314
315static inline void numaq_send_IPI_allbutself(int vector)
316{
317 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
318}
319
320static inline void numaq_send_IPI_all(int vector)
321{
322 numaq_send_IPI_mask(cpu_online_mask, vector);
323}
324
325#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
326#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
327
328/*
329 * Because we use NMIs rather than the INIT-STARTUP sequence to
330 * bootstrap the CPUs, the APIC may be in a weird state. Kick it:
331 */
332static inline void numaq_smp_callin_clear_local_apic(void)
333{
334 clear_local_APIC();
335}
336
337static inline const struct cpumask *numaq_target_cpus(void)
338{
339 return cpu_all_mask;
340}
341
342static inline unsigned long
343numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
344{
345 return physid_isset(apicid, bitmap);
346}
347
348static inline unsigned long numaq_check_apicid_present(int bit)
349{
350 return physid_isset(bit, phys_cpu_present_map);
351}
352
353static inline int numaq_apic_id_registered(void)
354{
355 return 1;
356}
357
358static inline void numaq_init_apic_ldr(void)
359{
360 /* Already done in NUMA-Q firmware */
361}
362
363static inline void numaq_setup_apic_routing(void)
364{
365 printk(KERN_INFO
366 "Enabling APIC mode: NUMA-Q. Using %d I/O APICs\n",
367 nr_ioapics);
368}
369
370/*
371 * Skip adding the timer int on secondary nodes, which causes
372 * a small but painful rift in the time-space continuum.
373 */
374static inline int numaq_multi_timer_check(int apic, int irq)
375{
376 return apic != 0 && irq == 0;
377}
378
379static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
380{
381 /* We don't have a good way to do this yet - hack */
382 return physids_promote(0xFUL);
383}
384
385static inline int numaq_cpu_to_logical_apicid(int cpu)
386{
387 if (cpu >= nr_cpu_ids)
388 return BAD_APICID;
389 return cpu_2_logical_apicid[cpu];
390}
391
392/*
393 * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
394 * cpu to APIC ID relation to properly interact with the intelligent
395 * mode of the cluster controller.
396 */
397static inline int numaq_cpu_present_to_apicid(int mps_cpu)
398{
399 if (mps_cpu < 60)
400 return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
401 else
402 return BAD_APICID;
403}
404
405static inline int numaq_apicid_to_node(int logical_apicid)
406{
407 return logical_apicid >> 4;
408}
409
410static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
411{
412 int node = numaq_apicid_to_node(logical_apicid);
413 int cpu = __ffs(logical_apicid & 0xf);
414
415 return physid_mask_of_physid(cpu + 4*node);
416}
417
418/* Where the IO area was mapped on multiquad, always 0 otherwise */
419void *xquad_portio;
420
421static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
422{
423 return 1;
424}
425
426/*
427 * We use physical apicids here, not logical, so just return the default
428 * physical broadcast to stop people from breaking us
429 */
430static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask)
431{
432 return 0x0F;
433}
434
435static inline unsigned int
436numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
437 const struct cpumask *andmask)
438{
439 return 0x0F;
440}
441
442/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
443static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
444{
445 return cpuid_apic >> index_msb;
446}
447
448static int
449numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
450{
451 if (strncmp(oem, "IBM NUMA", 8))
452 printk(KERN_ERR "Warning! Not a NUMA-Q system!\n");
453 else
454 found_numaq = 1;
455
456 return found_numaq;
457}
458
459static int probe_numaq(void)
460{
461 /* already know from get_memcfg_numaq() */
462 return found_numaq;
463}
464
465static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask)
466{
467 /* Careful. Some cpus do not strictly honor the set of cpus
468 * specified in the interrupt destination when using lowest
469 * priority interrupt delivery mode.
470 *
471 * In particular there was a hyperthreading cpu observed to
472 * deliver interrupts to the wrong hyperthread when only one
473 * hyperthread was specified in the interrupt desitination.
474 */
475 cpumask_clear(retmask);
476 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
477}
478
479static void numaq_setup_portio_remap(void)
480{
481 int num_quads = num_online_nodes();
482
483 if (num_quads <= 1)
484 return;
485
486 printk(KERN_INFO
487 "Remapping cross-quad port I/O for %d quads\n", num_quads);
488
489 xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
490
491 printk(KERN_INFO
492 "xquad_portio vaddr 0x%08lx, len %08lx\n",
493 (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
494}
495
496struct apic apic_numaq = {
497
498 .name = "NUMAQ",
499 .probe = probe_numaq,
500 .acpi_madt_oem_check = NULL,
501 .apic_id_registered = numaq_apic_id_registered,
502
503 .irq_delivery_mode = dest_LowestPrio,
504 /* physical delivery on LOCAL quad: */
505 .irq_dest_mode = 0,
506
507 .target_cpus = numaq_target_cpus,
508 .disable_esr = 1,
509 .dest_logical = APIC_DEST_LOGICAL,
510 .check_apicid_used = numaq_check_apicid_used,
511 .check_apicid_present = numaq_check_apicid_present,
512
513 .vector_allocation_domain = numaq_vector_allocation_domain,
514 .init_apic_ldr = numaq_init_apic_ldr,
515
516 .ioapic_phys_id_map = numaq_ioapic_phys_id_map,
517 .setup_apic_routing = numaq_setup_apic_routing,
518 .multi_timer_check = numaq_multi_timer_check,
519 .apicid_to_node = numaq_apicid_to_node,
520 .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid,
521 .cpu_present_to_apicid = numaq_cpu_present_to_apicid,
522 .apicid_to_cpu_present = numaq_apicid_to_cpu_present,
523 .setup_portio_remap = numaq_setup_portio_remap,
524 .check_phys_apicid_present = numaq_check_phys_apicid_present,
525 .enable_apic_mode = NULL,
526 .phys_pkg_id = numaq_phys_pkg_id,
527 .mps_oem_check = numaq_mps_oem_check,
528
529 .get_apic_id = numaq_get_apic_id,
530 .set_apic_id = NULL,
531 .apic_id_mask = 0x0F << 24,
532
533 .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid,
534 .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and,
535
536 .send_IPI_mask = numaq_send_IPI_mask,
537 .send_IPI_mask_allbutself = NULL,
538 .send_IPI_allbutself = numaq_send_IPI_allbutself,
539 .send_IPI_all = numaq_send_IPI_all,
540 .send_IPI_self = default_send_IPI_self,
541
542 .wakeup_secondary_cpu = wakeup_secondary_cpu_via_nmi,
543 .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW,
544 .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH,
545
546 /* We don't do anything here because we use NMI's to boot instead */
547 .wait_for_init_deassert = NULL,
548
549 .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic,
550 .inquire_remote_apic = NULL,
551
552 .read = native_apic_mem_read,
553 .write = native_apic_mem_write,
554 .icr_read = native_apic_icr_read,
555 .icr_write = native_apic_icr_write,
556 .wait_icr_idle = native_apic_wait_icr_idle,
557 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
558};
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
new file mode 100644
index 000000000000..01eda2ac65e4
--- /dev/null
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -0,0 +1,285 @@
1/*
2 * Default generic APIC driver. This handles up to 8 CPUs.
3 *
4 * Copyright 2003 Andi Kleen, SuSE Labs.
5 * Subject to the GNU Public License, v.2
6 *
7 * Generic x86 APIC driver probe layer.
8 */
9#include <linux/threads.h>
10#include <linux/cpumask.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/ctype.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <asm/fixmap.h>
18#include <asm/mpspec.h>
19#include <asm/apicdef.h>
20#include <asm/apic.h>
21#include <asm/setup.h>
22
23#include <linux/threads.h>
24#include <linux/cpumask.h>
25#include <asm/mpspec.h>
26#include <asm/fixmap.h>
27#include <asm/apicdef.h>
28#include <linux/kernel.h>
29#include <linux/string.h>
30#include <linux/smp.h>
31#include <linux/init.h>
32#include <asm/ipi.h>
33
34#include <linux/smp.h>
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <asm/acpi.h>
38#include <asm/e820.h>
39#include <asm/setup.h>
40
41#ifdef CONFIG_HOTPLUG_CPU
42#define DEFAULT_SEND_IPI (1)
43#else
44#define DEFAULT_SEND_IPI (0)
45#endif
46
47int no_broadcast = DEFAULT_SEND_IPI;
48
49static __init int no_ipi_broadcast(char *str)
50{
51 get_option(&str, &no_broadcast);
52 pr_info("Using %s mode\n",
53 no_broadcast ? "No IPI Broadcast" : "IPI Broadcast");
54 return 1;
55}
56__setup("no_ipi_broadcast=", no_ipi_broadcast);
57
58static int __init print_ipi_mode(void)
59{
60 pr_info("Using IPI %s mode\n",
61 no_broadcast ? "No-Shortcut" : "Shortcut");
62 return 0;
63}
64late_initcall(print_ipi_mode);
65
66void default_setup_apic_routing(void)
67{
68#ifdef CONFIG_X86_IO_APIC
69 printk(KERN_INFO
70 "Enabling APIC mode: Flat. Using %d I/O APICs\n",
71 nr_ioapics);
72#endif
73}
74
75static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
76{
77 /*
78 * Careful. Some cpus do not strictly honor the set of cpus
79 * specified in the interrupt destination when using lowest
80 * priority interrupt delivery mode.
81 *
82 * In particular there was a hyperthreading cpu observed to
83 * deliver interrupts to the wrong hyperthread when only one
84 * hyperthread was specified in the interrupt desitination.
85 */
86 cpumask_clear(retmask);
87 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
88}
89
90/* should be called last. */
91static int probe_default(void)
92{
93 return 1;
94}
95
96struct apic apic_default = {
97
98 .name = "default",
99 .probe = probe_default,
100 .acpi_madt_oem_check = NULL,
101 .apic_id_registered = default_apic_id_registered,
102
103 .irq_delivery_mode = dest_LowestPrio,
104 /* logical delivery broadcast to all CPUs: */
105 .irq_dest_mode = 1,
106
107 .target_cpus = default_target_cpus,
108 .disable_esr = 0,
109 .dest_logical = APIC_DEST_LOGICAL,
110 .check_apicid_used = default_check_apicid_used,
111 .check_apicid_present = default_check_apicid_present,
112
113 .vector_allocation_domain = default_vector_allocation_domain,
114 .init_apic_ldr = default_init_apic_ldr,
115
116 .ioapic_phys_id_map = default_ioapic_phys_id_map,
117 .setup_apic_routing = default_setup_apic_routing,
118 .multi_timer_check = NULL,
119 .apicid_to_node = default_apicid_to_node,
120 .cpu_to_logical_apicid = default_cpu_to_logical_apicid,
121 .cpu_present_to_apicid = default_cpu_present_to_apicid,
122 .apicid_to_cpu_present = default_apicid_to_cpu_present,
123 .setup_portio_remap = NULL,
124 .check_phys_apicid_present = default_check_phys_apicid_present,
125 .enable_apic_mode = NULL,
126 .phys_pkg_id = default_phys_pkg_id,
127 .mps_oem_check = NULL,
128
129 .get_apic_id = default_get_apic_id,
130 .set_apic_id = NULL,
131 .apic_id_mask = 0x0F << 24,
132
133 .cpu_mask_to_apicid = default_cpu_mask_to_apicid,
134 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
135
136 .send_IPI_mask = default_send_IPI_mask_logical,
137 .send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical,
138 .send_IPI_allbutself = default_send_IPI_allbutself,
139 .send_IPI_all = default_send_IPI_all,
140 .send_IPI_self = default_send_IPI_self,
141
142 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
143 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
144
145 .wait_for_init_deassert = default_wait_for_init_deassert,
146
147 .smp_callin_clear_local_apic = NULL,
148 .inquire_remote_apic = default_inquire_remote_apic,
149
150 .read = native_apic_mem_read,
151 .write = native_apic_mem_write,
152 .icr_read = native_apic_icr_read,
153 .icr_write = native_apic_icr_write,
154 .wait_icr_idle = native_apic_wait_icr_idle,
155 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
156};
157
158extern struct apic apic_numaq;
159extern struct apic apic_summit;
160extern struct apic apic_bigsmp;
161extern struct apic apic_es7000;
162extern struct apic apic_es7000_cluster;
163extern struct apic apic_default;
164
165struct apic *apic = &apic_default;
166EXPORT_SYMBOL_GPL(apic);
167
168static struct apic *apic_probe[] __initdata = {
169#ifdef CONFIG_X86_NUMAQ
170 &apic_numaq,
171#endif
172#ifdef CONFIG_X86_SUMMIT
173 &apic_summit,
174#endif
175#ifdef CONFIG_X86_BIGSMP
176 &apic_bigsmp,
177#endif
178#ifdef CONFIG_X86_ES7000
179 &apic_es7000,
180 &apic_es7000_cluster,
181#endif
182 &apic_default, /* must be last */
183 NULL,
184};
185
186static int cmdline_apic __initdata;
187static int __init parse_apic(char *arg)
188{
189 int i;
190
191 if (!arg)
192 return -EINVAL;
193
194 for (i = 0; apic_probe[i]; i++) {
195 if (!strcmp(apic_probe[i]->name, arg)) {
196 apic = apic_probe[i];
197 cmdline_apic = 1;
198 return 0;
199 }
200 }
201
202 /* Parsed again by __setup for debug/verbose */
203 return 0;
204}
205early_param("apic", parse_apic);
206
207void __init generic_bigsmp_probe(void)
208{
209#ifdef CONFIG_X86_BIGSMP
210 /*
211 * This routine is used to switch to bigsmp mode when
212 * - There is no apic= option specified by the user
213 * - generic_apic_probe() has chosen apic_default as the sub_arch
214 * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
215 */
216
217 if (!cmdline_apic && apic == &apic_default) {
218 if (apic_bigsmp.probe()) {
219 apic = &apic_bigsmp;
220 printk(KERN_INFO "Overriding APIC driver with %s\n",
221 apic->name);
222 }
223 }
224#endif
225}
226
227void __init generic_apic_probe(void)
228{
229 if (!cmdline_apic) {
230 int i;
231 for (i = 0; apic_probe[i]; i++) {
232 if (apic_probe[i]->probe()) {
233 apic = apic_probe[i];
234 break;
235 }
236 }
237 /* Not visible without early console */
238 if (!apic_probe[i])
239 panic("Didn't find an APIC driver");
240 }
241 printk(KERN_INFO "Using APIC driver %s\n", apic->name);
242}
243
244/* These functions can switch the APIC even after the initial ->probe() */
245
246int __init
247generic_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
248{
249 int i;
250
251 for (i = 0; apic_probe[i]; ++i) {
252 if (!apic_probe[i]->mps_oem_check)
253 continue;
254 if (!apic_probe[i]->mps_oem_check(mpc, oem, productid))
255 continue;
256
257 if (!cmdline_apic) {
258 apic = apic_probe[i];
259 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
260 apic->name);
261 }
262 return 1;
263 }
264 return 0;
265}
266
267int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
268{
269 int i;
270
271 for (i = 0; apic_probe[i]; ++i) {
272 if (!apic_probe[i]->acpi_madt_oem_check)
273 continue;
274 if (!apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id))
275 continue;
276
277 if (!cmdline_apic) {
278 apic = apic_probe[i];
279 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
280 apic->name);
281 }
282 return 1;
283 }
284 return 0;
285}
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
new file mode 100644
index 000000000000..8d7748efe6a8
--- /dev/null
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2004 James Cleverdon, IBM.
3 * Subject to the GNU Public License, v.2
4 *
5 * Generic APIC sub-arch probe layer.
6 *
7 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
9 * James Cleverdon.
10 */
11#include <linux/threads.h>
12#include <linux/cpumask.h>
13#include <linux/string.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/ctype.h>
17#include <linux/init.h>
18#include <linux/hardirq.h>
19#include <linux/dmar.h>
20
21#include <asm/smp.h>
22#include <asm/apic.h>
23#include <asm/ipi.h>
24#include <asm/setup.h>
25
26extern struct apic apic_flat;
27extern struct apic apic_physflat;
28extern struct apic apic_x2xpic_uv_x;
29extern struct apic apic_x2apic_phys;
30extern struct apic apic_x2apic_cluster;
31
32struct apic __read_mostly *apic = &apic_flat;
33EXPORT_SYMBOL_GPL(apic);
34
35static struct apic *apic_probe[] __initdata = {
36#ifdef CONFIG_X86_UV
37 &apic_x2apic_uv_x,
38#endif
39#ifdef CONFIG_X86_X2APIC
40 &apic_x2apic_phys,
41 &apic_x2apic_cluster,
42#endif
43 &apic_physflat,
44 NULL,
45};
46
47/*
48 * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
49 */
50void __init default_setup_apic_routing(void)
51{
52#ifdef CONFIG_X86_X2APIC
53 if (x2apic && (apic != &apic_x2apic_phys &&
54#ifdef CONFIG_X86_UV
55 apic != &apic_x2apic_uv_x &&
56#endif
57 apic != &apic_x2apic_cluster)) {
58 if (x2apic_phys)
59 apic = &apic_x2apic_phys;
60 else
61 apic = &apic_x2apic_cluster;
62 printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
63 }
64#endif
65
66 if (apic == &apic_flat) {
67 if (max_physical_apicid >= 8)
68 apic = &apic_physflat;
69 printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
70 }
71}
72
73/* Same for both flat and physical. */
74
75void apic_send_IPI_self(int vector)
76{
77 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
78}
79
80int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
81{
82 int i;
83
84 for (i = 0; apic_probe[i]; ++i) {
85 if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
86 apic = apic_probe[i];
87 printk(KERN_INFO "Setting APIC routing to %s.\n",
88 apic->name);
89 return 1;
90 }
91 }
92 return 0;
93}
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
new file mode 100644
index 000000000000..9cfe1f415d81
--- /dev/null
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -0,0 +1,576 @@
1/*
2 * IBM Summit-Specific Code
3 *
4 * Written By: Matthew Dobson, IBM Corporation
5 *
6 * Copyright (c) 2003 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <colpatch@us.ibm.com>
26 *
27 */
28
29#include <linux/mm.h>
30#include <linux/init.h>
31#include <asm/io.h>
32#include <asm/bios_ebda.h>
33
34/*
35 * APIC driver for the IBM "Summit" chipset.
36 */
37#include <linux/threads.h>
38#include <linux/cpumask.h>
39#include <asm/mpspec.h>
40#include <asm/apic.h>
41#include <asm/smp.h>
42#include <asm/fixmap.h>
43#include <asm/apicdef.h>
44#include <asm/ipi.h>
45#include <linux/kernel.h>
46#include <linux/string.h>
47#include <linux/init.h>
48#include <linux/gfp.h>
49#include <linux/smp.h>
50
51static unsigned summit_get_apic_id(unsigned long x)
52{
53 return (x >> 24) & 0xFF;
54}
55
56static inline void summit_send_IPI_mask(const struct cpumask *mask, int vector)
57{
58 default_send_IPI_mask_sequence_logical(mask, vector);
59}
60
61static void summit_send_IPI_allbutself(int vector)
62{
63 default_send_IPI_mask_allbutself_logical(cpu_online_mask, vector);
64}
65
66static void summit_send_IPI_all(int vector)
67{
68 summit_send_IPI_mask(cpu_online_mask, vector);
69}
70
71#include <asm/tsc.h>
72
73extern int use_cyclone;
74
75#ifdef CONFIG_X86_SUMMIT_NUMA
76static void setup_summit(void);
77#else
78static inline void setup_summit(void) {}
79#endif
80
81static int summit_mps_oem_check(struct mpc_table *mpc, char *oem,
82 char *productid)
83{
84 if (!strncmp(oem, "IBM ENSW", 8) &&
85 (!strncmp(productid, "VIGIL SMP", 9)
86 || !strncmp(productid, "EXA", 3)
87 || !strncmp(productid, "RUTHLESS SMP", 12))){
88 mark_tsc_unstable("Summit based system");
89 use_cyclone = 1; /*enable cyclone-timer*/
90 setup_summit();
91 return 1;
92 }
93 return 0;
94}
95
96/* Hook from generic ACPI tables.c */
97static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
98{
99 if (!strncmp(oem_id, "IBM", 3) &&
100 (!strncmp(oem_table_id, "SERVIGIL", 8)
101 || !strncmp(oem_table_id, "EXA", 3))){
102 mark_tsc_unstable("Summit based system");
103 use_cyclone = 1; /*enable cyclone-timer*/
104 setup_summit();
105 return 1;
106 }
107 return 0;
108}
109
110struct rio_table_hdr {
111 unsigned char version; /* Version number of this data structure */
112 /* Version 3 adds chassis_num & WP_index */
113 unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */
114 unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */
115} __attribute__((packed));
116
117struct scal_detail {
118 unsigned char node_id; /* Scalability Node ID */
119 unsigned long CBAR; /* Address of 1MB register space */
120 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
121 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
122 unsigned char port1node; /* Node ID port connected to: 0xFF = None */
123 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
124 unsigned char port2node; /* Node ID port connected to: 0xFF = None */
125 unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */
126 unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */
127} __attribute__((packed));
128
129struct rio_detail {
130 unsigned char node_id; /* RIO Node ID */
131 unsigned long BBAR; /* Address of 1MB register space */
132 unsigned char type; /* Type of device */
133 unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/
134 /* For CYC: Node ID of Twister that owns this CYC */
135 unsigned char port0node; /* Node ID port connected to: 0xFF=None */
136 unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */
137 unsigned char port1node; /* Node ID port connected to: 0xFF=None */
138 unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */
139 unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */
140 /* For CYC: 0 */
141 unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */
142 /* = 0 : the XAPIC is not used, ie:*/
143 /* ints fwded to another XAPIC */
144 /* Bits1:7 Reserved */
145 /* For CYC: Bits0:7 Reserved */
146 unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */
147 /* lower slot numbers/PCI bus numbers */
148 /* For CYC: No meaning */
149 unsigned char chassis_num; /* 1 based Chassis number */
150 /* For LookOut WPEGs this field indicates the */
151 /* Expansion Chassis #, enumerated from Boot */
152 /* Node WPEG external port, then Boot Node CYC */
153 /* external port, then Next Vigil chassis WPEG */
154 /* external port, etc. */
155 /* Shared Lookouts have only 1 chassis number (the */
156 /* first one assigned) */
157} __attribute__((packed));
158
159
160typedef enum {
161 CompatTwister = 0, /* Compatibility Twister */
162 AltTwister = 1, /* Alternate Twister of internal 8-way */
163 CompatCyclone = 2, /* Compatibility Cyclone */
164 AltCyclone = 3, /* Alternate Cyclone of internal 8-way */
165 CompatWPEG = 4, /* Compatibility WPEG */
166 AltWPEG = 5, /* Second Planar WPEG */
167 LookOutAWPEG = 6, /* LookOut WPEG */
168 LookOutBWPEG = 7, /* LookOut WPEG */
169} node_type;
170
171static inline int is_WPEG(struct rio_detail *rio){
172 return (rio->type == CompatWPEG || rio->type == AltWPEG ||
173 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
174}
175
176
177/* In clustered mode, the high nibble of APIC ID is a cluster number.
178 * The low nibble is a 4-bit bitmap. */
179#define XAPIC_DEST_CPUS_SHIFT 4
180#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
181#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
182
183#define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
184
185static const struct cpumask *summit_target_cpus(void)
186{
187 /* CPU_MASK_ALL (0xff) has undefined behaviour with
188 * dest_LowestPrio mode logical clustered apic interrupt routing
189 * Just start on cpu 0. IRQ balancing will spread load
190 */
191 return cpumask_of(0);
192}
193
194static unsigned long summit_check_apicid_used(physid_mask_t bitmap, int apicid)
195{
196 return 0;
197}
198
199/* we don't use the phys_cpu_present_map to indicate apicid presence */
200static unsigned long summit_check_apicid_present(int bit)
201{
202 return 1;
203}
204
205static void summit_init_apic_ldr(void)
206{
207 unsigned long val, id;
208 int count = 0;
209 u8 my_id = (u8)hard_smp_processor_id();
210 u8 my_cluster = APIC_CLUSTER(my_id);
211#ifdef CONFIG_SMP
212 u8 lid;
213 int i;
214
215 /* Create logical APIC IDs by counting CPUs already in cluster. */
216 for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
217 lid = cpu_2_logical_apicid[i];
218 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
219 ++count;
220 }
221#endif
222 /* We only have a 4 wide bitmap in cluster mode. If a deranged
223 * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
224 BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
225 id = my_cluster | (1UL << count);
226 apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
227 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
228 val |= SET_APIC_LOGICAL_ID(id);
229 apic_write(APIC_LDR, val);
230}
231
232static int summit_apic_id_registered(void)
233{
234 return 1;
235}
236
237static void summit_setup_apic_routing(void)
238{
239 printk("Enabling APIC mode: Summit. Using %d I/O APICs\n",
240 nr_ioapics);
241}
242
243static int summit_apicid_to_node(int logical_apicid)
244{
245#ifdef CONFIG_SMP
246 return apicid_2_node[hard_smp_processor_id()];
247#else
248 return 0;
249#endif
250}
251
252/* Mapping from cpu number to logical apicid */
253static inline int summit_cpu_to_logical_apicid(int cpu)
254{
255#ifdef CONFIG_SMP
256 if (cpu >= nr_cpu_ids)
257 return BAD_APICID;
258 return cpu_2_logical_apicid[cpu];
259#else
260 return logical_smp_processor_id();
261#endif
262}
263
264static int summit_cpu_present_to_apicid(int mps_cpu)
265{
266 if (mps_cpu < nr_cpu_ids)
267 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
268 else
269 return BAD_APICID;
270}
271
272static physid_mask_t summit_ioapic_phys_id_map(physid_mask_t phys_id_map)
273{
274 /* For clustered we don't have a good way to do this yet - hack */
275 return physids_promote(0x0F);
276}
277
278static physid_mask_t summit_apicid_to_cpu_present(int apicid)
279{
280 return physid_mask_of_physid(0);
281}
282
283static int summit_check_phys_apicid_present(int boot_cpu_physical_apicid)
284{
285 return 1;
286}
287
288static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask)
289{
290 unsigned int round = 0;
291 int cpu, apicid = 0;
292
293 /*
294 * The cpus in the mask must all be on the apic cluster.
295 */
296 for_each_cpu(cpu, cpumask) {
297 int new_apicid = summit_cpu_to_logical_apicid(cpu);
298
299 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
300 printk("%s: Not a valid mask!\n", __func__);
301 return BAD_APICID;
302 }
303 apicid |= new_apicid;
304 round++;
305 }
306 return apicid;
307}
308
309static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
310 const struct cpumask *andmask)
311{
312 int apicid = summit_cpu_to_logical_apicid(0);
313 cpumask_var_t cpumask;
314
315 if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
316 return apicid;
317
318 cpumask_and(cpumask, inmask, andmask);
319 cpumask_and(cpumask, cpumask, cpu_online_mask);
320 apicid = summit_cpu_mask_to_apicid(cpumask);
321
322 free_cpumask_var(cpumask);
323
324 return apicid;
325}
326
327/*
328 * cpuid returns the value latched in the HW at reset, not the APIC ID
329 * register's value. For any box whose BIOS changes APIC IDs, like
330 * clustered APIC systems, we must use hard_smp_processor_id.
331 *
332 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
333 */
334static int summit_phys_pkg_id(int cpuid_apic, int index_msb)
335{
336 return hard_smp_processor_id() >> index_msb;
337}
338
339static int probe_summit(void)
340{
341 /* probed later in mptable/ACPI hooks */
342 return 0;
343}
344
345static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask)
346{
347 /* Careful. Some cpus do not strictly honor the set of cpus
348 * specified in the interrupt destination when using lowest
349 * priority interrupt delivery mode.
350 *
351 * In particular there was a hyperthreading cpu observed to
352 * deliver interrupts to the wrong hyperthread when only one
353 * hyperthread was specified in the interrupt desitination.
354 */
355 cpumask_clear(retmask);
356 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
357}
358
359#ifdef CONFIG_X86_SUMMIT_NUMA
360static struct rio_table_hdr *rio_table_hdr;
361static struct scal_detail *scal_devs[MAX_NUMNODES];
362static struct rio_detail *rio_devs[MAX_NUMNODES*4];
363
364#ifndef CONFIG_X86_NUMAQ
365static int mp_bus_id_to_node[MAX_MP_BUSSES];
366#endif
367
368static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
369{
370 int twister = 0, node = 0;
371 int i, bus, num_buses;
372
373 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
374 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
375 twister = rio_devs[i]->owner_id;
376 break;
377 }
378 }
379 if (i == rio_table_hdr->num_rio_dev) {
380 printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__);
381 return last_bus;
382 }
383
384 for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
385 if (scal_devs[i]->node_id == twister) {
386 node = scal_devs[i]->node_id;
387 break;
388 }
389 }
390 if (i == rio_table_hdr->num_scal_dev) {
391 printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__);
392 return last_bus;
393 }
394
395 switch (rio_devs[wpeg_num]->type) {
396 case CompatWPEG:
397 /*
398 * The Compatibility Winnipeg controls the 2 legacy buses,
399 * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
400 * a PCI-PCI bridge card is used in either slot: total 5 buses.
401 */
402 num_buses = 5;
403 break;
404 case AltWPEG:
405 /*
406 * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
407 * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
408 * the "extra" buses for each of those slots: total 7 buses.
409 */
410 num_buses = 7;
411 break;
412 case LookOutAWPEG:
413 case LookOutBWPEG:
414 /*
415 * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
416 * & the "extra" buses for each of those slots: total 9 buses.
417 */
418 num_buses = 9;
419 break;
420 default:
421 printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__);
422 return last_bus;
423 }
424
425 for (bus = last_bus; bus < last_bus + num_buses; bus++)
426 mp_bus_id_to_node[bus] = node;
427 return bus;
428}
429
430static int build_detail_arrays(void)
431{
432 unsigned long ptr;
433 int i, scal_detail_size, rio_detail_size;
434
435 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
436 printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev);
437 return 0;
438 }
439
440 switch (rio_table_hdr->version) {
441 default:
442 printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version);
443 return 0;
444 case 2:
445 scal_detail_size = 11;
446 rio_detail_size = 13;
447 break;
448 case 3:
449 scal_detail_size = 12;
450 rio_detail_size = 15;
451 break;
452 }
453
454 ptr = (unsigned long)rio_table_hdr + 3;
455 for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
456 scal_devs[i] = (struct scal_detail *)ptr;
457
458 for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
459 rio_devs[i] = (struct rio_detail *)ptr;
460
461 return 1;
462}
463
464void setup_summit(void)
465{
466 unsigned long ptr;
467 unsigned short offset;
468 int i, next_wpeg, next_bus = 0;
469
470 /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
471 ptr = get_bios_ebda();
472 ptr = (unsigned long)phys_to_virt(ptr);
473
474 rio_table_hdr = NULL;
475 offset = 0x180;
476 while (offset) {
477 /* The block id is stored in the 2nd word */
478 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
479 /* set the pointer past the offset & block id */
480 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
481 break;
482 }
483 /* The next offset is stored in the 1st word. 0 means no more */
484 offset = *((unsigned short *)(ptr + offset));
485 }
486 if (!rio_table_hdr) {
487 printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__);
488 return;
489 }
490
491 if (!build_detail_arrays())
492 return;
493
494 /* The first Winnipeg we're looking for has an index of 0 */
495 next_wpeg = 0;
496 do {
497 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
498 if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
499 /* It's the Winnipeg we're looking for! */
500 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
501 next_wpeg++;
502 break;
503 }
504 }
505 /*
506 * If we go through all Rio devices and don't find one with
507 * the next index, it means we've found all the Winnipegs,
508 * and thus all the PCI buses.
509 */
510 if (i == rio_table_hdr->num_rio_dev)
511 next_wpeg = 0;
512 } while (next_wpeg != 0);
513}
514#endif
515
516struct apic apic_summit = {
517
518 .name = "summit",
519 .probe = probe_summit,
520 .acpi_madt_oem_check = summit_acpi_madt_oem_check,
521 .apic_id_registered = summit_apic_id_registered,
522
523 .irq_delivery_mode = dest_LowestPrio,
524 /* logical delivery broadcast to all CPUs: */
525 .irq_dest_mode = 1,
526
527 .target_cpus = summit_target_cpus,
528 .disable_esr = 1,
529 .dest_logical = APIC_DEST_LOGICAL,
530 .check_apicid_used = summit_check_apicid_used,
531 .check_apicid_present = summit_check_apicid_present,
532
533 .vector_allocation_domain = summit_vector_allocation_domain,
534 .init_apic_ldr = summit_init_apic_ldr,
535
536 .ioapic_phys_id_map = summit_ioapic_phys_id_map,
537 .setup_apic_routing = summit_setup_apic_routing,
538 .multi_timer_check = NULL,
539 .apicid_to_node = summit_apicid_to_node,
540 .cpu_to_logical_apicid = summit_cpu_to_logical_apicid,
541 .cpu_present_to_apicid = summit_cpu_present_to_apicid,
542 .apicid_to_cpu_present = summit_apicid_to_cpu_present,
543 .setup_portio_remap = NULL,
544 .check_phys_apicid_present = summit_check_phys_apicid_present,
545 .enable_apic_mode = NULL,
546 .phys_pkg_id = summit_phys_pkg_id,
547 .mps_oem_check = summit_mps_oem_check,
548
549 .get_apic_id = summit_get_apic_id,
550 .set_apic_id = NULL,
551 .apic_id_mask = 0xFF << 24,
552
553 .cpu_mask_to_apicid = summit_cpu_mask_to_apicid,
554 .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and,
555
556 .send_IPI_mask = summit_send_IPI_mask,
557 .send_IPI_mask_allbutself = NULL,
558 .send_IPI_allbutself = summit_send_IPI_allbutself,
559 .send_IPI_all = summit_send_IPI_all,
560 .send_IPI_self = default_send_IPI_self,
561
562 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
563 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
564
565 .wait_for_init_deassert = default_wait_for_init_deassert,
566
567 .smp_callin_clear_local_apic = NULL,
568 .inquire_remote_apic = default_inquire_remote_apic,
569
570 .read = native_apic_mem_read,
571 .write = native_apic_mem_write,
572 .icr_read = native_apic_icr_read,
573 .icr_write = native_apic_icr_write,
574 .wait_icr_idle = native_apic_wait_icr_idle,
575 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
576};
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
new file mode 100644
index 000000000000..8fb87b6dd633
--- /dev/null
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -0,0 +1,239 @@
1#include <linux/threads.h>
2#include <linux/cpumask.h>
3#include <linux/string.h>
4#include <linux/kernel.h>
5#include <linux/ctype.h>
6#include <linux/init.h>
7#include <linux/dmar.h>
8
9#include <asm/smp.h>
10#include <asm/apic.h>
11#include <asm/ipi.h>
12
13DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
14
15static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
16{
17 return x2apic_enabled();
18}
19
20/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
21
22static const struct cpumask *x2apic_target_cpus(void)
23{
24 return cpumask_of(0);
25}
26
27/*
28 * for now each logical cpu is in its own vector allocation domain.
29 */
30static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
31{
32 cpumask_clear(retmask);
33 cpumask_set_cpu(cpu, retmask);
34}
35
36static void
37 __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
38{
39 unsigned long cfg;
40
41 cfg = __prepare_ICR(0, vector, dest);
42
43 /*
44 * send the IPI.
45 */
46 native_x2apic_icr_write(cfg, apicid);
47}
48
49/*
50 * for now, we send the IPI's one by one in the cpumask.
51 * TBD: Based on the cpu mask, we can send the IPI's to the cluster group
52 * at once. We have 16 cpu's in a cluster. This will minimize IPI register
53 * writes.
54 */
55static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
56{
57 unsigned long query_cpu;
58 unsigned long flags;
59
60 local_irq_save(flags);
61 for_each_cpu(query_cpu, mask) {
62 __x2apic_send_IPI_dest(
63 per_cpu(x86_cpu_to_logical_apicid, query_cpu),
64 vector, apic->dest_logical);
65 }
66 local_irq_restore(flags);
67}
68
69static void
70 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
71{
72 unsigned long this_cpu = smp_processor_id();
73 unsigned long query_cpu;
74 unsigned long flags;
75
76 local_irq_save(flags);
77 for_each_cpu(query_cpu, mask) {
78 if (query_cpu == this_cpu)
79 continue;
80 __x2apic_send_IPI_dest(
81 per_cpu(x86_cpu_to_logical_apicid, query_cpu),
82 vector, apic->dest_logical);
83 }
84 local_irq_restore(flags);
85}
86
87static void x2apic_send_IPI_allbutself(int vector)
88{
89 unsigned long this_cpu = smp_processor_id();
90 unsigned long query_cpu;
91 unsigned long flags;
92
93 local_irq_save(flags);
94 for_each_online_cpu(query_cpu) {
95 if (query_cpu == this_cpu)
96 continue;
97 __x2apic_send_IPI_dest(
98 per_cpu(x86_cpu_to_logical_apicid, query_cpu),
99 vector, apic->dest_logical);
100 }
101 local_irq_restore(flags);
102}
103
104static void x2apic_send_IPI_all(int vector)
105{
106 x2apic_send_IPI_mask(cpu_online_mask, vector);
107}
108
109static int x2apic_apic_id_registered(void)
110{
111 return 1;
112}
113
114static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
115{
116 /*
117 * We're using fixed IRQ delivery, can only return one logical APIC ID.
118 * May as well be the first.
119 */
120 int cpu = cpumask_first(cpumask);
121
122 if ((unsigned)cpu < nr_cpu_ids)
123 return per_cpu(x86_cpu_to_logical_apicid, cpu);
124 else
125 return BAD_APICID;
126}
127
128static unsigned int
129x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
130 const struct cpumask *andmask)
131{
132 int cpu;
133
134 /*
135 * We're using fixed IRQ delivery, can only return one logical APIC ID.
136 * May as well be the first.
137 */
138 for_each_cpu_and(cpu, cpumask, andmask) {
139 if (cpumask_test_cpu(cpu, cpu_online_mask))
140 break;
141 }
142
143 if (cpu < nr_cpu_ids)
144 return per_cpu(x86_cpu_to_logical_apicid, cpu);
145
146 return BAD_APICID;
147}
148
149static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x)
150{
151 unsigned int id;
152
153 id = x;
154 return id;
155}
156
157static unsigned long set_apic_id(unsigned int id)
158{
159 unsigned long x;
160
161 x = id;
162 return x;
163}
164
165static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb)
166{
167 return current_cpu_data.initial_apicid >> index_msb;
168}
169
170static void x2apic_send_IPI_self(int vector)
171{
172 apic_write(APIC_SELF_IPI, vector);
173}
174
175static void init_x2apic_ldr(void)
176{
177 int cpu = smp_processor_id();
178
179 per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
180}
181
182struct apic apic_x2apic_cluster = {
183
184 .name = "cluster x2apic",
185 .probe = NULL,
186 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
187 .apic_id_registered = x2apic_apic_id_registered,
188
189 .irq_delivery_mode = dest_LowestPrio,
190 .irq_dest_mode = 1, /* logical */
191
192 .target_cpus = x2apic_target_cpus,
193 .disable_esr = 0,
194 .dest_logical = APIC_DEST_LOGICAL,
195 .check_apicid_used = NULL,
196 .check_apicid_present = NULL,
197
198 .vector_allocation_domain = x2apic_vector_allocation_domain,
199 .init_apic_ldr = init_x2apic_ldr,
200
201 .ioapic_phys_id_map = NULL,
202 .setup_apic_routing = NULL,
203 .multi_timer_check = NULL,
204 .apicid_to_node = NULL,
205 .cpu_to_logical_apicid = NULL,
206 .cpu_present_to_apicid = default_cpu_present_to_apicid,
207 .apicid_to_cpu_present = NULL,
208 .setup_portio_remap = NULL,
209 .check_phys_apicid_present = default_check_phys_apicid_present,
210 .enable_apic_mode = NULL,
211 .phys_pkg_id = x2apic_cluster_phys_pkg_id,
212 .mps_oem_check = NULL,
213
214 .get_apic_id = x2apic_cluster_phys_get_apic_id,
215 .set_apic_id = set_apic_id,
216 .apic_id_mask = 0xFFFFFFFFu,
217
218 .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
219 .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
220
221 .send_IPI_mask = x2apic_send_IPI_mask,
222 .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
223 .send_IPI_allbutself = x2apic_send_IPI_allbutself,
224 .send_IPI_all = x2apic_send_IPI_all,
225 .send_IPI_self = x2apic_send_IPI_self,
226
227 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
228 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
229 .wait_for_init_deassert = NULL,
230 .smp_callin_clear_local_apic = NULL,
231 .inquire_remote_apic = NULL,
232
233 .read = native_apic_msr_read,
234 .write = native_apic_msr_write,
235 .icr_read = native_x2apic_icr_read,
236 .icr_write = native_x2apic_icr_write,
237 .wait_icr_idle = native_x2apic_wait_icr_idle,
238 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
239};
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
new file mode 100644
index 000000000000..23625b9f98b2
--- /dev/null
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -0,0 +1,228 @@
1#include <linux/threads.h>
2#include <linux/cpumask.h>
3#include <linux/string.h>
4#include <linux/kernel.h>
5#include <linux/ctype.h>
6#include <linux/init.h>
7#include <linux/dmar.h>
8
9#include <asm/smp.h>
10#include <asm/apic.h>
11#include <asm/ipi.h>
12
13int x2apic_phys;
14
15static int set_x2apic_phys_mode(char *arg)
16{
17 x2apic_phys = 1;
18 return 0;
19}
20early_param("x2apic_phys", set_x2apic_phys_mode);
21
22static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
23{
24 if (x2apic_phys)
25 return x2apic_enabled();
26 else
27 return 0;
28}
29
30/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
31
32static const struct cpumask *x2apic_target_cpus(void)
33{
34 return cpumask_of(0);
35}
36
37static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
38{
39 cpumask_clear(retmask);
40 cpumask_set_cpu(cpu, retmask);
41}
42
43static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
44 unsigned int dest)
45{
46 unsigned long cfg;
47
48 cfg = __prepare_ICR(0, vector, dest);
49
50 /*
51 * send the IPI.
52 */
53 native_x2apic_icr_write(cfg, apicid);
54}
55
56static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
57{
58 unsigned long query_cpu;
59 unsigned long flags;
60
61 local_irq_save(flags);
62 for_each_cpu(query_cpu, mask) {
63 __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
64 vector, APIC_DEST_PHYSICAL);
65 }
66 local_irq_restore(flags);
67}
68
69static void
70 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
71{
72 unsigned long this_cpu = smp_processor_id();
73 unsigned long query_cpu;
74 unsigned long flags;
75
76 local_irq_save(flags);
77 for_each_cpu(query_cpu, mask) {
78 if (query_cpu != this_cpu)
79 __x2apic_send_IPI_dest(
80 per_cpu(x86_cpu_to_apicid, query_cpu),
81 vector, APIC_DEST_PHYSICAL);
82 }
83 local_irq_restore(flags);
84}
85
86static void x2apic_send_IPI_allbutself(int vector)
87{
88 unsigned long this_cpu = smp_processor_id();
89 unsigned long query_cpu;
90 unsigned long flags;
91
92 local_irq_save(flags);
93 for_each_online_cpu(query_cpu) {
94 if (query_cpu == this_cpu)
95 continue;
96 __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
97 vector, APIC_DEST_PHYSICAL);
98 }
99 local_irq_restore(flags);
100}
101
102static void x2apic_send_IPI_all(int vector)
103{
104 x2apic_send_IPI_mask(cpu_online_mask, vector);
105}
106
107static int x2apic_apic_id_registered(void)
108{
109 return 1;
110}
111
112static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
113{
114 /*
115 * We're using fixed IRQ delivery, can only return one phys APIC ID.
116 * May as well be the first.
117 */
118 int cpu = cpumask_first(cpumask);
119
120 if ((unsigned)cpu < nr_cpu_ids)
121 return per_cpu(x86_cpu_to_apicid, cpu);
122 else
123 return BAD_APICID;
124}
125
126static unsigned int
127x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
128 const struct cpumask *andmask)
129{
130 int cpu;
131
132 /*
133 * We're using fixed IRQ delivery, can only return one phys APIC ID.
134 * May as well be the first.
135 */
136 for_each_cpu_and(cpu, cpumask, andmask) {
137 if (cpumask_test_cpu(cpu, cpu_online_mask))
138 break;
139 }
140
141 if (cpu < nr_cpu_ids)
142 return per_cpu(x86_cpu_to_apicid, cpu);
143
144 return BAD_APICID;
145}
146
147static unsigned int x2apic_phys_get_apic_id(unsigned long x)
148{
149 return x;
150}
151
152static unsigned long set_apic_id(unsigned int id)
153{
154 return id;
155}
156
157static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
158{
159 return current_cpu_data.initial_apicid >> index_msb;
160}
161
162static void x2apic_send_IPI_self(int vector)
163{
164 apic_write(APIC_SELF_IPI, vector);
165}
166
167static void init_x2apic_ldr(void)
168{
169}
170
171struct apic apic_x2apic_phys = {
172
173 .name = "physical x2apic",
174 .probe = NULL,
175 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
176 .apic_id_registered = x2apic_apic_id_registered,
177
178 .irq_delivery_mode = dest_Fixed,
179 .irq_dest_mode = 0, /* physical */
180
181 .target_cpus = x2apic_target_cpus,
182 .disable_esr = 0,
183 .dest_logical = 0,
184 .check_apicid_used = NULL,
185 .check_apicid_present = NULL,
186
187 .vector_allocation_domain = x2apic_vector_allocation_domain,
188 .init_apic_ldr = init_x2apic_ldr,
189
190 .ioapic_phys_id_map = NULL,
191 .setup_apic_routing = NULL,
192 .multi_timer_check = NULL,
193 .apicid_to_node = NULL,
194 .cpu_to_logical_apicid = NULL,
195 .cpu_present_to_apicid = default_cpu_present_to_apicid,
196 .apicid_to_cpu_present = NULL,
197 .setup_portio_remap = NULL,
198 .check_phys_apicid_present = default_check_phys_apicid_present,
199 .enable_apic_mode = NULL,
200 .phys_pkg_id = x2apic_phys_pkg_id,
201 .mps_oem_check = NULL,
202
203 .get_apic_id = x2apic_phys_get_apic_id,
204 .set_apic_id = set_apic_id,
205 .apic_id_mask = 0xFFFFFFFFu,
206
207 .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
208 .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
209
210 .send_IPI_mask = x2apic_send_IPI_mask,
211 .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
212 .send_IPI_allbutself = x2apic_send_IPI_allbutself,
213 .send_IPI_all = x2apic_send_IPI_all,
214 .send_IPI_self = x2apic_send_IPI_self,
215
216 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
217 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
218 .wait_for_init_deassert = NULL,
219 .smp_callin_clear_local_apic = NULL,
220 .inquire_remote_apic = NULL,
221
222 .read = native_apic_msr_read,
223 .write = native_apic_msr_write,
224 .icr_read = native_x2apic_icr_read,
225 .icr_write = native_x2apic_icr_write,
226 .wait_icr_idle = native_x2apic_wait_icr_idle,
227 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
228};
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
new file mode 100644
index 000000000000..1bd6da1f8fad
--- /dev/null
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -0,0 +1,647 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/cpu.h>
21#include <linux/init.h>
22
23#include <asm/uv/uv_mmrs.h>
24#include <asm/uv/uv_hub.h>
25#include <asm/current.h>
26#include <asm/pgtable.h>
27#include <asm/uv/bios.h>
28#include <asm/uv/uv.h>
29#include <asm/apic.h>
30#include <asm/ipi.h>
31#include <asm/smp.h>
32
33DEFINE_PER_CPU(int, x2apic_extra_bits);
34
35static enum uv_system_type uv_system_type;
36
37static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
38{
39 if (!strcmp(oem_id, "SGI")) {
40 if (!strcmp(oem_table_id, "UVL"))
41 uv_system_type = UV_LEGACY_APIC;
42 else if (!strcmp(oem_table_id, "UVX"))
43 uv_system_type = UV_X2APIC;
44 else if (!strcmp(oem_table_id, "UVH")) {
45 uv_system_type = UV_NON_UNIQUE_APIC;
46 return 1;
47 }
48 }
49 return 0;
50}
51
52enum uv_system_type get_uv_system_type(void)
53{
54 return uv_system_type;
55}
56
57int is_uv_system(void)
58{
59 return uv_system_type != UV_NONE;
60}
61EXPORT_SYMBOL_GPL(is_uv_system);
62
63DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
64EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
65
66struct uv_blade_info *uv_blade_info;
67EXPORT_SYMBOL_GPL(uv_blade_info);
68
69short *uv_node_to_blade;
70EXPORT_SYMBOL_GPL(uv_node_to_blade);
71
72short *uv_cpu_to_blade;
73EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
74
75short uv_possible_blades;
76EXPORT_SYMBOL_GPL(uv_possible_blades);
77
78unsigned long sn_rtc_cycles_per_second;
79EXPORT_SYMBOL(sn_rtc_cycles_per_second);
80
81/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
82
83static const struct cpumask *uv_target_cpus(void)
84{
85 return cpumask_of(0);
86}
87
88static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
89{
90 cpumask_clear(retmask);
91 cpumask_set_cpu(cpu, retmask);
92}
93
94static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
95{
96#ifdef CONFIG_SMP
97 unsigned long val;
98 int pnode;
99
100 pnode = uv_apicid_to_pnode(phys_apicid);
101 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
102 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
103 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
104 APIC_DM_INIT;
105 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
106 mdelay(10);
107
108 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
109 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
110 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
111 APIC_DM_STARTUP;
112 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
113
114 atomic_set(&init_deasserted, 1);
115#endif
116 return 0;
117}
118
119static void uv_send_IPI_one(int cpu, int vector)
120{
121 unsigned long val, apicid;
122 int pnode;
123
124 apicid = per_cpu(x86_cpu_to_apicid, cpu);
125 pnode = uv_apicid_to_pnode(apicid);
126
127 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
128 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
129 (vector << UVH_IPI_INT_VECTOR_SHFT);
130
131 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
132}
133
134static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
135{
136 unsigned int cpu;
137
138 for_each_cpu(cpu, mask)
139 uv_send_IPI_one(cpu, vector);
140}
141
142static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
143{
144 unsigned int this_cpu = smp_processor_id();
145 unsigned int cpu;
146
147 for_each_cpu(cpu, mask) {
148 if (cpu != this_cpu)
149 uv_send_IPI_one(cpu, vector);
150 }
151}
152
153static void uv_send_IPI_allbutself(int vector)
154{
155 unsigned int this_cpu = smp_processor_id();
156 unsigned int cpu;
157
158 for_each_online_cpu(cpu) {
159 if (cpu != this_cpu)
160 uv_send_IPI_one(cpu, vector);
161 }
162}
163
164static void uv_send_IPI_all(int vector)
165{
166 uv_send_IPI_mask(cpu_online_mask, vector);
167}
168
169static int uv_apic_id_registered(void)
170{
171 return 1;
172}
173
174static void uv_init_apic_ldr(void)
175{
176}
177
178static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
179{
180 /*
181 * We're using fixed IRQ delivery, can only return one phys APIC ID.
182 * May as well be the first.
183 */
184 int cpu = cpumask_first(cpumask);
185
186 if ((unsigned)cpu < nr_cpu_ids)
187 return per_cpu(x86_cpu_to_apicid, cpu);
188 else
189 return BAD_APICID;
190}
191
192static unsigned int
193uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
194 const struct cpumask *andmask)
195{
196 int cpu;
197
198 /*
199 * We're using fixed IRQ delivery, can only return one phys APIC ID.
200 * May as well be the first.
201 */
202 for_each_cpu_and(cpu, cpumask, andmask) {
203 if (cpumask_test_cpu(cpu, cpu_online_mask))
204 break;
205 }
206 if (cpu < nr_cpu_ids)
207 return per_cpu(x86_cpu_to_apicid, cpu);
208
209 return BAD_APICID;
210}
211
212static unsigned int x2apic_get_apic_id(unsigned long x)
213{
214 unsigned int id;
215
216 WARN_ON(preemptible() && num_online_cpus() > 1);
217 id = x | __get_cpu_var(x2apic_extra_bits);
218
219 return id;
220}
221
222static unsigned long set_apic_id(unsigned int id)
223{
224 unsigned long x;
225
226 /* maskout x2apic_extra_bits ? */
227 x = id;
228 return x;
229}
230
231static unsigned int uv_read_apic_id(void)
232{
233
234 return x2apic_get_apic_id(apic_read(APIC_ID));
235}
236
237static int uv_phys_pkg_id(int initial_apicid, int index_msb)
238{
239 return uv_read_apic_id() >> index_msb;
240}
241
242static void uv_send_IPI_self(int vector)
243{
244 apic_write(APIC_SELF_IPI, vector);
245}
246
247struct apic apic_x2apic_uv_x = {
248
249 .name = "UV large system",
250 .probe = NULL,
251 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
252 .apic_id_registered = uv_apic_id_registered,
253
254 .irq_delivery_mode = dest_Fixed,
255 .irq_dest_mode = 1, /* logical */
256
257 .target_cpus = uv_target_cpus,
258 .disable_esr = 0,
259 .dest_logical = APIC_DEST_LOGICAL,
260 .check_apicid_used = NULL,
261 .check_apicid_present = NULL,
262
263 .vector_allocation_domain = uv_vector_allocation_domain,
264 .init_apic_ldr = uv_init_apic_ldr,
265
266 .ioapic_phys_id_map = NULL,
267 .setup_apic_routing = NULL,
268 .multi_timer_check = NULL,
269 .apicid_to_node = NULL,
270 .cpu_to_logical_apicid = NULL,
271 .cpu_present_to_apicid = default_cpu_present_to_apicid,
272 .apicid_to_cpu_present = NULL,
273 .setup_portio_remap = NULL,
274 .check_phys_apicid_present = default_check_phys_apicid_present,
275 .enable_apic_mode = NULL,
276 .phys_pkg_id = uv_phys_pkg_id,
277 .mps_oem_check = NULL,
278
279 .get_apic_id = x2apic_get_apic_id,
280 .set_apic_id = set_apic_id,
281 .apic_id_mask = 0xFFFFFFFFu,
282
283 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
284 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
285
286 .send_IPI_mask = uv_send_IPI_mask,
287 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
288 .send_IPI_allbutself = uv_send_IPI_allbutself,
289 .send_IPI_all = uv_send_IPI_all,
290 .send_IPI_self = uv_send_IPI_self,
291
292 .wakeup_secondary_cpu = uv_wakeup_secondary,
293 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
294 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
295 .wait_for_init_deassert = NULL,
296 .smp_callin_clear_local_apic = NULL,
297 .inquire_remote_apic = NULL,
298
299 .read = native_apic_msr_read,
300 .write = native_apic_msr_write,
301 .icr_read = native_x2apic_icr_read,
302 .icr_write = native_x2apic_icr_write,
303 .wait_icr_idle = native_x2apic_wait_icr_idle,
304 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
305};
306
307static __cpuinit void set_x2apic_extra_bits(int pnode)
308{
309 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
310}
311
312/*
313 * Called on boot cpu.
314 */
315static __init int boot_pnode_to_blade(int pnode)
316{
317 int blade;
318
319 for (blade = 0; blade < uv_num_possible_blades(); blade++)
320 if (pnode == uv_blade_info[blade].pnode)
321 return blade;
322 BUG();
323}
324
325struct redir_addr {
326 unsigned long redirect;
327 unsigned long alias;
328};
329
330#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
331
332static __initdata struct redir_addr redir_addrs[] = {
333 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
334 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
335 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
336};
337
338static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
339{
340 union uvh_si_alias0_overlay_config_u alias;
341 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
342 int i;
343
344 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
345 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
346 if (alias.s.base == 0) {
347 *size = (1UL << alias.s.m_alias);
348 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
349 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
350 return;
351 }
352 }
353 BUG();
354}
355
356static __init void map_low_mmrs(void)
357{
358 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
359 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
360}
361
362enum map_type {map_wb, map_uc};
363
364static __init void map_high(char *id, unsigned long base, int shift,
365 int max_pnode, enum map_type map_type)
366{
367 unsigned long bytes, paddr;
368
369 paddr = base << shift;
370 bytes = (1UL << shift) * (max_pnode + 1);
371 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
372 paddr + bytes);
373 if (map_type == map_uc)
374 init_extra_mapping_uc(paddr, bytes);
375 else
376 init_extra_mapping_wb(paddr, bytes);
377
378}
379static __init void map_gru_high(int max_pnode)
380{
381 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
382 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
383
384 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
385 if (gru.s.enable)
386 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
387}
388
389static __init void map_config_high(int max_pnode)
390{
391 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
392 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
393
394 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
395 if (cfg.s.enable)
396 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
397}
398
399static __init void map_mmr_high(int max_pnode)
400{
401 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
402 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
403
404 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
405 if (mmr.s.enable)
406 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
407}
408
409static __init void map_mmioh_high(int max_pnode)
410{
411 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
412 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
413
414 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
415 if (mmioh.s.enable)
416 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
417}
418
419static __init void uv_rtc_init(void)
420{
421 long status;
422 u64 ticks_per_sec;
423
424 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
425 &ticks_per_sec);
426 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
427 printk(KERN_WARNING
428 "unable to determine platform RTC clock frequency, "
429 "guessing.\n");
430 /* BIOS gives wrong value for clock freq. so guess */
431 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
432 } else
433 sn_rtc_cycles_per_second = ticks_per_sec;
434}
435
436/*
437 * percpu heartbeat timer
438 */
439static void uv_heartbeat(unsigned long ignored)
440{
441 struct timer_list *timer = &uv_hub_info->scir.timer;
442 unsigned char bits = uv_hub_info->scir.state;
443
444 /* flip heartbeat bit */
445 bits ^= SCIR_CPU_HEARTBEAT;
446
447 /* is this cpu idle? */
448 if (idle_cpu(raw_smp_processor_id()))
449 bits &= ~SCIR_CPU_ACTIVITY;
450 else
451 bits |= SCIR_CPU_ACTIVITY;
452
453 /* update system controller interface reg */
454 uv_set_scir_bits(bits);
455
456 /* enable next timer period */
457 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
458}
459
460static void __cpuinit uv_heartbeat_enable(int cpu)
461{
462 if (!uv_cpu_hub_info(cpu)->scir.enabled) {
463 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
464
465 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
466 setup_timer(timer, uv_heartbeat, cpu);
467 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
468 add_timer_on(timer, cpu);
469 uv_cpu_hub_info(cpu)->scir.enabled = 1;
470 }
471
472 /* check boot cpu */
473 if (!uv_cpu_hub_info(0)->scir.enabled)
474 uv_heartbeat_enable(0);
475}
476
477#ifdef CONFIG_HOTPLUG_CPU
478static void __cpuinit uv_heartbeat_disable(int cpu)
479{
480 if (uv_cpu_hub_info(cpu)->scir.enabled) {
481 uv_cpu_hub_info(cpu)->scir.enabled = 0;
482 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
483 }
484 uv_set_cpu_scir_bits(cpu, 0xff);
485}
486
487/*
488 * cpu hotplug notifier
489 */
490static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
491 unsigned long action, void *hcpu)
492{
493 long cpu = (long)hcpu;
494
495 switch (action) {
496 case CPU_ONLINE:
497 uv_heartbeat_enable(cpu);
498 break;
499 case CPU_DOWN_PREPARE:
500 uv_heartbeat_disable(cpu);
501 break;
502 default:
503 break;
504 }
505 return NOTIFY_OK;
506}
507
508static __init void uv_scir_register_cpu_notifier(void)
509{
510 hotcpu_notifier(uv_scir_cpu_notify, 0);
511}
512
513#else /* !CONFIG_HOTPLUG_CPU */
514
515static __init void uv_scir_register_cpu_notifier(void)
516{
517}
518
519static __init int uv_init_heartbeat(void)
520{
521 int cpu;
522
523 if (is_uv_system())
524 for_each_online_cpu(cpu)
525 uv_heartbeat_enable(cpu);
526 return 0;
527}
528
529late_initcall(uv_init_heartbeat);
530
531#endif /* !CONFIG_HOTPLUG_CPU */
532
533/*
534 * Called on each cpu to initialize the per_cpu UV data area.
535 * FIXME: hotplug not supported yet
536 */
537void __cpuinit uv_cpu_init(void)
538{
539 /* CPU 0 initilization will be done via uv_system_init. */
540 if (!uv_blade_info)
541 return;
542
543 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
544
545 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
546 set_x2apic_extra_bits(uv_hub_info->pnode);
547}
548
549
550void __init uv_system_init(void)
551{
552 union uvh_si_addr_map_config_u m_n_config;
553 union uvh_node_id_u node_id;
554 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
555 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
556 int max_pnode = 0;
557 unsigned long mmr_base, present;
558
559 map_low_mmrs();
560
561 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
562 m_val = m_n_config.s.m_skt;
563 n_val = m_n_config.s.n_skt;
564 mmr_base =
565 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
566 ~UV_MMR_ENABLE;
567 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
568
569 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
570 uv_possible_blades +=
571 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
572 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
573
574 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
575 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
576
577 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
578
579 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
580 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
581 memset(uv_node_to_blade, 255, bytes);
582
583 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
584 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
585 memset(uv_cpu_to_blade, 255, bytes);
586
587 blade = 0;
588 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
589 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
590 for (j = 0; j < 64; j++) {
591 if (!test_bit(j, &present))
592 continue;
593 uv_blade_info[blade].pnode = (i * 64 + j);
594 uv_blade_info[blade].nr_possible_cpus = 0;
595 uv_blade_info[blade].nr_online_cpus = 0;
596 blade++;
597 }
598 }
599
600 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
601 gnode_upper = (((unsigned long)node_id.s.node_id) &
602 ~((1 << n_val) - 1)) << m_val;
603
604 uv_bios_init();
605 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
606 &sn_coherency_id, &sn_region_size);
607 uv_rtc_init();
608
609 for_each_present_cpu(cpu) {
610 nid = cpu_to_node(cpu);
611 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
612 blade = boot_pnode_to_blade(pnode);
613 lcpu = uv_blade_info[blade].nr_possible_cpus;
614 uv_blade_info[blade].nr_possible_cpus++;
615
616 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
617 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
618 uv_cpu_hub_info(cpu)->m_val = m_val;
619 uv_cpu_hub_info(cpu)->n_val = m_val;
620 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
621 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
622 uv_cpu_hub_info(cpu)->pnode = pnode;
623 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
624 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
625 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
626 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
627 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
628 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
629 uv_node_to_blade[nid] = blade;
630 uv_cpu_to_blade[cpu] = blade;
631 max_pnode = max(pnode, max_pnode);
632
633 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
634 "lcpu %d, blade %d\n",
635 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
636 lcpu, blade);
637 }
638
639 map_gru_high(max_pnode);
640 map_mmr_high(max_pnode);
641 map_config_high(max_pnode);
642 map_mmioh_high(max_pnode);
643
644 uv_cpu_init();
645 uv_scir_register_cpu_notifier();
646 proc_mkdir("sgi_uv", NULL);
647}
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