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diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
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1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/mc146818rtc.h>
19#include <linux/acpi_pmtmr.h>
20#include <linux/clockchips.h>
21#include <linux/interrupt.h>
22#include <linux/bootmem.h>
23#include <linux/ftrace.h>
24#include <linux/ioport.h>
25#include <linux/module.h>
26#include <linux/sysdev.h>
27#include <linux/delay.h>
28#include <linux/timex.h>
29#include <linux/dmar.h>
30#include <linux/init.h>
31#include <linux/cpu.h>
32#include <linux/dmi.h>
33#include <linux/nmi.h>
34#include <linux/smp.h>
35#include <linux/mm.h>
36
37#include <asm/pgalloc.h>
38#include <asm/atomic.h>
39#include <asm/mpspec.h>
40#include <asm/i8253.h>
41#include <asm/i8259.h>
42#include <asm/proto.h>
43#include <asm/apic.h>
44#include <asm/desc.h>
45#include <asm/hpet.h>
46#include <asm/idle.h>
47#include <asm/mtrr.h>
48#include <asm/smp.h>
49#include <asm/mce.h>
50
51unsigned int num_processors;
52
53unsigned disabled_cpus __cpuinitdata;
54
55/* Processor that is doing the boot up */
56unsigned int boot_cpu_physical_apicid = -1U;
57
58/*
59 * The highest APIC ID seen during enumeration.
60 *
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
64 *
65 * If there's an APIC ID above 8, we use physical addressing.
66 */
67unsigned int max_physical_apicid;
68
69/*
70 * Bitmask of physically existing CPUs:
71 */
72physid_mask_t phys_cpu_present_map;
73
74/*
75 * Map cpu index to physical APIC ID
76 */
77DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
81
82#ifdef CONFIG_X86_32
83/*
84 * Knob to control our willingness to enable the local APIC.
85 *
86 * +1=force-enable
87 */
88static int force_enable_local_apic;
89/*
90 * APIC command line parameters
91 */
92static int __init parse_lapic(char *arg)
93{
94 force_enable_local_apic = 1;
95 return 0;
96}
97early_param("lapic", parse_lapic);
98/* Local APIC was disabled by the BIOS and enabled by the kernel */
99static int enabled_via_apicbase;
100
101#endif
102
103#ifdef CONFIG_X86_64
104static int apic_calibrate_pmtmr __initdata;
105static __init int setup_apicpmtimer(char *s)
106{
107 apic_calibrate_pmtmr = 1;
108 notsc_setup(NULL);
109 return 0;
110}
111__setup("apicpmtimer", setup_apicpmtimer);
112#endif
113
114#ifdef CONFIG_X86_X2APIC
115int x2apic;
116/* x2apic enabled before OS handover */
117static int x2apic_preenabled;
118static int disable_x2apic;
119static __init int setup_nox2apic(char *str)
120{
121 disable_x2apic = 1;
122 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
123 return 0;
124}
125early_param("nox2apic", setup_nox2apic);
126#endif
127
128unsigned long mp_lapic_addr;
129int disable_apic;
130/* Disable local APIC timer from the kernel commandline or via dmi quirk */
131static int disable_apic_timer __cpuinitdata;
132/* Local APIC timer works in C2 */
133int local_apic_timer_c2_ok;
134EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
135
136int first_system_vector = 0xfe;
137
138/*
139 * Debug level, exported for io_apic.c
140 */
141unsigned int apic_verbosity;
142
143int pic_mode;
144
145/* Have we found an MP table */
146int smp_found_config;
147
148static struct resource lapic_resource = {
149 .name = "Local APIC",
150 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
151};
152
153static unsigned int calibration_result;
154
155static int lapic_next_event(unsigned long delta,
156 struct clock_event_device *evt);
157static void lapic_timer_setup(enum clock_event_mode mode,
158 struct clock_event_device *evt);
159static void lapic_timer_broadcast(const struct cpumask *mask);
160static void apic_pm_activate(void);
161
162/*
163 * The local apic timer can be used for any function which is CPU local.
164 */
165static struct clock_event_device lapic_clockevent = {
166 .name = "lapic",
167 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
168 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
169 .shift = 32,
170 .set_mode = lapic_timer_setup,
171 .set_next_event = lapic_next_event,
172 .broadcast = lapic_timer_broadcast,
173 .rating = 100,
174 .irq = -1,
175};
176static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
177
178static unsigned long apic_phys;
179
180/*
181 * Get the LAPIC version
182 */
183static inline int lapic_get_version(void)
184{
185 return GET_APIC_VERSION(apic_read(APIC_LVR));
186}
187
188/*
189 * Check, if the APIC is integrated or a separate chip
190 */
191static inline int lapic_is_integrated(void)
192{
193#ifdef CONFIG_X86_64
194 return 1;
195#else
196 return APIC_INTEGRATED(lapic_get_version());
197#endif
198}
199
200/*
201 * Check, whether this is a modern or a first generation APIC
202 */
203static int modern_apic(void)
204{
205 /* AMD systems use old APIC versions, so check the CPU */
206 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
207 boot_cpu_data.x86 >= 0xf)
208 return 1;
209 return lapic_get_version() >= 0x14;
210}
211
212void native_apic_wait_icr_idle(void)
213{
214 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
215 cpu_relax();
216}
217
218u32 native_safe_apic_wait_icr_idle(void)
219{
220 u32 send_status;
221 int timeout;
222
223 timeout = 0;
224 do {
225 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
226 if (!send_status)
227 break;
228 udelay(100);
229 } while (timeout++ < 1000);
230
231 return send_status;
232}
233
234void native_apic_icr_write(u32 low, u32 id)
235{
236 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
237 apic_write(APIC_ICR, low);
238}
239
240u64 native_apic_icr_read(void)
241{
242 u32 icr1, icr2;
243
244 icr2 = apic_read(APIC_ICR2);
245 icr1 = apic_read(APIC_ICR);
246
247 return icr1 | ((u64)icr2 << 32);
248}
249
250/**
251 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
252 */
253void __cpuinit enable_NMI_through_LVT0(void)
254{
255 unsigned int v;
256
257 /* unmask and set to NMI */
258 v = APIC_DM_NMI;
259
260 /* Level triggered for 82489DX (32bit mode) */
261 if (!lapic_is_integrated())
262 v |= APIC_LVT_LEVEL_TRIGGER;
263
264 apic_write(APIC_LVT0, v);
265}
266
267#ifdef CONFIG_X86_32
268/**
269 * get_physical_broadcast - Get number of physical broadcast IDs
270 */
271int get_physical_broadcast(void)
272{
273 return modern_apic() ? 0xff : 0xf;
274}
275#endif
276
277/**
278 * lapic_get_maxlvt - get the maximum number of local vector table entries
279 */
280int lapic_get_maxlvt(void)
281{
282 unsigned int v;
283
284 v = apic_read(APIC_LVR);
285 /*
286 * - we always have APIC integrated on 64bit mode
287 * - 82489DXs do not report # of LVT entries
288 */
289 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
290}
291
292/*
293 * Local APIC timer
294 */
295
296/* Clock divisor */
297#define APIC_DIVISOR 16
298
299/*
300 * This function sets up the local APIC timer, with a timeout of
301 * 'clocks' APIC bus clock. During calibration we actually call
302 * this function twice on the boot CPU, once with a bogus timeout
303 * value, second time for real. The other (noncalibrating) CPUs
304 * call this function only once, with the real, calibrated value.
305 *
306 * We do reads before writes even if unnecessary, to get around the
307 * P5 APIC double write bug.
308 */
309static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
310{
311 unsigned int lvtt_value, tmp_value;
312
313 lvtt_value = LOCAL_TIMER_VECTOR;
314 if (!oneshot)
315 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
316 if (!lapic_is_integrated())
317 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
318
319 if (!irqen)
320 lvtt_value |= APIC_LVT_MASKED;
321
322 apic_write(APIC_LVTT, lvtt_value);
323
324 /*
325 * Divide PICLK by 16
326 */
327 tmp_value = apic_read(APIC_TDCR);
328 apic_write(APIC_TDCR,
329 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
330 APIC_TDR_DIV_16);
331
332 if (!oneshot)
333 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
334}
335
336/*
337 * Setup extended LVT, AMD specific (K8, family 10h)
338 *
339 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
340 * MCE interrupts are supported. Thus MCE offset must be set to 0.
341 *
342 * If mask=1, the LVT entry does not generate interrupts while mask=0
343 * enables the vector. See also the BKDGs.
344 */
345
346#define APIC_EILVT_LVTOFF_MCE 0
347#define APIC_EILVT_LVTOFF_IBS 1
348
349static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
350{
351 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
352 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
353
354 apic_write(reg, v);
355}
356
357u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
358{
359 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
360 return APIC_EILVT_LVTOFF_MCE;
361}
362
363u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
364{
365 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
366 return APIC_EILVT_LVTOFF_IBS;
367}
368EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
369
370/*
371 * Program the next event, relative to now
372 */
373static int lapic_next_event(unsigned long delta,
374 struct clock_event_device *evt)
375{
376 apic_write(APIC_TMICT, delta);
377 return 0;
378}
379
380/*
381 * Setup the lapic timer in periodic or oneshot mode
382 */
383static void lapic_timer_setup(enum clock_event_mode mode,
384 struct clock_event_device *evt)
385{
386 unsigned long flags;
387 unsigned int v;
388
389 /* Lapic used as dummy for broadcast ? */
390 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
391 return;
392
393 local_irq_save(flags);
394
395 switch (mode) {
396 case CLOCK_EVT_MODE_PERIODIC:
397 case CLOCK_EVT_MODE_ONESHOT:
398 __setup_APIC_LVTT(calibration_result,
399 mode != CLOCK_EVT_MODE_PERIODIC, 1);
400 break;
401 case CLOCK_EVT_MODE_UNUSED:
402 case CLOCK_EVT_MODE_SHUTDOWN:
403 v = apic_read(APIC_LVTT);
404 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
405 apic_write(APIC_LVTT, v);
406 apic_write(APIC_TMICT, 0xffffffff);
407 break;
408 case CLOCK_EVT_MODE_RESUME:
409 /* Nothing to do here */
410 break;
411 }
412
413 local_irq_restore(flags);
414}
415
416/*
417 * Local APIC timer broadcast function
418 */
419static void lapic_timer_broadcast(const struct cpumask *mask)
420{
421#ifdef CONFIG_SMP
422 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
423#endif
424}
425
426/*
427 * Setup the local APIC timer for this CPU. Copy the initilized values
428 * of the boot CPU and register the clock event in the framework.
429 */
430static void __cpuinit setup_APIC_timer(void)
431{
432 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
433
434 memcpy(levt, &lapic_clockevent, sizeof(*levt));
435 levt->cpumask = cpumask_of(smp_processor_id());
436
437 clockevents_register_device(levt);
438}
439
440/*
441 * In this functions we calibrate APIC bus clocks to the external timer.
442 *
443 * We want to do the calibration only once since we want to have local timer
444 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
445 * frequency.
446 *
447 * This was previously done by reading the PIT/HPET and waiting for a wrap
448 * around to find out, that a tick has elapsed. I have a box, where the PIT
449 * readout is broken, so it never gets out of the wait loop again. This was
450 * also reported by others.
451 *
452 * Monitoring the jiffies value is inaccurate and the clockevents
453 * infrastructure allows us to do a simple substitution of the interrupt
454 * handler.
455 *
456 * The calibration routine also uses the pm_timer when possible, as the PIT
457 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
458 * back to normal later in the boot process).
459 */
460
461#define LAPIC_CAL_LOOPS (HZ/10)
462
463static __initdata int lapic_cal_loops = -1;
464static __initdata long lapic_cal_t1, lapic_cal_t2;
465static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
466static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
467static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
468
469/*
470 * Temporary interrupt handler.
471 */
472static void __init lapic_cal_handler(struct clock_event_device *dev)
473{
474 unsigned long long tsc = 0;
475 long tapic = apic_read(APIC_TMCCT);
476 unsigned long pm = acpi_pm_read_early();
477
478 if (cpu_has_tsc)
479 rdtscll(tsc);
480
481 switch (lapic_cal_loops++) {
482 case 0:
483 lapic_cal_t1 = tapic;
484 lapic_cal_tsc1 = tsc;
485 lapic_cal_pm1 = pm;
486 lapic_cal_j1 = jiffies;
487 break;
488
489 case LAPIC_CAL_LOOPS:
490 lapic_cal_t2 = tapic;
491 lapic_cal_tsc2 = tsc;
492 if (pm < lapic_cal_pm1)
493 pm += ACPI_PM_OVRRUN;
494 lapic_cal_pm2 = pm;
495 lapic_cal_j2 = jiffies;
496 break;
497 }
498}
499
500static int __init
501calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
502{
503 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
504 const long pm_thresh = pm_100ms / 100;
505 unsigned long mult;
506 u64 res;
507
508#ifndef CONFIG_X86_PM_TIMER
509 return -1;
510#endif
511
512 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
513
514 /* Check, if the PM timer is available */
515 if (!deltapm)
516 return -1;
517
518 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
519
520 if (deltapm > (pm_100ms - pm_thresh) &&
521 deltapm < (pm_100ms + pm_thresh)) {
522 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
523 return 0;
524 }
525
526 res = (((u64)deltapm) * mult) >> 22;
527 do_div(res, 1000000);
528 pr_warning("APIC calibration not consistent "
529 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
530
531 /* Correct the lapic counter value */
532 res = (((u64)(*delta)) * pm_100ms);
533 do_div(res, deltapm);
534 pr_info("APIC delta adjusted to PM-Timer: "
535 "%lu (%ld)\n", (unsigned long)res, *delta);
536 *delta = (long)res;
537
538 /* Correct the tsc counter value */
539 if (cpu_has_tsc) {
540 res = (((u64)(*deltatsc)) * pm_100ms);
541 do_div(res, deltapm);
542 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
543 "PM-Timer: %lu (%ld) \n",
544 (unsigned long)res, *deltatsc);
545 *deltatsc = (long)res;
546 }
547
548 return 0;
549}
550
551static int __init calibrate_APIC_clock(void)
552{
553 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
554 void (*real_handler)(struct clock_event_device *dev);
555 unsigned long deltaj;
556 long delta, deltatsc;
557 int pm_referenced = 0;
558
559 local_irq_disable();
560
561 /* Replace the global interrupt handler */
562 real_handler = global_clock_event->event_handler;
563 global_clock_event->event_handler = lapic_cal_handler;
564
565 /*
566 * Setup the APIC counter to maximum. There is no way the lapic
567 * can underflow in the 100ms detection time frame
568 */
569 __setup_APIC_LVTT(0xffffffff, 0, 0);
570
571 /* Let the interrupts run */
572 local_irq_enable();
573
574 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
575 cpu_relax();
576
577 local_irq_disable();
578
579 /* Restore the real event handler */
580 global_clock_event->event_handler = real_handler;
581
582 /* Build delta t1-t2 as apic timer counts down */
583 delta = lapic_cal_t1 - lapic_cal_t2;
584 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
585
586 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
587
588 /* we trust the PM based calibration if possible */
589 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
590 &delta, &deltatsc);
591
592 /* Calculate the scaled math multiplication factor */
593 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
594 lapic_clockevent.shift);
595 lapic_clockevent.max_delta_ns =
596 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
597 lapic_clockevent.min_delta_ns =
598 clockevent_delta2ns(0xF, &lapic_clockevent);
599
600 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
601
602 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
603 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
604 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
605 calibration_result);
606
607 if (cpu_has_tsc) {
608 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
609 "%ld.%04ld MHz.\n",
610 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
611 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
612 }
613
614 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
615 "%u.%04u MHz.\n",
616 calibration_result / (1000000 / HZ),
617 calibration_result % (1000000 / HZ));
618
619 /*
620 * Do a sanity check on the APIC calibration result
621 */
622 if (calibration_result < (1000000 / HZ)) {
623 local_irq_enable();
624 pr_warning("APIC frequency too slow, disabling apic timer\n");
625 return -1;
626 }
627
628 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
629
630 /*
631 * PM timer calibration failed or not turned on
632 * so lets try APIC timer based calibration
633 */
634 if (!pm_referenced) {
635 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
636
637 /*
638 * Setup the apic timer manually
639 */
640 levt->event_handler = lapic_cal_handler;
641 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
642 lapic_cal_loops = -1;
643
644 /* Let the interrupts run */
645 local_irq_enable();
646
647 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
648 cpu_relax();
649
650 /* Stop the lapic timer */
651 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
652
653 /* Jiffies delta */
654 deltaj = lapic_cal_j2 - lapic_cal_j1;
655 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
656
657 /* Check, if the jiffies result is consistent */
658 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
659 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
660 else
661 levt->features |= CLOCK_EVT_FEAT_DUMMY;
662 } else
663 local_irq_enable();
664
665 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
666 pr_warning("APIC timer disabled due to verification failure\n");
667 return -1;
668 }
669
670 return 0;
671}
672
673/*
674 * Setup the boot APIC
675 *
676 * Calibrate and verify the result.
677 */
678void __init setup_boot_APIC_clock(void)
679{
680 /*
681 * The local apic timer can be disabled via the kernel
682 * commandline or from the CPU detection code. Register the lapic
683 * timer as a dummy clock event source on SMP systems, so the
684 * broadcast mechanism is used. On UP systems simply ignore it.
685 */
686 if (disable_apic_timer) {
687 pr_info("Disabling APIC timer\n");
688 /* No broadcast on UP ! */
689 if (num_possible_cpus() > 1) {
690 lapic_clockevent.mult = 1;
691 setup_APIC_timer();
692 }
693 return;
694 }
695
696 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
697 "calibrating APIC timer ...\n");
698
699 if (calibrate_APIC_clock()) {
700 /* No broadcast on UP ! */
701 if (num_possible_cpus() > 1)
702 setup_APIC_timer();
703 return;
704 }
705
706 /*
707 * If nmi_watchdog is set to IO_APIC, we need the
708 * PIT/HPET going. Otherwise register lapic as a dummy
709 * device.
710 */
711 if (nmi_watchdog != NMI_IO_APIC)
712 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
713 else
714 pr_warning("APIC timer registered as dummy,"
715 " due to nmi_watchdog=%d!\n", nmi_watchdog);
716
717 /* Setup the lapic or request the broadcast */
718 setup_APIC_timer();
719}
720
721void __cpuinit setup_secondary_APIC_clock(void)
722{
723 setup_APIC_timer();
724}
725
726/*
727 * The guts of the apic timer interrupt
728 */
729static void local_apic_timer_interrupt(void)
730{
731 int cpu = smp_processor_id();
732 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
733
734 /*
735 * Normally we should not be here till LAPIC has been initialized but
736 * in some cases like kdump, its possible that there is a pending LAPIC
737 * timer interrupt from previous kernel's context and is delivered in
738 * new kernel the moment interrupts are enabled.
739 *
740 * Interrupts are enabled early and LAPIC is setup much later, hence
741 * its possible that when we get here evt->event_handler is NULL.
742 * Check for event_handler being NULL and discard the interrupt as
743 * spurious.
744 */
745 if (!evt->event_handler) {
746 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
747 /* Switch it off */
748 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
749 return;
750 }
751
752 /*
753 * the NMI deadlock-detector uses this.
754 */
755 inc_irq_stat(apic_timer_irqs);
756
757 evt->event_handler(evt);
758}
759
760/*
761 * Local APIC timer interrupt. This is the most natural way for doing
762 * local interrupts, but local timer interrupts can be emulated by
763 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
764 *
765 * [ if a single-CPU system runs an SMP kernel then we call the local
766 * interrupt as well. Thus we cannot inline the local irq ... ]
767 */
768void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
769{
770 struct pt_regs *old_regs = set_irq_regs(regs);
771
772 /*
773 * NOTE! We'd better ACK the irq immediately,
774 * because timer handling can be slow.
775 */
776 ack_APIC_irq();
777 /*
778 * update_process_times() expects us to have done irq_enter().
779 * Besides, if we don't timer interrupts ignore the global
780 * interrupt lock, which is the WrongThing (tm) to do.
781 */
782 exit_idle();
783 irq_enter();
784 local_apic_timer_interrupt();
785 irq_exit();
786
787 set_irq_regs(old_regs);
788}
789
790int setup_profiling_timer(unsigned int multiplier)
791{
792 return -EINVAL;
793}
794
795/*
796 * Local APIC start and shutdown
797 */
798
799/**
800 * clear_local_APIC - shutdown the local APIC
801 *
802 * This is called, when a CPU is disabled and before rebooting, so the state of
803 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
804 * leftovers during boot.
805 */
806void clear_local_APIC(void)
807{
808 int maxlvt;
809 u32 v;
810
811 /* APIC hasn't been mapped yet */
812 if (!apic_phys)
813 return;
814
815 maxlvt = lapic_get_maxlvt();
816 /*
817 * Masking an LVT entry can trigger a local APIC error
818 * if the vector is zero. Mask LVTERR first to prevent this.
819 */
820 if (maxlvt >= 3) {
821 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
822 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
823 }
824 /*
825 * Careful: we have to set masks only first to deassert
826 * any level-triggered sources.
827 */
828 v = apic_read(APIC_LVTT);
829 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
830 v = apic_read(APIC_LVT0);
831 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
832 v = apic_read(APIC_LVT1);
833 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
834 if (maxlvt >= 4) {
835 v = apic_read(APIC_LVTPC);
836 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
837 }
838
839 /* lets not touch this if we didn't frob it */
840#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
841 if (maxlvt >= 5) {
842 v = apic_read(APIC_LVTTHMR);
843 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
844 }
845#endif
846#ifdef CONFIG_X86_MCE_INTEL
847 if (maxlvt >= 6) {
848 v = apic_read(APIC_LVTCMCI);
849 if (!(v & APIC_LVT_MASKED))
850 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
851 }
852#endif
853
854 /*
855 * Clean APIC state for other OSs:
856 */
857 apic_write(APIC_LVTT, APIC_LVT_MASKED);
858 apic_write(APIC_LVT0, APIC_LVT_MASKED);
859 apic_write(APIC_LVT1, APIC_LVT_MASKED);
860 if (maxlvt >= 3)
861 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
862 if (maxlvt >= 4)
863 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
864
865 /* Integrated APIC (!82489DX) ? */
866 if (lapic_is_integrated()) {
867 if (maxlvt > 3)
868 /* Clear ESR due to Pentium errata 3AP and 11AP */
869 apic_write(APIC_ESR, 0);
870 apic_read(APIC_ESR);
871 }
872}
873
874/**
875 * disable_local_APIC - clear and disable the local APIC
876 */
877void disable_local_APIC(void)
878{
879 unsigned int value;
880
881 /* APIC hasn't been mapped yet */
882 if (!apic_phys)
883 return;
884
885 clear_local_APIC();
886
887 /*
888 * Disable APIC (implies clearing of registers
889 * for 82489DX!).
890 */
891 value = apic_read(APIC_SPIV);
892 value &= ~APIC_SPIV_APIC_ENABLED;
893 apic_write(APIC_SPIV, value);
894
895#ifdef CONFIG_X86_32
896 /*
897 * When LAPIC was disabled by the BIOS and enabled by the kernel,
898 * restore the disabled state.
899 */
900 if (enabled_via_apicbase) {
901 unsigned int l, h;
902
903 rdmsr(MSR_IA32_APICBASE, l, h);
904 l &= ~MSR_IA32_APICBASE_ENABLE;
905 wrmsr(MSR_IA32_APICBASE, l, h);
906 }
907#endif
908}
909
910/*
911 * If Linux enabled the LAPIC against the BIOS default disable it down before
912 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
913 * not power-off. Additionally clear all LVT entries before disable_local_APIC
914 * for the case where Linux didn't enable the LAPIC.
915 */
916void lapic_shutdown(void)
917{
918 unsigned long flags;
919
920 if (!cpu_has_apic)
921 return;
922
923 local_irq_save(flags);
924
925#ifdef CONFIG_X86_32
926 if (!enabled_via_apicbase)
927 clear_local_APIC();
928 else
929#endif
930 disable_local_APIC();
931
932
933 local_irq_restore(flags);
934}
935
936/*
937 * This is to verify that we're looking at a real local APIC.
938 * Check these against your board if the CPUs aren't getting
939 * started for no apparent reason.
940 */
941int __init verify_local_APIC(void)
942{
943 unsigned int reg0, reg1;
944
945 /*
946 * The version register is read-only in a real APIC.
947 */
948 reg0 = apic_read(APIC_LVR);
949 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
950 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
951 reg1 = apic_read(APIC_LVR);
952 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
953
954 /*
955 * The two version reads above should print the same
956 * numbers. If the second one is different, then we
957 * poke at a non-APIC.
958 */
959 if (reg1 != reg0)
960 return 0;
961
962 /*
963 * Check if the version looks reasonably.
964 */
965 reg1 = GET_APIC_VERSION(reg0);
966 if (reg1 == 0x00 || reg1 == 0xff)
967 return 0;
968 reg1 = lapic_get_maxlvt();
969 if (reg1 < 0x02 || reg1 == 0xff)
970 return 0;
971
972 /*
973 * The ID register is read/write in a real APIC.
974 */
975 reg0 = apic_read(APIC_ID);
976 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
977 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
978 reg1 = apic_read(APIC_ID);
979 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
980 apic_write(APIC_ID, reg0);
981 if (reg1 != (reg0 ^ apic->apic_id_mask))
982 return 0;
983
984 /*
985 * The next two are just to see if we have sane values.
986 * They're only really relevant if we're in Virtual Wire
987 * compatibility mode, but most boxes are anymore.
988 */
989 reg0 = apic_read(APIC_LVT0);
990 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
991 reg1 = apic_read(APIC_LVT1);
992 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
993
994 return 1;
995}
996
997/**
998 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
999 */
1000void __init sync_Arb_IDs(void)
1001{
1002 /*
1003 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1004 * needed on AMD.
1005 */
1006 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1007 return;
1008
1009 /*
1010 * Wait for idle.
1011 */
1012 apic_wait_icr_idle();
1013
1014 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1015 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1016 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1017}
1018
1019/*
1020 * An initial setup of the virtual wire mode.
1021 */
1022void __init init_bsp_APIC(void)
1023{
1024 unsigned int value;
1025
1026 /*
1027 * Don't do the setup now if we have a SMP BIOS as the
1028 * through-I/O-APIC virtual wire mode might be active.
1029 */
1030 if (smp_found_config || !cpu_has_apic)
1031 return;
1032
1033 /*
1034 * Do not trust the local APIC being empty at bootup.
1035 */
1036 clear_local_APIC();
1037
1038 /*
1039 * Enable APIC.
1040 */
1041 value = apic_read(APIC_SPIV);
1042 value &= ~APIC_VECTOR_MASK;
1043 value |= APIC_SPIV_APIC_ENABLED;
1044
1045#ifdef CONFIG_X86_32
1046 /* This bit is reserved on P4/Xeon and should be cleared */
1047 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1048 (boot_cpu_data.x86 == 15))
1049 value &= ~APIC_SPIV_FOCUS_DISABLED;
1050 else
1051#endif
1052 value |= APIC_SPIV_FOCUS_DISABLED;
1053 value |= SPURIOUS_APIC_VECTOR;
1054 apic_write(APIC_SPIV, value);
1055
1056 /*
1057 * Set up the virtual wire mode.
1058 */
1059 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1060 value = APIC_DM_NMI;
1061 if (!lapic_is_integrated()) /* 82489DX */
1062 value |= APIC_LVT_LEVEL_TRIGGER;
1063 apic_write(APIC_LVT1, value);
1064}
1065
1066static void __cpuinit lapic_setup_esr(void)
1067{
1068 unsigned int oldvalue, value, maxlvt;
1069
1070 if (!lapic_is_integrated()) {
1071 pr_info("No ESR for 82489DX.\n");
1072 return;
1073 }
1074
1075 if (apic->disable_esr) {
1076 /*
1077 * Something untraceable is creating bad interrupts on
1078 * secondary quads ... for the moment, just leave the
1079 * ESR disabled - we can't do anything useful with the
1080 * errors anyway - mbligh
1081 */
1082 pr_info("Leaving ESR disabled.\n");
1083 return;
1084 }
1085
1086 maxlvt = lapic_get_maxlvt();
1087 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1088 apic_write(APIC_ESR, 0);
1089 oldvalue = apic_read(APIC_ESR);
1090
1091 /* enables sending errors */
1092 value = ERROR_APIC_VECTOR;
1093 apic_write(APIC_LVTERR, value);
1094
1095 /*
1096 * spec says clear errors after enabling vector.
1097 */
1098 if (maxlvt > 3)
1099 apic_write(APIC_ESR, 0);
1100 value = apic_read(APIC_ESR);
1101 if (value != oldvalue)
1102 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1103 "vector: 0x%08x after: 0x%08x\n",
1104 oldvalue, value);
1105}
1106
1107
1108/**
1109 * setup_local_APIC - setup the local APIC
1110 */
1111void __cpuinit setup_local_APIC(void)
1112{
1113 unsigned int value;
1114 int i, j;
1115
1116 if (disable_apic) {
1117 arch_disable_smp_support();
1118 return;
1119 }
1120
1121#ifdef CONFIG_X86_32
1122 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1123 if (lapic_is_integrated() && apic->disable_esr) {
1124 apic_write(APIC_ESR, 0);
1125 apic_write(APIC_ESR, 0);
1126 apic_write(APIC_ESR, 0);
1127 apic_write(APIC_ESR, 0);
1128 }
1129#endif
1130
1131 preempt_disable();
1132
1133 /*
1134 * Double-check whether this APIC is really registered.
1135 * This is meaningless in clustered apic mode, so we skip it.
1136 */
1137 if (!apic->apic_id_registered())
1138 BUG();
1139
1140 /*
1141 * Intel recommends to set DFR, LDR and TPR before enabling
1142 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1143 * document number 292116). So here it goes...
1144 */
1145 apic->init_apic_ldr();
1146
1147 /*
1148 * Set Task Priority to 'accept all'. We never change this
1149 * later on.
1150 */
1151 value = apic_read(APIC_TASKPRI);
1152 value &= ~APIC_TPRI_MASK;
1153 apic_write(APIC_TASKPRI, value);
1154
1155 /*
1156 * After a crash, we no longer service the interrupts and a pending
1157 * interrupt from previous kernel might still have ISR bit set.
1158 *
1159 * Most probably by now CPU has serviced that pending interrupt and
1160 * it might not have done the ack_APIC_irq() because it thought,
1161 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1162 * does not clear the ISR bit and cpu thinks it has already serivced
1163 * the interrupt. Hence a vector might get locked. It was noticed
1164 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1165 */
1166 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1167 value = apic_read(APIC_ISR + i*0x10);
1168 for (j = 31; j >= 0; j--) {
1169 if (value & (1<<j))
1170 ack_APIC_irq();
1171 }
1172 }
1173
1174 /*
1175 * Now that we are all set up, enable the APIC
1176 */
1177 value = apic_read(APIC_SPIV);
1178 value &= ~APIC_VECTOR_MASK;
1179 /*
1180 * Enable APIC
1181 */
1182 value |= APIC_SPIV_APIC_ENABLED;
1183
1184#ifdef CONFIG_X86_32
1185 /*
1186 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1187 * certain networking cards. If high frequency interrupts are
1188 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1189 * entry is masked/unmasked at a high rate as well then sooner or
1190 * later IOAPIC line gets 'stuck', no more interrupts are received
1191 * from the device. If focus CPU is disabled then the hang goes
1192 * away, oh well :-(
1193 *
1194 * [ This bug can be reproduced easily with a level-triggered
1195 * PCI Ne2000 networking cards and PII/PIII processors, dual
1196 * BX chipset. ]
1197 */
1198 /*
1199 * Actually disabling the focus CPU check just makes the hang less
1200 * frequent as it makes the interrupt distributon model be more
1201 * like LRU than MRU (the short-term load is more even across CPUs).
1202 * See also the comment in end_level_ioapic_irq(). --macro
1203 */
1204
1205 /*
1206 * - enable focus processor (bit==0)
1207 * - 64bit mode always use processor focus
1208 * so no need to set it
1209 */
1210 value &= ~APIC_SPIV_FOCUS_DISABLED;
1211#endif
1212
1213 /*
1214 * Set spurious IRQ vector
1215 */
1216 value |= SPURIOUS_APIC_VECTOR;
1217 apic_write(APIC_SPIV, value);
1218
1219 /*
1220 * Set up LVT0, LVT1:
1221 *
1222 * set up through-local-APIC on the BP's LINT0. This is not
1223 * strictly necessary in pure symmetric-IO mode, but sometimes
1224 * we delegate interrupts to the 8259A.
1225 */
1226 /*
1227 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1228 */
1229 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1230 if (!smp_processor_id() && (pic_mode || !value)) {
1231 value = APIC_DM_EXTINT;
1232 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1233 smp_processor_id());
1234 } else {
1235 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1236 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1237 smp_processor_id());
1238 }
1239 apic_write(APIC_LVT0, value);
1240
1241 /*
1242 * only the BP should see the LINT1 NMI signal, obviously.
1243 */
1244 if (!smp_processor_id())
1245 value = APIC_DM_NMI;
1246 else
1247 value = APIC_DM_NMI | APIC_LVT_MASKED;
1248 if (!lapic_is_integrated()) /* 82489DX */
1249 value |= APIC_LVT_LEVEL_TRIGGER;
1250 apic_write(APIC_LVT1, value);
1251
1252 preempt_enable();
1253
1254#ifdef CONFIG_X86_MCE_INTEL
1255 /* Recheck CMCI information after local APIC is up on CPU #0 */
1256 if (smp_processor_id() == 0)
1257 cmci_recheck();
1258#endif
1259}
1260
1261void __cpuinit end_local_APIC_setup(void)
1262{
1263 lapic_setup_esr();
1264
1265#ifdef CONFIG_X86_32
1266 {
1267 unsigned int value;
1268 /* Disable the local apic timer */
1269 value = apic_read(APIC_LVTT);
1270 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1271 apic_write(APIC_LVTT, value);
1272 }
1273#endif
1274
1275 setup_apic_nmi_watchdog(NULL);
1276 apic_pm_activate();
1277}
1278
1279#ifdef CONFIG_X86_X2APIC
1280void check_x2apic(void)
1281{
1282 if (x2apic_enabled()) {
1283 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1284 x2apic_preenabled = x2apic = 1;
1285 }
1286}
1287
1288void enable_x2apic(void)
1289{
1290 int msr, msr2;
1291
1292 if (!x2apic)
1293 return;
1294
1295 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1296 if (!(msr & X2APIC_ENABLE)) {
1297 pr_info("Enabling x2apic\n");
1298 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1299 }
1300}
1301
1302void __init enable_IR_x2apic(void)
1303{
1304#ifdef CONFIG_INTR_REMAP
1305 int ret;
1306 unsigned long flags;
1307
1308 if (!cpu_has_x2apic)
1309 return;
1310
1311 if (!x2apic_preenabled && disable_x2apic) {
1312 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1313 "because of nox2apic\n");
1314 return;
1315 }
1316
1317 if (x2apic_preenabled && disable_x2apic)
1318 panic("Bios already enabled x2apic, can't enforce nox2apic");
1319
1320 if (!x2apic_preenabled && skip_ioapic_setup) {
1321 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1322 "because of skipping io-apic setup\n");
1323 return;
1324 }
1325
1326 ret = dmar_table_init();
1327 if (ret) {
1328 pr_info("dmar_table_init() failed with %d:\n", ret);
1329
1330 if (x2apic_preenabled)
1331 panic("x2apic enabled by bios. But IR enabling failed");
1332 else
1333 pr_info("Not enabling x2apic,Intr-remapping\n");
1334 return;
1335 }
1336
1337 local_irq_save(flags);
1338 mask_8259A();
1339
1340 ret = save_mask_IO_APIC_setup();
1341 if (ret) {
1342 pr_info("Saving IO-APIC state failed: %d\n", ret);
1343 goto end;
1344 }
1345
1346 ret = enable_intr_remapping(1);
1347
1348 if (ret && x2apic_preenabled) {
1349 local_irq_restore(flags);
1350 panic("x2apic enabled by bios. But IR enabling failed");
1351 }
1352
1353 if (ret)
1354 goto end_restore;
1355
1356 if (!x2apic) {
1357 x2apic = 1;
1358 enable_x2apic();
1359 }
1360
1361end_restore:
1362 if (ret)
1363 /*
1364 * IR enabling failed
1365 */
1366 restore_IO_APIC_setup();
1367 else
1368 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1369
1370end:
1371 unmask_8259A();
1372 local_irq_restore(flags);
1373
1374 if (!ret) {
1375 if (!x2apic_preenabled)
1376 pr_info("Enabled x2apic and interrupt-remapping\n");
1377 else
1378 pr_info("Enabled Interrupt-remapping\n");
1379 } else
1380 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1381#else
1382 if (!cpu_has_x2apic)
1383 return;
1384
1385 if (x2apic_preenabled)
1386 panic("x2apic enabled prior OS handover,"
1387 " enable CONFIG_INTR_REMAP");
1388
1389 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1390 " and x2apic\n");
1391#endif
1392
1393 return;
1394}
1395#endif /* CONFIG_X86_X2APIC */
1396
1397#ifdef CONFIG_X86_64
1398/*
1399 * Detect and enable local APICs on non-SMP boards.
1400 * Original code written by Keir Fraser.
1401 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1402 * not correctly set up (usually the APIC timer won't work etc.)
1403 */
1404static int __init detect_init_APIC(void)
1405{
1406 if (!cpu_has_apic) {
1407 pr_info("No local APIC present\n");
1408 return -1;
1409 }
1410
1411 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1412 boot_cpu_physical_apicid = 0;
1413 return 0;
1414}
1415#else
1416/*
1417 * Detect and initialize APIC
1418 */
1419static int __init detect_init_APIC(void)
1420{
1421 u32 h, l, features;
1422
1423 /* Disabled by kernel option? */
1424 if (disable_apic)
1425 return -1;
1426
1427 switch (boot_cpu_data.x86_vendor) {
1428 case X86_VENDOR_AMD:
1429 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1430 (boot_cpu_data.x86 >= 15))
1431 break;
1432 goto no_apic;
1433 case X86_VENDOR_INTEL:
1434 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1435 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1436 break;
1437 goto no_apic;
1438 default:
1439 goto no_apic;
1440 }
1441
1442 if (!cpu_has_apic) {
1443 /*
1444 * Over-ride BIOS and try to enable the local APIC only if
1445 * "lapic" specified.
1446 */
1447 if (!force_enable_local_apic) {
1448 pr_info("Local APIC disabled by BIOS -- "
1449 "you can enable it with \"lapic\"\n");
1450 return -1;
1451 }
1452 /*
1453 * Some BIOSes disable the local APIC in the APIC_BASE
1454 * MSR. This can only be done in software for Intel P6 or later
1455 * and AMD K7 (Model > 1) or later.
1456 */
1457 rdmsr(MSR_IA32_APICBASE, l, h);
1458 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1459 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1460 l &= ~MSR_IA32_APICBASE_BASE;
1461 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1462 wrmsr(MSR_IA32_APICBASE, l, h);
1463 enabled_via_apicbase = 1;
1464 }
1465 }
1466 /*
1467 * The APIC feature bit should now be enabled
1468 * in `cpuid'
1469 */
1470 features = cpuid_edx(1);
1471 if (!(features & (1 << X86_FEATURE_APIC))) {
1472 pr_warning("Could not enable APIC!\n");
1473 return -1;
1474 }
1475 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1476 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1477
1478 /* The BIOS may have set up the APIC at some other address */
1479 rdmsr(MSR_IA32_APICBASE, l, h);
1480 if (l & MSR_IA32_APICBASE_ENABLE)
1481 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1482
1483 pr_info("Found and enabled local APIC!\n");
1484
1485 apic_pm_activate();
1486
1487 return 0;
1488
1489no_apic:
1490 pr_info("No local APIC present or hardware disabled\n");
1491 return -1;
1492}
1493#endif
1494
1495#ifdef CONFIG_X86_64
1496void __init early_init_lapic_mapping(void)
1497{
1498 unsigned long phys_addr;
1499
1500 /*
1501 * If no local APIC can be found then go out
1502 * : it means there is no mpatable and MADT
1503 */
1504 if (!smp_found_config)
1505 return;
1506
1507 phys_addr = mp_lapic_addr;
1508
1509 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1510 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1511 APIC_BASE, phys_addr);
1512
1513 /*
1514 * Fetch the APIC ID of the BSP in case we have a
1515 * default configuration (or the MP table is broken).
1516 */
1517 boot_cpu_physical_apicid = read_apic_id();
1518}
1519#endif
1520
1521/**
1522 * init_apic_mappings - initialize APIC mappings
1523 */
1524void __init init_apic_mappings(void)
1525{
1526#ifdef CONFIG_X86_X2APIC
1527 if (x2apic) {
1528 boot_cpu_physical_apicid = read_apic_id();
1529 return;
1530 }
1531#endif
1532
1533 /*
1534 * If no local APIC can be found then set up a fake all
1535 * zeroes page to simulate the local APIC and another
1536 * one for the IO-APIC.
1537 */
1538 if (!smp_found_config && detect_init_APIC()) {
1539 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1540 apic_phys = __pa(apic_phys);
1541 } else
1542 apic_phys = mp_lapic_addr;
1543
1544 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1545 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1546 APIC_BASE, apic_phys);
1547
1548 /*
1549 * Fetch the APIC ID of the BSP in case we have a
1550 * default configuration (or the MP table is broken).
1551 */
1552 if (boot_cpu_physical_apicid == -1U)
1553 boot_cpu_physical_apicid = read_apic_id();
1554}
1555
1556/*
1557 * This initializes the IO-APIC and APIC hardware if this is
1558 * a UP kernel.
1559 */
1560int apic_version[MAX_APICS];
1561
1562int __init APIC_init_uniprocessor(void)
1563{
1564 if (disable_apic) {
1565 pr_info("Apic disabled\n");
1566 return -1;
1567 }
1568#ifdef CONFIG_X86_64
1569 if (!cpu_has_apic) {
1570 disable_apic = 1;
1571 pr_info("Apic disabled by BIOS\n");
1572 return -1;
1573 }
1574#else
1575 if (!smp_found_config && !cpu_has_apic)
1576 return -1;
1577
1578 /*
1579 * Complain if the BIOS pretends there is one.
1580 */
1581 if (!cpu_has_apic &&
1582 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1583 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1584 boot_cpu_physical_apicid);
1585 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1586 return -1;
1587 }
1588#endif
1589
1590 enable_IR_x2apic();
1591#ifdef CONFIG_X86_64
1592 default_setup_apic_routing();
1593#endif
1594
1595 verify_local_APIC();
1596 connect_bsp_APIC();
1597
1598#ifdef CONFIG_X86_64
1599 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1600#else
1601 /*
1602 * Hack: In case of kdump, after a crash, kernel might be booting
1603 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1604 * might be zero if read from MP tables. Get it from LAPIC.
1605 */
1606# ifdef CONFIG_CRASH_DUMP
1607 boot_cpu_physical_apicid = read_apic_id();
1608# endif
1609#endif
1610 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1611 setup_local_APIC();
1612
1613#ifdef CONFIG_X86_IO_APIC
1614 /*
1615 * Now enable IO-APICs, actually call clear_IO_APIC
1616 * We need clear_IO_APIC before enabling error vector
1617 */
1618 if (!skip_ioapic_setup && nr_ioapics)
1619 enable_IO_APIC();
1620#endif
1621
1622 end_local_APIC_setup();
1623
1624#ifdef CONFIG_X86_IO_APIC
1625 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1626 setup_IO_APIC();
1627 else {
1628 nr_ioapics = 0;
1629 localise_nmi_watchdog();
1630 }
1631#else
1632 localise_nmi_watchdog();
1633#endif
1634
1635 setup_boot_clock();
1636#ifdef CONFIG_X86_64
1637 check_nmi_watchdog();
1638#endif
1639
1640 return 0;
1641}
1642
1643/*
1644 * Local APIC interrupts
1645 */
1646
1647/*
1648 * This interrupt should _never_ happen with our APIC/SMP architecture
1649 */
1650void smp_spurious_interrupt(struct pt_regs *regs)
1651{
1652 u32 v;
1653
1654 exit_idle();
1655 irq_enter();
1656 /*
1657 * Check if this really is a spurious interrupt and ACK it
1658 * if it is a vectored one. Just in case...
1659 * Spurious interrupts should not be ACKed.
1660 */
1661 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1662 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1663 ack_APIC_irq();
1664
1665 inc_irq_stat(irq_spurious_count);
1666
1667 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1668 pr_info("spurious APIC interrupt on CPU#%d, "
1669 "should never happen.\n", smp_processor_id());
1670 irq_exit();
1671}
1672
1673/*
1674 * This interrupt should never happen with our APIC/SMP architecture
1675 */
1676void smp_error_interrupt(struct pt_regs *regs)
1677{
1678 u32 v, v1;
1679
1680 exit_idle();
1681 irq_enter();
1682 /* First tickle the hardware, only then report what went on. -- REW */
1683 v = apic_read(APIC_ESR);
1684 apic_write(APIC_ESR, 0);
1685 v1 = apic_read(APIC_ESR);
1686 ack_APIC_irq();
1687 atomic_inc(&irq_err_count);
1688
1689 /*
1690 * Here is what the APIC error bits mean:
1691 * 0: Send CS error
1692 * 1: Receive CS error
1693 * 2: Send accept error
1694 * 3: Receive accept error
1695 * 4: Reserved
1696 * 5: Send illegal vector
1697 * 6: Received illegal vector
1698 * 7: Illegal register address
1699 */
1700 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1701 smp_processor_id(), v , v1);
1702 irq_exit();
1703}
1704
1705/**
1706 * connect_bsp_APIC - attach the APIC to the interrupt system
1707 */
1708void __init connect_bsp_APIC(void)
1709{
1710#ifdef CONFIG_X86_32
1711 if (pic_mode) {
1712 /*
1713 * Do not trust the local APIC being empty at bootup.
1714 */
1715 clear_local_APIC();
1716 /*
1717 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1718 * local APIC to INT and NMI lines.
1719 */
1720 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1721 "enabling APIC mode.\n");
1722 outb(0x70, 0x22);
1723 outb(0x01, 0x23);
1724 }
1725#endif
1726 if (apic->enable_apic_mode)
1727 apic->enable_apic_mode();
1728}
1729
1730/**
1731 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1732 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1733 *
1734 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1735 * APIC is disabled.
1736 */
1737void disconnect_bsp_APIC(int virt_wire_setup)
1738{
1739 unsigned int value;
1740
1741#ifdef CONFIG_X86_32
1742 if (pic_mode) {
1743 /*
1744 * Put the board back into PIC mode (has an effect only on
1745 * certain older boards). Note that APIC interrupts, including
1746 * IPIs, won't work beyond this point! The only exception are
1747 * INIT IPIs.
1748 */
1749 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1750 "entering PIC mode.\n");
1751 outb(0x70, 0x22);
1752 outb(0x00, 0x23);
1753 return;
1754 }
1755#endif
1756
1757 /* Go back to Virtual Wire compatibility mode */
1758
1759 /* For the spurious interrupt use vector F, and enable it */
1760 value = apic_read(APIC_SPIV);
1761 value &= ~APIC_VECTOR_MASK;
1762 value |= APIC_SPIV_APIC_ENABLED;
1763 value |= 0xf;
1764 apic_write(APIC_SPIV, value);
1765
1766 if (!virt_wire_setup) {
1767 /*
1768 * For LVT0 make it edge triggered, active high,
1769 * external and enabled
1770 */
1771 value = apic_read(APIC_LVT0);
1772 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1773 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1774 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1775 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1776 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1777 apic_write(APIC_LVT0, value);
1778 } else {
1779 /* Disable LVT0 */
1780 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1781 }
1782
1783 /*
1784 * For LVT1 make it edge triggered, active high,
1785 * nmi and enabled
1786 */
1787 value = apic_read(APIC_LVT1);
1788 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1789 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1790 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1791 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1792 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1793 apic_write(APIC_LVT1, value);
1794}
1795
1796void __cpuinit generic_processor_info(int apicid, int version)
1797{
1798 int cpu;
1799
1800 /*
1801 * Validate version
1802 */
1803 if (version == 0x0) {
1804 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1805 "fixing up to 0x10. (tell your hw vendor)\n",
1806 version);
1807 version = 0x10;
1808 }
1809 apic_version[apicid] = version;
1810
1811 if (num_processors >= nr_cpu_ids) {
1812 int max = nr_cpu_ids;
1813 int thiscpu = max + disabled_cpus;
1814
1815 pr_warning(
1816 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1817 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1818
1819 disabled_cpus++;
1820 return;
1821 }
1822
1823 num_processors++;
1824 cpu = cpumask_next_zero(-1, cpu_present_mask);
1825
1826 if (version != apic_version[boot_cpu_physical_apicid])
1827 WARN_ONCE(1,
1828 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1829 apic_version[boot_cpu_physical_apicid], cpu, version);
1830
1831 physid_set(apicid, phys_cpu_present_map);
1832 if (apicid == boot_cpu_physical_apicid) {
1833 /*
1834 * x86_bios_cpu_apicid is required to have processors listed
1835 * in same order as logical cpu numbers. Hence the first
1836 * entry is BSP, and so on.
1837 */
1838 cpu = 0;
1839 }
1840 if (apicid > max_physical_apicid)
1841 max_physical_apicid = apicid;
1842
1843#ifdef CONFIG_X86_32
1844 /*
1845 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1846 * but we need to work other dependencies like SMP_SUSPEND etc
1847 * before this can be done without some confusion.
1848 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1849 * - Ashok Raj <ashok.raj@intel.com>
1850 */
1851 if (max_physical_apicid >= 8) {
1852 switch (boot_cpu_data.x86_vendor) {
1853 case X86_VENDOR_INTEL:
1854 if (!APIC_XAPIC(version)) {
1855 def_to_bigsmp = 0;
1856 break;
1857 }
1858 /* If P4 and above fall through */
1859 case X86_VENDOR_AMD:
1860 def_to_bigsmp = 1;
1861 }
1862 }
1863#endif
1864
1865#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1866 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1867 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1868#endif
1869
1870 set_cpu_possible(cpu, true);
1871 set_cpu_present(cpu, true);
1872}
1873
1874int hard_smp_processor_id(void)
1875{
1876 return read_apic_id();
1877}
1878
1879void default_init_apic_ldr(void)
1880{
1881 unsigned long val;
1882
1883 apic_write(APIC_DFR, APIC_DFR_VALUE);
1884 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1885 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1886 apic_write(APIC_LDR, val);
1887}
1888
1889#ifdef CONFIG_X86_32
1890int default_apicid_to_node(int logical_apicid)
1891{
1892#ifdef CONFIG_SMP
1893 return apicid_2_node[hard_smp_processor_id()];
1894#else
1895 return 0;
1896#endif
1897}
1898#endif
1899
1900/*
1901 * Power management
1902 */
1903#ifdef CONFIG_PM
1904
1905static struct {
1906 /*
1907 * 'active' is true if the local APIC was enabled by us and
1908 * not the BIOS; this signifies that we are also responsible
1909 * for disabling it before entering apm/acpi suspend
1910 */
1911 int active;
1912 /* r/w apic fields */
1913 unsigned int apic_id;
1914 unsigned int apic_taskpri;
1915 unsigned int apic_ldr;
1916 unsigned int apic_dfr;
1917 unsigned int apic_spiv;
1918 unsigned int apic_lvtt;
1919 unsigned int apic_lvtpc;
1920 unsigned int apic_lvt0;
1921 unsigned int apic_lvt1;
1922 unsigned int apic_lvterr;
1923 unsigned int apic_tmict;
1924 unsigned int apic_tdcr;
1925 unsigned int apic_thmr;
1926} apic_pm_state;
1927
1928static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1929{
1930 unsigned long flags;
1931 int maxlvt;
1932
1933 if (!apic_pm_state.active)
1934 return 0;
1935
1936 maxlvt = lapic_get_maxlvt();
1937
1938 apic_pm_state.apic_id = apic_read(APIC_ID);
1939 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1940 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1941 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1942 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1943 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1944 if (maxlvt >= 4)
1945 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1946 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1947 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1948 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1949 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1950 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1951#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1952 if (maxlvt >= 5)
1953 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1954#endif
1955
1956 local_irq_save(flags);
1957 disable_local_APIC();
1958 local_irq_restore(flags);
1959 return 0;
1960}
1961
1962static int lapic_resume(struct sys_device *dev)
1963{
1964 unsigned int l, h;
1965 unsigned long flags;
1966 int maxlvt;
1967
1968 if (!apic_pm_state.active)
1969 return 0;
1970
1971 maxlvt = lapic_get_maxlvt();
1972
1973 local_irq_save(flags);
1974
1975#ifdef CONFIG_X86_X2APIC
1976 if (x2apic)
1977 enable_x2apic();
1978 else
1979#endif
1980 {
1981 /*
1982 * Make sure the APICBASE points to the right address
1983 *
1984 * FIXME! This will be wrong if we ever support suspend on
1985 * SMP! We'll need to do this as part of the CPU restore!
1986 */
1987 rdmsr(MSR_IA32_APICBASE, l, h);
1988 l &= ~MSR_IA32_APICBASE_BASE;
1989 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1990 wrmsr(MSR_IA32_APICBASE, l, h);
1991 }
1992
1993 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1994 apic_write(APIC_ID, apic_pm_state.apic_id);
1995 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1996 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1997 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1998 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1999 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2000 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2001#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2002 if (maxlvt >= 5)
2003 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2004#endif
2005 if (maxlvt >= 4)
2006 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2007 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2008 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2009 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2010 apic_write(APIC_ESR, 0);
2011 apic_read(APIC_ESR);
2012 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2013 apic_write(APIC_ESR, 0);
2014 apic_read(APIC_ESR);
2015
2016 local_irq_restore(flags);
2017
2018 return 0;
2019}
2020
2021/*
2022 * This device has no shutdown method - fully functioning local APICs
2023 * are needed on every CPU up until machine_halt/restart/poweroff.
2024 */
2025
2026static struct sysdev_class lapic_sysclass = {
2027 .name = "lapic",
2028 .resume = lapic_resume,
2029 .suspend = lapic_suspend,
2030};
2031
2032static struct sys_device device_lapic = {
2033 .id = 0,
2034 .cls = &lapic_sysclass,
2035};
2036
2037static void __cpuinit apic_pm_activate(void)
2038{
2039 apic_pm_state.active = 1;
2040}
2041
2042static int __init init_lapic_sysfs(void)
2043{
2044 int error;
2045
2046 if (!cpu_has_apic)
2047 return 0;
2048 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2049
2050 error = sysdev_class_register(&lapic_sysclass);
2051 if (!error)
2052 error = sysdev_register(&device_lapic);
2053 return error;
2054}
2055device_initcall(init_lapic_sysfs);
2056
2057#else /* CONFIG_PM */
2058
2059static void apic_pm_activate(void) { }
2060
2061#endif /* CONFIG_PM */
2062
2063#ifdef CONFIG_X86_64
2064/*
2065 * apic_is_clustered_box() -- Check if we can expect good TSC
2066 *
2067 * Thus far, the major user of this is IBM's Summit2 series:
2068 *
2069 * Clustered boxes may have unsynced TSC problems if they are
2070 * multi-chassis. Use available data to take a good guess.
2071 * If in doubt, go HPET.
2072 */
2073__cpuinit int apic_is_clustered_box(void)
2074{
2075 int i, clusters, zeros;
2076 unsigned id;
2077 u16 *bios_cpu_apicid;
2078 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2079
2080 /*
2081 * there is not this kind of box with AMD CPU yet.
2082 * Some AMD box with quadcore cpu and 8 sockets apicid
2083 * will be [4, 0x23] or [8, 0x27] could be thought to
2084 * vsmp box still need checking...
2085 */
2086 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2087 return 0;
2088
2089 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2090 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2091
2092 for (i = 0; i < nr_cpu_ids; i++) {
2093 /* are we being called early in kernel startup? */
2094 if (bios_cpu_apicid) {
2095 id = bios_cpu_apicid[i];
2096 } else if (i < nr_cpu_ids) {
2097 if (cpu_present(i))
2098 id = per_cpu(x86_bios_cpu_apicid, i);
2099 else
2100 continue;
2101 } else
2102 break;
2103
2104 if (id != BAD_APICID)
2105 __set_bit(APIC_CLUSTERID(id), clustermap);
2106 }
2107
2108 /* Problem: Partially populated chassis may not have CPUs in some of
2109 * the APIC clusters they have been allocated. Only present CPUs have
2110 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2111 * Since clusters are allocated sequentially, count zeros only if
2112 * they are bounded by ones.
2113 */
2114 clusters = 0;
2115 zeros = 0;
2116 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2117 if (test_bit(i, clustermap)) {
2118 clusters += 1 + zeros;
2119 zeros = 0;
2120 } else
2121 ++zeros;
2122 }
2123
2124 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2125 * not guaranteed to be synced between boards
2126 */
2127 if (is_vsmp_box() && clusters > 1)
2128 return 1;
2129
2130 /*
2131 * If clusters > 2, then should be multi-chassis.
2132 * May have to revisit this when multi-core + hyperthreaded CPUs come
2133 * out, but AFAIK this will work even for them.
2134 */
2135 return (clusters > 2);
2136}
2137#endif
2138
2139/*
2140 * APIC command line parameters
2141 */
2142static int __init setup_disableapic(char *arg)
2143{
2144 disable_apic = 1;
2145 setup_clear_cpu_cap(X86_FEATURE_APIC);
2146 return 0;
2147}
2148early_param("disableapic", setup_disableapic);
2149
2150/* same as disableapic, for compatibility */
2151static int __init setup_nolapic(char *arg)
2152{
2153 return setup_disableapic(arg);
2154}
2155early_param("nolapic", setup_nolapic);
2156
2157static int __init parse_lapic_timer_c2_ok(char *arg)
2158{
2159 local_apic_timer_c2_ok = 1;
2160 return 0;
2161}
2162early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2163
2164static int __init parse_disable_apic_timer(char *arg)
2165{
2166 disable_apic_timer = 1;
2167 return 0;
2168}
2169early_param("noapictimer", parse_disable_apic_timer);
2170
2171static int __init parse_nolapic_timer(char *arg)
2172{
2173 disable_apic_timer = 1;
2174 return 0;
2175}
2176early_param("nolapic_timer", parse_nolapic_timer);
2177
2178static int __init apic_set_verbosity(char *arg)
2179{
2180 if (!arg) {
2181#ifdef CONFIG_X86_64
2182 skip_ioapic_setup = 0;
2183 return 0;
2184#endif
2185 return -EINVAL;
2186 }
2187
2188 if (strcmp("debug", arg) == 0)
2189 apic_verbosity = APIC_DEBUG;
2190 else if (strcmp("verbose", arg) == 0)
2191 apic_verbosity = APIC_VERBOSE;
2192 else {
2193 pr_warning("APIC Verbosity level %s not recognised"
2194 " use apic=verbose or apic=debug\n", arg);
2195 return -EINVAL;
2196 }
2197
2198 return 0;
2199}
2200early_param("apic", apic_set_verbosity);
2201
2202static int __init lapic_insert_resource(void)
2203{
2204 if (!apic_phys)
2205 return -1;
2206
2207 /* Put local APIC into the resource map. */
2208 lapic_resource.start = apic_phys;
2209 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2210 insert_resource(&iomem_resource, &lapic_resource);
2211
2212 return 0;
2213}
2214
2215/*
2216 * need call insert after e820_reserve_resources()
2217 * that is using request_resource
2218 */
2219late_initcall(lapic_insert_resource);
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-16 17:57:23 -0500