diff options
Diffstat (limited to 'arch/x86/kernel/apic.c')
-rw-r--r-- | arch/x86/kernel/apic.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index a894eea9d51a..004aa1c31e4f 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c | |||
@@ -112,11 +112,7 @@ static __init int setup_apicpmtimer(char *s) | |||
112 | __setup("apicpmtimer", setup_apicpmtimer); | 112 | __setup("apicpmtimer", setup_apicpmtimer); |
113 | #endif | 113 | #endif |
114 | 114 | ||
115 | #ifdef CONFIG_X86_64 | 115 | #ifdef CONFIG_X86_X2APIC |
116 | #define HAVE_X2APIC | ||
117 | #endif | ||
118 | |||
119 | #ifdef HAVE_X2APIC | ||
120 | int x2apic; | 116 | int x2apic; |
121 | /* x2apic enabled before OS handover */ | 117 | /* x2apic enabled before OS handover */ |
122 | static int x2apic_preenabled; | 118 | static int x2apic_preenabled; |
@@ -269,7 +265,7 @@ static struct apic_ops xapic_ops = { | |||
269 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | 265 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; |
270 | EXPORT_SYMBOL_GPL(apic_ops); | 266 | EXPORT_SYMBOL_GPL(apic_ops); |
271 | 267 | ||
272 | #ifdef HAVE_X2APIC | 268 | #ifdef CONFIG_X86_X2APIC |
273 | static void x2apic_wait_icr_idle(void) | 269 | static void x2apic_wait_icr_idle(void) |
274 | { | 270 | { |
275 | /* no need to wait for icr idle in x2apic */ | 271 | /* no need to wait for icr idle in x2apic */ |
@@ -1320,11 +1316,14 @@ void __cpuinit end_local_APIC_setup(void) | |||
1320 | apic_pm_activate(); | 1316 | apic_pm_activate(); |
1321 | } | 1317 | } |
1322 | 1318 | ||
1323 | #ifdef HAVE_X2APIC | 1319 | #ifdef CONFIG_X86_X2APIC |
1324 | void check_x2apic(void) | 1320 | void check_x2apic(void) |
1325 | { | 1321 | { |
1326 | int msr, msr2; | 1322 | int msr, msr2; |
1327 | 1323 | ||
1324 | if (!cpu_has_x2apic) | ||
1325 | return; | ||
1326 | |||
1328 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | 1327 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1329 | 1328 | ||
1330 | if (msr & X2APIC_ENABLE) { | 1329 | if (msr & X2APIC_ENABLE) { |
@@ -1338,6 +1337,9 @@ void enable_x2apic(void) | |||
1338 | { | 1337 | { |
1339 | int msr, msr2; | 1338 | int msr, msr2; |
1340 | 1339 | ||
1340 | if (!x2apic) | ||
1341 | return; | ||
1342 | |||
1341 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | 1343 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
1342 | if (!(msr & X2APIC_ENABLE)) { | 1344 | if (!(msr & X2APIC_ENABLE)) { |
1343 | pr_info("Enabling x2apic\n"); | 1345 | pr_info("Enabling x2apic\n"); |
@@ -1439,7 +1441,7 @@ end: | |||
1439 | 1441 | ||
1440 | return; | 1442 | return; |
1441 | } | 1443 | } |
1442 | #endif /* HAVE_X2APIC */ | 1444 | #endif /* CONFIG_X86_X2APIC */ |
1443 | 1445 | ||
1444 | #ifdef CONFIG_X86_64 | 1446 | #ifdef CONFIG_X86_64 |
1445 | /* | 1447 | /* |
@@ -1570,7 +1572,7 @@ void __init early_init_lapic_mapping(void) | |||
1570 | */ | 1572 | */ |
1571 | void __init init_apic_mappings(void) | 1573 | void __init init_apic_mappings(void) |
1572 | { | 1574 | { |
1573 | #ifdef HAVE_X2APIC | 1575 | #ifdef CONFIG_X86_X2APIC |
1574 | if (x2apic) { | 1576 | if (x2apic) { |
1575 | boot_cpu_physical_apicid = read_apic_id(); | 1577 | boot_cpu_physical_apicid = read_apic_id(); |
1576 | return; | 1578 | return; |
@@ -1634,9 +1636,7 @@ int __init APIC_init_uniprocessor(void) | |||
1634 | } | 1636 | } |
1635 | #endif | 1637 | #endif |
1636 | 1638 | ||
1637 | #ifdef HAVE_X2APIC | ||
1638 | enable_IR_x2apic(); | 1639 | enable_IR_x2apic(); |
1639 | #endif | ||
1640 | #ifdef CONFIG_X86_64 | 1640 | #ifdef CONFIG_X86_64 |
1641 | default_setup_apic_routing(); | 1641 | default_setup_apic_routing(); |
1642 | #endif | 1642 | #endif |
@@ -2021,7 +2021,7 @@ static int lapic_resume(struct sys_device *dev) | |||
2021 | 2021 | ||
2022 | local_irq_save(flags); | 2022 | local_irq_save(flags); |
2023 | 2023 | ||
2024 | #ifdef HAVE_X2APIC | 2024 | #ifdef CONFIG_X86_X2APIC |
2025 | if (x2apic) | 2025 | if (x2apic) |
2026 | enable_x2apic(); | 2026 | enable_x2apic(); |
2027 | else | 2027 | else |