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1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/init.h>
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/bootmem.h>
22#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
26#include <linux/ioport.h>
27#include <linux/cpu.h>
28#include <linux/clockchips.h>
29#include <linux/acpi_pmtmr.h>
30#include <linux/module.h>
31#include <linux/dmi.h>
32#include <linux/dmar.h>
33
34#include <asm/atomic.h>
35#include <asm/smp.h>
36#include <asm/mtrr.h>
37#include <asm/mpspec.h>
38#include <asm/desc.h>
39#include <asm/arch_hooks.h>
40#include <asm/hpet.h>
41#include <asm/pgalloc.h>
42#include <asm/i8253.h>
43#include <asm/nmi.h>
44#include <asm/idle.h>
45#include <asm/proto.h>
46#include <asm/timex.h>
47#include <asm/apic.h>
48#include <asm/i8259.h>
49
50#include <mach_apic.h>
51#include <mach_apicdef.h>
52#include <mach_ipi.h>
53
54/*
55 * Sanity check
56 */
57#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58# error SPURIOUS_APIC_VECTOR definition error
59#endif
60
61#ifdef CONFIG_X86_32
62/*
63 * Knob to control our willingness to enable the local APIC.
64 *
65 * +1=force-enable
66 */
67static int force_enable_local_apic;
68/*
69 * APIC command line parameters
70 */
71static int __init parse_lapic(char *arg)
72{
73 force_enable_local_apic = 1;
74 return 0;
75}
76early_param("lapic", parse_lapic);
77/* Local APIC was disabled by the BIOS and enabled by the kernel */
78static int enabled_via_apicbase;
79
80#endif
81
82#ifdef CONFIG_X86_64
83static int apic_calibrate_pmtmr __initdata;
84static __init int setup_apicpmtimer(char *s)
85{
86 apic_calibrate_pmtmr = 1;
87 notsc_setup(NULL);
88 return 0;
89}
90__setup("apicpmtimer", setup_apicpmtimer);
91#endif
92
93#ifdef CONFIG_X86_64
94#define HAVE_X2APIC
95#endif
96
97#ifdef HAVE_X2APIC
98int x2apic;
99/* x2apic enabled before OS handover */
100int x2apic_preenabled;
101int disable_x2apic;
102static __init int setup_nox2apic(char *str)
103{
104 disable_x2apic = 1;
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
106 return 0;
107}
108early_param("nox2apic", setup_nox2apic);
109#endif
110
111unsigned long mp_lapic_addr;
112int disable_apic;
113/* Disable local APIC timer from the kernel commandline or via dmi quirk */
114static int disable_apic_timer __cpuinitdata;
115/* Local APIC timer works in C2 */
116int local_apic_timer_c2_ok;
117EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
118
119int first_system_vector = 0xfe;
120
121char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
122
123/*
124 * Debug level, exported for io_apic.c
125 */
126unsigned int apic_verbosity;
127
128int pic_mode;
129
130/* Have we found an MP table */
131int smp_found_config;
132
133static struct resource lapic_resource = {
134 .name = "Local APIC",
135 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
136};
137
138static unsigned int calibration_result;
139
140static int lapic_next_event(unsigned long delta,
141 struct clock_event_device *evt);
142static void lapic_timer_setup(enum clock_event_mode mode,
143 struct clock_event_device *evt);
144static void lapic_timer_broadcast(cpumask_t mask);
145static void apic_pm_activate(void);
146
147/*
148 * The local apic timer can be used for any function which is CPU local.
149 */
150static struct clock_event_device lapic_clockevent = {
151 .name = "lapic",
152 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
154 .shift = 32,
155 .set_mode = lapic_timer_setup,
156 .set_next_event = lapic_next_event,
157 .broadcast = lapic_timer_broadcast,
158 .rating = 100,
159 .irq = -1,
160};
161static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
162
163static unsigned long apic_phys;
164
165/*
166 * Get the LAPIC version
167 */
168static inline int lapic_get_version(void)
169{
170 return GET_APIC_VERSION(apic_read(APIC_LVR));
171}
172
173/*
174 * Check, if the APIC is integrated or a separate chip
175 */
176static inline int lapic_is_integrated(void)
177{
178#ifdef CONFIG_X86_64
179 return 1;
180#else
181 return APIC_INTEGRATED(lapic_get_version());
182#endif
183}
184
185/*
186 * Check, whether this is a modern or a first generation APIC
187 */
188static int modern_apic(void)
189{
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
192 boot_cpu_data.x86 >= 0xf)
193 return 1;
194 return lapic_get_version() >= 0x14;
195}
196
197/*
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
201 */
202void xapic_wait_icr_idle(void)
203{
204 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
205 cpu_relax();
206}
207
208u32 safe_xapic_wait_icr_idle(void)
209{
210 u32 send_status;
211 int timeout;
212
213 timeout = 0;
214 do {
215 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
216 if (!send_status)
217 break;
218 udelay(100);
219 } while (timeout++ < 1000);
220
221 return send_status;
222}
223
224void xapic_icr_write(u32 low, u32 id)
225{
226 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
227 apic_write(APIC_ICR, low);
228}
229
230u64 xapic_icr_read(void)
231{
232 u32 icr1, icr2;
233
234 icr2 = apic_read(APIC_ICR2);
235 icr1 = apic_read(APIC_ICR);
236
237 return icr1 | ((u64)icr2 << 32);
238}
239
240static struct apic_ops xapic_ops = {
241 .read = native_apic_mem_read,
242 .write = native_apic_mem_write,
243 .icr_read = xapic_icr_read,
244 .icr_write = xapic_icr_write,
245 .wait_icr_idle = xapic_wait_icr_idle,
246 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
247};
248
249struct apic_ops __read_mostly *apic_ops = &xapic_ops;
250EXPORT_SYMBOL_GPL(apic_ops);
251
252#ifdef HAVE_X2APIC
253static void x2apic_wait_icr_idle(void)
254{
255 /* no need to wait for icr idle in x2apic */
256 return;
257}
258
259static u32 safe_x2apic_wait_icr_idle(void)
260{
261 /* no need to wait for icr idle in x2apic */
262 return 0;
263}
264
265void x2apic_icr_write(u32 low, u32 id)
266{
267 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
268}
269
270u64 x2apic_icr_read(void)
271{
272 unsigned long val;
273
274 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
275 return val;
276}
277
278static struct apic_ops x2apic_ops = {
279 .read = native_apic_msr_read,
280 .write = native_apic_msr_write,
281 .icr_read = x2apic_icr_read,
282 .icr_write = x2apic_icr_write,
283 .wait_icr_idle = x2apic_wait_icr_idle,
284 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
285};
286#endif
287
288/**
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
290 */
291void __cpuinit enable_NMI_through_LVT0(void)
292{
293 unsigned int v;
294
295 /* unmask and set to NMI */
296 v = APIC_DM_NMI;
297
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v |= APIC_LVT_LEVEL_TRIGGER;
301
302 apic_write(APIC_LVT0, v);
303}
304
305#ifdef CONFIG_X86_32
306/**
307 * get_physical_broadcast - Get number of physical broadcast IDs
308 */
309int get_physical_broadcast(void)
310{
311 return modern_apic() ? 0xff : 0xf;
312}
313#endif
314
315/**
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
317 */
318int lapic_get_maxlvt(void)
319{
320 unsigned int v;
321
322 v = apic_read(APIC_LVR);
323 /*
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
326 */
327 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
328}
329
330/*
331 * Local APIC timer
332 */
333
334/* Clock divisor */
335#define APIC_DIVISOR 16
336
337/*
338 * This function sets up the local APIC timer, with a timeout of
339 * 'clocks' APIC bus clock. During calibration we actually call
340 * this function twice on the boot CPU, once with a bogus timeout
341 * value, second time for real. The other (noncalibrating) CPUs
342 * call this function only once, with the real, calibrated value.
343 *
344 * We do reads before writes even if unnecessary, to get around the
345 * P5 APIC double write bug.
346 */
347static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
348{
349 unsigned int lvtt_value, tmp_value;
350
351 lvtt_value = LOCAL_TIMER_VECTOR;
352 if (!oneshot)
353 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
354 if (!lapic_is_integrated())
355 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
356
357 if (!irqen)
358 lvtt_value |= APIC_LVT_MASKED;
359
360 apic_write(APIC_LVTT, lvtt_value);
361
362 /*
363 * Divide PICLK by 16
364 */
365 tmp_value = apic_read(APIC_TDCR);
366 apic_write(APIC_TDCR,
367 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 APIC_TDR_DIV_16);
369
370 if (!oneshot)
371 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372}
373
374/*
375 * Setup extended LVT, AMD specific (K8, family 10h)
376 *
377 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
378 * MCE interrupts are supported. Thus MCE offset must be set to 0.
379 *
380 * If mask=1, the LVT entry does not generate interrupts while mask=0
381 * enables the vector. See also the BKDGs.
382 */
383
384#define APIC_EILVT_LVTOFF_MCE 0
385#define APIC_EILVT_LVTOFF_IBS 1
386
387static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
388{
389 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
390 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
391
392 apic_write(reg, v);
393}
394
395u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
396{
397 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
398 return APIC_EILVT_LVTOFF_MCE;
399}
400
401u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
402{
403 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
404 return APIC_EILVT_LVTOFF_IBS;
405}
406EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
407
408/*
409 * Program the next event, relative to now
410 */
411static int lapic_next_event(unsigned long delta,
412 struct clock_event_device *evt)
413{
414 apic_write(APIC_TMICT, delta);
415 return 0;
416}
417
418/*
419 * Setup the lapic timer in periodic or oneshot mode
420 */
421static void lapic_timer_setup(enum clock_event_mode mode,
422 struct clock_event_device *evt)
423{
424 unsigned long flags;
425 unsigned int v;
426
427 /* Lapic used as dummy for broadcast ? */
428 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
429 return;
430
431 local_irq_save(flags);
432
433 switch (mode) {
434 case CLOCK_EVT_MODE_PERIODIC:
435 case CLOCK_EVT_MODE_ONESHOT:
436 __setup_APIC_LVTT(calibration_result,
437 mode != CLOCK_EVT_MODE_PERIODIC, 1);
438 break;
439 case CLOCK_EVT_MODE_UNUSED:
440 case CLOCK_EVT_MODE_SHUTDOWN:
441 v = apic_read(APIC_LVTT);
442 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
443 apic_write(APIC_LVTT, v);
444 break;
445 case CLOCK_EVT_MODE_RESUME:
446 /* Nothing to do here */
447 break;
448 }
449
450 local_irq_restore(flags);
451}
452
453/*
454 * Local APIC timer broadcast function
455 */
456static void lapic_timer_broadcast(cpumask_t mask)
457{
458#ifdef CONFIG_SMP
459 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
460#endif
461}
462
463/*
464 * Setup the local APIC timer for this CPU. Copy the initilized values
465 * of the boot CPU and register the clock event in the framework.
466 */
467static void __cpuinit setup_APIC_timer(void)
468{
469 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
470
471 memcpy(levt, &lapic_clockevent, sizeof(*levt));
472 levt->cpumask = cpumask_of_cpu(smp_processor_id());
473
474 clockevents_register_device(levt);
475}
476
477/*
478 * In this functions we calibrate APIC bus clocks to the external timer.
479 *
480 * We want to do the calibration only once since we want to have local timer
481 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
482 * frequency.
483 *
484 * This was previously done by reading the PIT/HPET and waiting for a wrap
485 * around to find out, that a tick has elapsed. I have a box, where the PIT
486 * readout is broken, so it never gets out of the wait loop again. This was
487 * also reported by others.
488 *
489 * Monitoring the jiffies value is inaccurate and the clockevents
490 * infrastructure allows us to do a simple substitution of the interrupt
491 * handler.
492 *
493 * The calibration routine also uses the pm_timer when possible, as the PIT
494 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
495 * back to normal later in the boot process).
496 */
497
498#define LAPIC_CAL_LOOPS (HZ/10)
499
500static __initdata int lapic_cal_loops = -1;
501static __initdata long lapic_cal_t1, lapic_cal_t2;
502static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
503static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
504static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
505
506/*
507 * Temporary interrupt handler.
508 */
509static void __init lapic_cal_handler(struct clock_event_device *dev)
510{
511 unsigned long long tsc = 0;
512 long tapic = apic_read(APIC_TMCCT);
513 unsigned long pm = acpi_pm_read_early();
514
515 if (cpu_has_tsc)
516 rdtscll(tsc);
517
518 switch (lapic_cal_loops++) {
519 case 0:
520 lapic_cal_t1 = tapic;
521 lapic_cal_tsc1 = tsc;
522 lapic_cal_pm1 = pm;
523 lapic_cal_j1 = jiffies;
524 break;
525
526 case LAPIC_CAL_LOOPS:
527 lapic_cal_t2 = tapic;
528 lapic_cal_tsc2 = tsc;
529 if (pm < lapic_cal_pm1)
530 pm += ACPI_PM_OVRRUN;
531 lapic_cal_pm2 = pm;
532 lapic_cal_j2 = jiffies;
533 break;
534 }
535}
536
537static int __init calibrate_by_pmtimer(long deltapm, long *delta)
538{
539 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
540 const long pm_thresh = pm_100ms / 100;
541 unsigned long mult;
542 u64 res;
543
544#ifndef CONFIG_X86_PM_TIMER
545 return -1;
546#endif
547
548 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
549
550 /* Check, if the PM timer is available */
551 if (!deltapm)
552 return -1;
553
554 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
555
556 if (deltapm > (pm_100ms - pm_thresh) &&
557 deltapm < (pm_100ms + pm_thresh)) {
558 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
559 } else {
560 res = (((u64)deltapm) * mult) >> 22;
561 do_div(res, 1000000);
562 printk(KERN_WARNING "APIC calibration not consistent "
563 "with PM Timer: %ldms instead of 100ms\n",
564 (long)res);
565 /* Correct the lapic counter value */
566 res = (((u64)(*delta)) * pm_100ms);
567 do_div(res, deltapm);
568 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
569 "%lu (%ld)\n", (unsigned long)res, *delta);
570 *delta = (long)res;
571 }
572
573 return 0;
574}
575
576static int __init calibrate_APIC_clock(void)
577{
578 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
579 void (*real_handler)(struct clock_event_device *dev);
580 unsigned long deltaj;
581 long delta;
582 int pm_referenced = 0;
583
584 local_irq_disable();
585
586 /* Replace the global interrupt handler */
587 real_handler = global_clock_event->event_handler;
588 global_clock_event->event_handler = lapic_cal_handler;
589
590 /*
591 * Setup the APIC counter to maximum. There is no way the lapic
592 * can underflow in the 100ms detection time frame
593 */
594 __setup_APIC_LVTT(0xffffffff, 0, 0);
595
596 /* Let the interrupts run */
597 local_irq_enable();
598
599 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
600 cpu_relax();
601
602 local_irq_disable();
603
604 /* Restore the real event handler */
605 global_clock_event->event_handler = real_handler;
606
607 /* Build delta t1-t2 as apic timer counts down */
608 delta = lapic_cal_t1 - lapic_cal_t2;
609 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
610
611 /* we trust the PM based calibration if possible */
612 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
613 &delta);
614
615 /* Calculate the scaled math multiplication factor */
616 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
617 lapic_clockevent.shift);
618 lapic_clockevent.max_delta_ns =
619 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
620 lapic_clockevent.min_delta_ns =
621 clockevent_delta2ns(0xF, &lapic_clockevent);
622
623 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
624
625 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
626 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
627 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
628 calibration_result);
629
630 if (cpu_has_tsc) {
631 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
632 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
633 "%ld.%04ld MHz.\n",
634 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
635 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
636 }
637
638 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
639 "%u.%04u MHz.\n",
640 calibration_result / (1000000 / HZ),
641 calibration_result % (1000000 / HZ));
642
643 /*
644 * Do a sanity check on the APIC calibration result
645 */
646 if (calibration_result < (1000000 / HZ)) {
647 local_irq_enable();
648 printk(KERN_WARNING
649 "APIC frequency too slow, disabling apic timer\n");
650 return -1;
651 }
652
653 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
654
655 /*
656 * PM timer calibration failed or not turned on
657 * so lets try APIC timer based calibration
658 */
659 if (!pm_referenced) {
660 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
661
662 /*
663 * Setup the apic timer manually
664 */
665 levt->event_handler = lapic_cal_handler;
666 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
667 lapic_cal_loops = -1;
668
669 /* Let the interrupts run */
670 local_irq_enable();
671
672 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
673 cpu_relax();
674
675 local_irq_disable();
676
677 /* Stop the lapic timer */
678 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
679
680 local_irq_enable();
681
682 /* Jiffies delta */
683 deltaj = lapic_cal_j2 - lapic_cal_j1;
684 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
685
686 /* Check, if the jiffies result is consistent */
687 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
688 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
689 else
690 levt->features |= CLOCK_EVT_FEAT_DUMMY;
691 } else
692 local_irq_enable();
693
694 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
695 printk(KERN_WARNING
696 "APIC timer disabled due to verification failure.\n");
697 return -1;
698 }
699
700 return 0;
701}
702
703/*
704 * Setup the boot APIC
705 *
706 * Calibrate and verify the result.
707 */
708void __init setup_boot_APIC_clock(void)
709{
710 /*
711 * The local apic timer can be disabled via the kernel
712 * commandline or from the CPU detection code. Register the lapic
713 * timer as a dummy clock event source on SMP systems, so the
714 * broadcast mechanism is used. On UP systems simply ignore it.
715 */
716 if (disable_apic_timer) {
717 printk(KERN_INFO "Disabling APIC timer\n");
718 /* No broadcast on UP ! */
719 if (num_possible_cpus() > 1) {
720 lapic_clockevent.mult = 1;
721 setup_APIC_timer();
722 }
723 return;
724 }
725
726 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
727 "calibrating APIC timer ...\n");
728
729 if (calibrate_APIC_clock()) {
730 /* No broadcast on UP ! */
731 if (num_possible_cpus() > 1)
732 setup_APIC_timer();
733 return;
734 }
735
736 /*
737 * If nmi_watchdog is set to IO_APIC, we need the
738 * PIT/HPET going. Otherwise register lapic as a dummy
739 * device.
740 */
741 if (nmi_watchdog != NMI_IO_APIC)
742 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
743 else
744 printk(KERN_WARNING "APIC timer registered as dummy,"
745 " due to nmi_watchdog=%d!\n", nmi_watchdog);
746
747 /* Setup the lapic or request the broadcast */
748 setup_APIC_timer();
749}
750
751void __cpuinit setup_secondary_APIC_clock(void)
752{
753 setup_APIC_timer();
754}
755
756/*
757 * The guts of the apic timer interrupt
758 */
759static void local_apic_timer_interrupt(void)
760{
761 int cpu = smp_processor_id();
762 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
763
764 /*
765 * Normally we should not be here till LAPIC has been initialized but
766 * in some cases like kdump, its possible that there is a pending LAPIC
767 * timer interrupt from previous kernel's context and is delivered in
768 * new kernel the moment interrupts are enabled.
769 *
770 * Interrupts are enabled early and LAPIC is setup much later, hence
771 * its possible that when we get here evt->event_handler is NULL.
772 * Check for event_handler being NULL and discard the interrupt as
773 * spurious.
774 */
775 if (!evt->event_handler) {
776 printk(KERN_WARNING
777 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
778 /* Switch it off */
779 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
780 return;
781 }
782
783 /*
784 * the NMI deadlock-detector uses this.
785 */
786#ifdef CONFIG_X86_64
787 add_pda(apic_timer_irqs, 1);
788#else
789 per_cpu(irq_stat, cpu).apic_timer_irqs++;
790#endif
791
792 evt->event_handler(evt);
793}
794
795/*
796 * Local APIC timer interrupt. This is the most natural way for doing
797 * local interrupts, but local timer interrupts can be emulated by
798 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
799 *
800 * [ if a single-CPU system runs an SMP kernel then we call the local
801 * interrupt as well. Thus we cannot inline the local irq ... ]
802 */
803void smp_apic_timer_interrupt(struct pt_regs *regs)
804{
805 struct pt_regs *old_regs = set_irq_regs(regs);
806
807 /*
808 * NOTE! We'd better ACK the irq immediately,
809 * because timer handling can be slow.
810 */
811 ack_APIC_irq();
812 /*
813 * update_process_times() expects us to have done irq_enter().
814 * Besides, if we don't timer interrupts ignore the global
815 * interrupt lock, which is the WrongThing (tm) to do.
816 */
817#ifdef CONFIG_X86_64
818 exit_idle();
819#endif
820 irq_enter();
821 local_apic_timer_interrupt();
822 irq_exit();
823
824 set_irq_regs(old_regs);
825}
826
827int setup_profiling_timer(unsigned int multiplier)
828{
829 return -EINVAL;
830}
831
832/*
833 * Local APIC start and shutdown
834 */
835
836/**
837 * clear_local_APIC - shutdown the local APIC
838 *
839 * This is called, when a CPU is disabled and before rebooting, so the state of
840 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
841 * leftovers during boot.
842 */
843void clear_local_APIC(void)
844{
845 int maxlvt;
846 u32 v;
847
848 /* APIC hasn't been mapped yet */
849 if (!apic_phys)
850 return;
851
852 maxlvt = lapic_get_maxlvt();
853 /*
854 * Masking an LVT entry can trigger a local APIC error
855 * if the vector is zero. Mask LVTERR first to prevent this.
856 */
857 if (maxlvt >= 3) {
858 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
859 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
860 }
861 /*
862 * Careful: we have to set masks only first to deassert
863 * any level-triggered sources.
864 */
865 v = apic_read(APIC_LVTT);
866 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
867 v = apic_read(APIC_LVT0);
868 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
869 v = apic_read(APIC_LVT1);
870 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
871 if (maxlvt >= 4) {
872 v = apic_read(APIC_LVTPC);
873 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
874 }
875
876 /* lets not touch this if we didn't frob it */
877#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
878 if (maxlvt >= 5) {
879 v = apic_read(APIC_LVTTHMR);
880 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
881 }
882#endif
883 /*
884 * Clean APIC state for other OSs:
885 */
886 apic_write(APIC_LVTT, APIC_LVT_MASKED);
887 apic_write(APIC_LVT0, APIC_LVT_MASKED);
888 apic_write(APIC_LVT1, APIC_LVT_MASKED);
889 if (maxlvt >= 3)
890 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
891 if (maxlvt >= 4)
892 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
893
894 /* Integrated APIC (!82489DX) ? */
895 if (lapic_is_integrated()) {
896 if (maxlvt > 3)
897 /* Clear ESR due to Pentium errata 3AP and 11AP */
898 apic_write(APIC_ESR, 0);
899 apic_read(APIC_ESR);
900 }
901}
902
903/**
904 * disable_local_APIC - clear and disable the local APIC
905 */
906void disable_local_APIC(void)
907{
908 unsigned int value;
909
910 clear_local_APIC();
911
912 /*
913 * Disable APIC (implies clearing of registers
914 * for 82489DX!).
915 */
916 value = apic_read(APIC_SPIV);
917 value &= ~APIC_SPIV_APIC_ENABLED;
918 apic_write(APIC_SPIV, value);
919
920#ifdef CONFIG_X86_32
921 /*
922 * When LAPIC was disabled by the BIOS and enabled by the kernel,
923 * restore the disabled state.
924 */
925 if (enabled_via_apicbase) {
926 unsigned int l, h;
927
928 rdmsr(MSR_IA32_APICBASE, l, h);
929 l &= ~MSR_IA32_APICBASE_ENABLE;
930 wrmsr(MSR_IA32_APICBASE, l, h);
931 }
932#endif
933}
934
935/*
936 * If Linux enabled the LAPIC against the BIOS default disable it down before
937 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
938 * not power-off. Additionally clear all LVT entries before disable_local_APIC
939 * for the case where Linux didn't enable the LAPIC.
940 */
941void lapic_shutdown(void)
942{
943 unsigned long flags;
944
945 if (!cpu_has_apic)
946 return;
947
948 local_irq_save(flags);
949
950#ifdef CONFIG_X86_32
951 if (!enabled_via_apicbase)
952 clear_local_APIC();
953 else
954#endif
955 disable_local_APIC();
956
957
958 local_irq_restore(flags);
959}
960
961/*
962 * This is to verify that we're looking at a real local APIC.
963 * Check these against your board if the CPUs aren't getting
964 * started for no apparent reason.
965 */
966int __init verify_local_APIC(void)
967{
968 unsigned int reg0, reg1;
969
970 /*
971 * The version register is read-only in a real APIC.
972 */
973 reg0 = apic_read(APIC_LVR);
974 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
975 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
976 reg1 = apic_read(APIC_LVR);
977 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
978
979 /*
980 * The two version reads above should print the same
981 * numbers. If the second one is different, then we
982 * poke at a non-APIC.
983 */
984 if (reg1 != reg0)
985 return 0;
986
987 /*
988 * Check if the version looks reasonably.
989 */
990 reg1 = GET_APIC_VERSION(reg0);
991 if (reg1 == 0x00 || reg1 == 0xff)
992 return 0;
993 reg1 = lapic_get_maxlvt();
994 if (reg1 < 0x02 || reg1 == 0xff)
995 return 0;
996
997 /*
998 * The ID register is read/write in a real APIC.
999 */
1000 reg0 = apic_read(APIC_ID);
1001 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1002 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
1003 reg1 = apic_read(APIC_ID);
1004 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1005 apic_write(APIC_ID, reg0);
1006 if (reg1 != (reg0 ^ APIC_ID_MASK))
1007 return 0;
1008
1009 /*
1010 * The next two are just to see if we have sane values.
1011 * They're only really relevant if we're in Virtual Wire
1012 * compatibility mode, but most boxes are anymore.
1013 */
1014 reg0 = apic_read(APIC_LVT0);
1015 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1016 reg1 = apic_read(APIC_LVT1);
1017 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1018
1019 return 1;
1020}
1021
1022/**
1023 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1024 */
1025void __init sync_Arb_IDs(void)
1026{
1027 /*
1028 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1029 * needed on AMD.
1030 */
1031 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1032 return;
1033
1034 /*
1035 * Wait for idle.
1036 */
1037 apic_wait_icr_idle();
1038
1039 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1040 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1041 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1042}
1043
1044/*
1045 * An initial setup of the virtual wire mode.
1046 */
1047void __init init_bsp_APIC(void)
1048{
1049 unsigned int value;
1050
1051 /*
1052 * Don't do the setup now if we have a SMP BIOS as the
1053 * through-I/O-APIC virtual wire mode might be active.
1054 */
1055 if (smp_found_config || !cpu_has_apic)
1056 return;
1057
1058 /*
1059 * Do not trust the local APIC being empty at bootup.
1060 */
1061 clear_local_APIC();
1062
1063 /*
1064 * Enable APIC.
1065 */
1066 value = apic_read(APIC_SPIV);
1067 value &= ~APIC_VECTOR_MASK;
1068 value |= APIC_SPIV_APIC_ENABLED;
1069
1070#ifdef CONFIG_X86_32
1071 /* This bit is reserved on P4/Xeon and should be cleared */
1072 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1073 (boot_cpu_data.x86 == 15))
1074 value &= ~APIC_SPIV_FOCUS_DISABLED;
1075 else
1076#endif
1077 value |= APIC_SPIV_FOCUS_DISABLED;
1078 value |= SPURIOUS_APIC_VECTOR;
1079 apic_write(APIC_SPIV, value);
1080
1081 /*
1082 * Set up the virtual wire mode.
1083 */
1084 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1085 value = APIC_DM_NMI;
1086 if (!lapic_is_integrated()) /* 82489DX */
1087 value |= APIC_LVT_LEVEL_TRIGGER;
1088 apic_write(APIC_LVT1, value);
1089}
1090
1091static void __cpuinit lapic_setup_esr(void)
1092{
1093 unsigned int oldvalue, value, maxlvt;
1094
1095 if (!lapic_is_integrated()) {
1096 printk(KERN_INFO "No ESR for 82489DX.\n");
1097 return;
1098 }
1099
1100 if (esr_disable) {
1101 /*
1102 * Something untraceable is creating bad interrupts on
1103 * secondary quads ... for the moment, just leave the
1104 * ESR disabled - we can't do anything useful with the
1105 * errors anyway - mbligh
1106 */
1107 printk(KERN_INFO "Leaving ESR disabled.\n");
1108 return;
1109 }
1110
1111 maxlvt = lapic_get_maxlvt();
1112 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1113 apic_write(APIC_ESR, 0);
1114 oldvalue = apic_read(APIC_ESR);
1115
1116 /* enables sending errors */
1117 value = ERROR_APIC_VECTOR;
1118 apic_write(APIC_LVTERR, value);
1119
1120 /*
1121 * spec says clear errors after enabling vector.
1122 */
1123 if (maxlvt > 3)
1124 apic_write(APIC_ESR, 0);
1125 value = apic_read(APIC_ESR);
1126 if (value != oldvalue)
1127 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1128 "vector: 0x%08x after: 0x%08x\n",
1129 oldvalue, value);
1130}
1131
1132
1133/**
1134 * setup_local_APIC - setup the local APIC
1135 */
1136void __cpuinit setup_local_APIC(void)
1137{
1138 unsigned int value;
1139 int i, j;
1140
1141#ifdef CONFIG_X86_32
1142 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1143 if (lapic_is_integrated() && esr_disable) {
1144 apic_write(APIC_ESR, 0);
1145 apic_write(APIC_ESR, 0);
1146 apic_write(APIC_ESR, 0);
1147 apic_write(APIC_ESR, 0);
1148 }
1149#endif
1150
1151 preempt_disable();
1152
1153 /*
1154 * Double-check whether this APIC is really registered.
1155 * This is meaningless in clustered apic mode, so we skip it.
1156 */
1157 if (!apic_id_registered())
1158 BUG();
1159
1160 /*
1161 * Intel recommends to set DFR, LDR and TPR before enabling
1162 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1163 * document number 292116). So here it goes...
1164 */
1165 init_apic_ldr();
1166
1167 /*
1168 * Set Task Priority to 'accept all'. We never change this
1169 * later on.
1170 */
1171 value = apic_read(APIC_TASKPRI);
1172 value &= ~APIC_TPRI_MASK;
1173 apic_write(APIC_TASKPRI, value);
1174
1175 /*
1176 * After a crash, we no longer service the interrupts and a pending
1177 * interrupt from previous kernel might still have ISR bit set.
1178 *
1179 * Most probably by now CPU has serviced that pending interrupt and
1180 * it might not have done the ack_APIC_irq() because it thought,
1181 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1182 * does not clear the ISR bit and cpu thinks it has already serivced
1183 * the interrupt. Hence a vector might get locked. It was noticed
1184 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1185 */
1186 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1187 value = apic_read(APIC_ISR + i*0x10);
1188 for (j = 31; j >= 0; j--) {
1189 if (value & (1<<j))
1190 ack_APIC_irq();
1191 }
1192 }
1193
1194 /*
1195 * Now that we are all set up, enable the APIC
1196 */
1197 value = apic_read(APIC_SPIV);
1198 value &= ~APIC_VECTOR_MASK;
1199 /*
1200 * Enable APIC
1201 */
1202 value |= APIC_SPIV_APIC_ENABLED;
1203
1204#ifdef CONFIG_X86_32
1205 /*
1206 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1207 * certain networking cards. If high frequency interrupts are
1208 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1209 * entry is masked/unmasked at a high rate as well then sooner or
1210 * later IOAPIC line gets 'stuck', no more interrupts are received
1211 * from the device. If focus CPU is disabled then the hang goes
1212 * away, oh well :-(
1213 *
1214 * [ This bug can be reproduced easily with a level-triggered
1215 * PCI Ne2000 networking cards and PII/PIII processors, dual
1216 * BX chipset. ]
1217 */
1218 /*
1219 * Actually disabling the focus CPU check just makes the hang less
1220 * frequent as it makes the interrupt distributon model be more
1221 * like LRU than MRU (the short-term load is more even across CPUs).
1222 * See also the comment in end_level_ioapic_irq(). --macro
1223 */
1224
1225 /*
1226 * - enable focus processor (bit==0)
1227 * - 64bit mode always use processor focus
1228 * so no need to set it
1229 */
1230 value &= ~APIC_SPIV_FOCUS_DISABLED;
1231#endif
1232
1233 /*
1234 * Set spurious IRQ vector
1235 */
1236 value |= SPURIOUS_APIC_VECTOR;
1237 apic_write(APIC_SPIV, value);
1238
1239 /*
1240 * Set up LVT0, LVT1:
1241 *
1242 * set up through-local-APIC on the BP's LINT0. This is not
1243 * strictly necessary in pure symmetric-IO mode, but sometimes
1244 * we delegate interrupts to the 8259A.
1245 */
1246 /*
1247 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1248 */
1249 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1250 if (!smp_processor_id() && (pic_mode || !value)) {
1251 value = APIC_DM_EXTINT;
1252 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1253 smp_processor_id());
1254 } else {
1255 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1256 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1257 smp_processor_id());
1258 }
1259 apic_write(APIC_LVT0, value);
1260
1261 /*
1262 * only the BP should see the LINT1 NMI signal, obviously.
1263 */
1264 if (!smp_processor_id())
1265 value = APIC_DM_NMI;
1266 else
1267 value = APIC_DM_NMI | APIC_LVT_MASKED;
1268 if (!lapic_is_integrated()) /* 82489DX */
1269 value |= APIC_LVT_LEVEL_TRIGGER;
1270 apic_write(APIC_LVT1, value);
1271
1272 preempt_enable();
1273}
1274
1275void __cpuinit end_local_APIC_setup(void)
1276{
1277 lapic_setup_esr();
1278
1279#ifdef CONFIG_X86_32
1280 {
1281 unsigned int value;
1282 /* Disable the local apic timer */
1283 value = apic_read(APIC_LVTT);
1284 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1285 apic_write(APIC_LVTT, value);
1286 }
1287#endif
1288
1289 setup_apic_nmi_watchdog(NULL);
1290 apic_pm_activate();
1291}
1292
1293#ifdef HAVE_X2APIC
1294void check_x2apic(void)
1295{
1296 int msr, msr2;
1297
1298 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1299
1300 if (msr & X2APIC_ENABLE) {
1301 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1302 x2apic_preenabled = x2apic = 1;
1303 apic_ops = &x2apic_ops;
1304 }
1305}
1306
1307void enable_x2apic(void)
1308{
1309 int msr, msr2;
1310
1311 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1312 if (!(msr & X2APIC_ENABLE)) {
1313 printk("Enabling x2apic\n");
1314 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1315 }
1316}
1317
1318void enable_IR_x2apic(void)
1319{
1320#ifdef CONFIG_INTR_REMAP
1321 int ret;
1322 unsigned long flags;
1323
1324 if (!cpu_has_x2apic)
1325 return;
1326
1327 if (!x2apic_preenabled && disable_x2apic) {
1328 printk(KERN_INFO
1329 "Skipped enabling x2apic and Interrupt-remapping "
1330 "because of nox2apic\n");
1331 return;
1332 }
1333
1334 if (x2apic_preenabled && disable_x2apic)
1335 panic("Bios already enabled x2apic, can't enforce nox2apic");
1336
1337 if (!x2apic_preenabled && skip_ioapic_setup) {
1338 printk(KERN_INFO
1339 "Skipped enabling x2apic and Interrupt-remapping "
1340 "because of skipping io-apic setup\n");
1341 return;
1342 }
1343
1344 ret = dmar_table_init();
1345 if (ret) {
1346 printk(KERN_INFO
1347 "dmar_table_init() failed with %d:\n", ret);
1348
1349 if (x2apic_preenabled)
1350 panic("x2apic enabled by bios. But IR enabling failed");
1351 else
1352 printk(KERN_INFO
1353 "Not enabling x2apic,Intr-remapping\n");
1354 return;
1355 }
1356
1357 local_irq_save(flags);
1358 mask_8259A();
1359
1360 ret = save_mask_IO_APIC_setup();
1361 if (ret) {
1362 printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret);
1363 goto end;
1364 }
1365
1366 ret = enable_intr_remapping(1);
1367
1368 if (ret && x2apic_preenabled) {
1369 local_irq_restore(flags);
1370 panic("x2apic enabled by bios. But IR enabling failed");
1371 }
1372
1373 if (ret)
1374 goto end_restore;
1375
1376 if (!x2apic) {
1377 x2apic = 1;
1378 apic_ops = &x2apic_ops;
1379 enable_x2apic();
1380 }
1381
1382end_restore:
1383 if (ret)
1384 /*
1385 * IR enabling failed
1386 */
1387 restore_IO_APIC_setup();
1388 else
1389 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1390
1391end:
1392 unmask_8259A();
1393 local_irq_restore(flags);
1394
1395 if (!ret) {
1396 if (!x2apic_preenabled)
1397 printk(KERN_INFO
1398 "Enabled x2apic and interrupt-remapping\n");
1399 else
1400 printk(KERN_INFO
1401 "Enabled Interrupt-remapping\n");
1402 } else
1403 printk(KERN_ERR
1404 "Failed to enable Interrupt-remapping and x2apic\n");
1405#else
1406 if (!cpu_has_x2apic)
1407 return;
1408
1409 if (x2apic_preenabled)
1410 panic("x2apic enabled prior OS handover,"
1411 " enable CONFIG_INTR_REMAP");
1412
1413 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1414 " and x2apic\n");
1415#endif
1416
1417 return;
1418}
1419#endif /* HAVE_X2APIC */
1420
1421#ifdef CONFIG_X86_64
1422/*
1423 * Detect and enable local APICs on non-SMP boards.
1424 * Original code written by Keir Fraser.
1425 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1426 * not correctly set up (usually the APIC timer won't work etc.)
1427 */
1428static int __init detect_init_APIC(void)
1429{
1430 if (!cpu_has_apic) {
1431 printk(KERN_INFO "No local APIC present\n");
1432 return -1;
1433 }
1434
1435 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1436 boot_cpu_physical_apicid = 0;
1437 return 0;
1438}
1439#else
1440/*
1441 * Detect and initialize APIC
1442 */
1443static int __init detect_init_APIC(void)
1444{
1445 u32 h, l, features;
1446
1447 /* Disabled by kernel option? */
1448 if (disable_apic)
1449 return -1;
1450
1451 switch (boot_cpu_data.x86_vendor) {
1452 case X86_VENDOR_AMD:
1453 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1454 (boot_cpu_data.x86 == 15))
1455 break;
1456 goto no_apic;
1457 case X86_VENDOR_INTEL:
1458 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1459 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1460 break;
1461 goto no_apic;
1462 default:
1463 goto no_apic;
1464 }
1465
1466 if (!cpu_has_apic) {
1467 /*
1468 * Over-ride BIOS and try to enable the local APIC only if
1469 * "lapic" specified.
1470 */
1471 if (!force_enable_local_apic) {
1472 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1473 "you can enable it with \"lapic\"\n");
1474 return -1;
1475 }
1476 /*
1477 * Some BIOSes disable the local APIC in the APIC_BASE
1478 * MSR. This can only be done in software for Intel P6 or later
1479 * and AMD K7 (Model > 1) or later.
1480 */
1481 rdmsr(MSR_IA32_APICBASE, l, h);
1482 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1483 printk(KERN_INFO
1484 "Local APIC disabled by BIOS -- reenabling.\n");
1485 l &= ~MSR_IA32_APICBASE_BASE;
1486 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1487 wrmsr(MSR_IA32_APICBASE, l, h);
1488 enabled_via_apicbase = 1;
1489 }
1490 }
1491 /*
1492 * The APIC feature bit should now be enabled
1493 * in `cpuid'
1494 */
1495 features = cpuid_edx(1);
1496 if (!(features & (1 << X86_FEATURE_APIC))) {
1497 printk(KERN_WARNING "Could not enable APIC!\n");
1498 return -1;
1499 }
1500 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1501 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1502
1503 /* The BIOS may have set up the APIC at some other address */
1504 rdmsr(MSR_IA32_APICBASE, l, h);
1505 if (l & MSR_IA32_APICBASE_ENABLE)
1506 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1507
1508 printk(KERN_INFO "Found and enabled local APIC!\n");
1509
1510 apic_pm_activate();
1511
1512 return 0;
1513
1514no_apic:
1515 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1516 return -1;
1517}
1518#endif
1519
1520#ifdef CONFIG_X86_64
1521void __init early_init_lapic_mapping(void)
1522{
1523 unsigned long phys_addr;
1524
1525 /*
1526 * If no local APIC can be found then go out
1527 * : it means there is no mpatable and MADT
1528 */
1529 if (!smp_found_config)
1530 return;
1531
1532 phys_addr = mp_lapic_addr;
1533
1534 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1535 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1536 APIC_BASE, phys_addr);
1537
1538 /*
1539 * Fetch the APIC ID of the BSP in case we have a
1540 * default configuration (or the MP table is broken).
1541 */
1542 boot_cpu_physical_apicid = read_apic_id();
1543}
1544#endif
1545
1546/**
1547 * init_apic_mappings - initialize APIC mappings
1548 */
1549void __init init_apic_mappings(void)
1550{
1551#ifdef HAVE_X2APIC
1552 if (x2apic) {
1553 boot_cpu_physical_apicid = read_apic_id();
1554 return;
1555 }
1556#endif
1557
1558 /*
1559 * If no local APIC can be found then set up a fake all
1560 * zeroes page to simulate the local APIC and another
1561 * one for the IO-APIC.
1562 */
1563 if (!smp_found_config && detect_init_APIC()) {
1564 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1565 apic_phys = __pa(apic_phys);
1566 } else
1567 apic_phys = mp_lapic_addr;
1568
1569 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1570 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1571 APIC_BASE, apic_phys);
1572
1573 /*
1574 * Fetch the APIC ID of the BSP in case we have a
1575 * default configuration (or the MP table is broken).
1576 */
1577 if (boot_cpu_physical_apicid == -1U)
1578 boot_cpu_physical_apicid = read_apic_id();
1579}
1580
1581/*
1582 * This initializes the IO-APIC and APIC hardware if this is
1583 * a UP kernel.
1584 */
1585int apic_version[MAX_APICS];
1586
1587int __init APIC_init_uniprocessor(void)
1588{
1589#ifdef CONFIG_X86_64
1590 if (disable_apic) {
1591 printk(KERN_INFO "Apic disabled\n");
1592 return -1;
1593 }
1594 if (!cpu_has_apic) {
1595 disable_apic = 1;
1596 printk(KERN_INFO "Apic disabled by BIOS\n");
1597 return -1;
1598 }
1599#else
1600 if (!smp_found_config && !cpu_has_apic)
1601 return -1;
1602
1603 /*
1604 * Complain if the BIOS pretends there is one.
1605 */
1606 if (!cpu_has_apic &&
1607 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1608 printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n",
1609 boot_cpu_physical_apicid);
1610 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1611 return -1;
1612 }
1613#endif
1614
1615#ifdef HAVE_X2APIC
1616 enable_IR_x2apic();
1617#endif
1618#ifdef CONFIG_X86_64
1619 setup_apic_routing();
1620#endif
1621
1622 verify_local_APIC();
1623 connect_bsp_APIC();
1624
1625#ifdef CONFIG_X86_64
1626 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1627#else
1628 /*
1629 * Hack: In case of kdump, after a crash, kernel might be booting
1630 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1631 * might be zero if read from MP tables. Get it from LAPIC.
1632 */
1633# ifdef CONFIG_CRASH_DUMP
1634 boot_cpu_physical_apicid = read_apic_id();
1635# endif
1636#endif
1637 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1638 setup_local_APIC();
1639
1640#ifdef CONFIG_X86_64
1641 /*
1642 * Now enable IO-APICs, actually call clear_IO_APIC
1643 * We need clear_IO_APIC before enabling vector on BP
1644 */
1645 if (!skip_ioapic_setup && nr_ioapics)
1646 enable_IO_APIC();
1647#endif
1648
1649#ifdef CONFIG_X86_IO_APIC
1650 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1651#endif
1652 localise_nmi_watchdog();
1653 end_local_APIC_setup();
1654
1655#ifdef CONFIG_X86_IO_APIC
1656 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1657 setup_IO_APIC();
1658# ifdef CONFIG_X86_64
1659 else
1660 nr_ioapics = 0;
1661# endif
1662#endif
1663
1664#ifdef CONFIG_X86_64
1665 setup_boot_APIC_clock();
1666 check_nmi_watchdog();
1667#else
1668 setup_boot_clock();
1669#endif
1670
1671 return 0;
1672}
1673
1674/*
1675 * Local APIC interrupts
1676 */
1677
1678/*
1679 * This interrupt should _never_ happen with our APIC/SMP architecture
1680 */
1681void smp_spurious_interrupt(struct pt_regs *regs)
1682{
1683 u32 v;
1684
1685#ifdef CONFIG_X86_64
1686 exit_idle();
1687#endif
1688 irq_enter();
1689 /*
1690 * Check if this really is a spurious interrupt and ACK it
1691 * if it is a vectored one. Just in case...
1692 * Spurious interrupts should not be ACKed.
1693 */
1694 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1695 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1696 ack_APIC_irq();
1697
1698#ifdef CONFIG_X86_64
1699 add_pda(irq_spurious_count, 1);
1700#else
1701 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1702 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1703 "should never happen.\n", smp_processor_id());
1704 __get_cpu_var(irq_stat).irq_spurious_count++;
1705#endif
1706 irq_exit();
1707}
1708
1709/*
1710 * This interrupt should never happen with our APIC/SMP architecture
1711 */
1712void smp_error_interrupt(struct pt_regs *regs)
1713{
1714 u32 v, v1;
1715
1716#ifdef CONFIG_X86_64
1717 exit_idle();
1718#endif
1719 irq_enter();
1720 /* First tickle the hardware, only then report what went on. -- REW */
1721 v = apic_read(APIC_ESR);
1722 apic_write(APIC_ESR, 0);
1723 v1 = apic_read(APIC_ESR);
1724 ack_APIC_irq();
1725 atomic_inc(&irq_err_count);
1726
1727 /* Here is what the APIC error bits mean:
1728 0: Send CS error
1729 1: Receive CS error
1730 2: Send accept error
1731 3: Receive accept error
1732 4: Reserved
1733 5: Send illegal vector
1734 6: Received illegal vector
1735 7: Illegal register address
1736 */
1737 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1738 smp_processor_id(), v , v1);
1739 irq_exit();
1740}
1741
1742/**
1743 * connect_bsp_APIC - attach the APIC to the interrupt system
1744 */
1745void __init connect_bsp_APIC(void)
1746{
1747#ifdef CONFIG_X86_32
1748 if (pic_mode) {
1749 /*
1750 * Do not trust the local APIC being empty at bootup.
1751 */
1752 clear_local_APIC();
1753 /*
1754 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1755 * local APIC to INT and NMI lines.
1756 */
1757 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1758 "enabling APIC mode.\n");
1759 outb(0x70, 0x22);
1760 outb(0x01, 0x23);
1761 }
1762#endif
1763 enable_apic_mode();
1764}
1765
1766/**
1767 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1768 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1769 *
1770 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1771 * APIC is disabled.
1772 */
1773void disconnect_bsp_APIC(int virt_wire_setup)
1774{
1775 unsigned int value;
1776
1777#ifdef CONFIG_X86_32
1778 if (pic_mode) {
1779 /*
1780 * Put the board back into PIC mode (has an effect only on
1781 * certain older boards). Note that APIC interrupts, including
1782 * IPIs, won't work beyond this point! The only exception are
1783 * INIT IPIs.
1784 */
1785 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1786 "entering PIC mode.\n");
1787 outb(0x70, 0x22);
1788 outb(0x00, 0x23);
1789 return;
1790 }
1791#endif
1792
1793 /* Go back to Virtual Wire compatibility mode */
1794
1795 /* For the spurious interrupt use vector F, and enable it */
1796 value = apic_read(APIC_SPIV);
1797 value &= ~APIC_VECTOR_MASK;
1798 value |= APIC_SPIV_APIC_ENABLED;
1799 value |= 0xf;
1800 apic_write(APIC_SPIV, value);
1801
1802 if (!virt_wire_setup) {
1803 /*
1804 * For LVT0 make it edge triggered, active high,
1805 * external and enabled
1806 */
1807 value = apic_read(APIC_LVT0);
1808 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1809 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1810 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1811 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1812 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1813 apic_write(APIC_LVT0, value);
1814 } else {
1815 /* Disable LVT0 */
1816 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1817 }
1818
1819 /*
1820 * For LVT1 make it edge triggered, active high,
1821 * nmi and enabled
1822 */
1823 value = apic_read(APIC_LVT1);
1824 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1825 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1826 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1827 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1828 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1829 apic_write(APIC_LVT1, value);
1830}
1831
1832void __cpuinit generic_processor_info(int apicid, int version)
1833{
1834 int cpu;
1835 cpumask_t tmp_map;
1836
1837 /*
1838 * Validate version
1839 */
1840 if (version == 0x0) {
1841 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1842 "fixing up to 0x10. (tell your hw vendor)\n",
1843 version);
1844 version = 0x10;
1845 }
1846 apic_version[apicid] = version;
1847
1848 if (num_processors >= NR_CPUS) {
1849 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1850 " Processor ignored.\n", NR_CPUS);
1851 return;
1852 }
1853
1854 num_processors++;
1855 cpus_complement(tmp_map, cpu_present_map);
1856 cpu = first_cpu(tmp_map);
1857
1858 physid_set(apicid, phys_cpu_present_map);
1859 if (apicid == boot_cpu_physical_apicid) {
1860 /*
1861 * x86_bios_cpu_apicid is required to have processors listed
1862 * in same order as logical cpu numbers. Hence the first
1863 * entry is BSP, and so on.
1864 */
1865 cpu = 0;
1866 }
1867 if (apicid > max_physical_apicid)
1868 max_physical_apicid = apicid;
1869
1870#ifdef CONFIG_X86_32
1871 /*
1872 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1873 * but we need to work other dependencies like SMP_SUSPEND etc
1874 * before this can be done without some confusion.
1875 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1876 * - Ashok Raj <ashok.raj@intel.com>
1877 */
1878 if (max_physical_apicid >= 8) {
1879 switch (boot_cpu_data.x86_vendor) {
1880 case X86_VENDOR_INTEL:
1881 if (!APIC_XAPIC(version)) {
1882 def_to_bigsmp = 0;
1883 break;
1884 }
1885 /* If P4 and above fall through */
1886 case X86_VENDOR_AMD:
1887 def_to_bigsmp = 1;
1888 }
1889 }
1890#endif
1891
1892#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1893 /* are we being called early in kernel startup? */
1894 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1895 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1896 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1897
1898 cpu_to_apicid[cpu] = apicid;
1899 bios_cpu_apicid[cpu] = apicid;
1900 } else {
1901 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1902 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1903 }
1904#endif
1905
1906 cpu_set(cpu, cpu_possible_map);
1907 cpu_set(cpu, cpu_present_map);
1908}
1909
1910#ifdef CONFIG_X86_64
1911int hard_smp_processor_id(void)
1912{
1913 return read_apic_id();
1914}
1915#endif
1916
1917/*
1918 * Power management
1919 */
1920#ifdef CONFIG_PM
1921
1922static struct {
1923 /*
1924 * 'active' is true if the local APIC was enabled by us and
1925 * not the BIOS; this signifies that we are also responsible
1926 * for disabling it before entering apm/acpi suspend
1927 */
1928 int active;
1929 /* r/w apic fields */
1930 unsigned int apic_id;
1931 unsigned int apic_taskpri;
1932 unsigned int apic_ldr;
1933 unsigned int apic_dfr;
1934 unsigned int apic_spiv;
1935 unsigned int apic_lvtt;
1936 unsigned int apic_lvtpc;
1937 unsigned int apic_lvt0;
1938 unsigned int apic_lvt1;
1939 unsigned int apic_lvterr;
1940 unsigned int apic_tmict;
1941 unsigned int apic_tdcr;
1942 unsigned int apic_thmr;
1943} apic_pm_state;
1944
1945static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1946{
1947 unsigned long flags;
1948 int maxlvt;
1949
1950 if (!apic_pm_state.active)
1951 return 0;
1952
1953 maxlvt = lapic_get_maxlvt();
1954
1955 apic_pm_state.apic_id = apic_read(APIC_ID);
1956 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1957 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1958 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1959 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1960 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1961 if (maxlvt >= 4)
1962 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1963 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1964 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1965 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1966 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1967 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1968#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1969 if (maxlvt >= 5)
1970 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1971#endif
1972
1973 local_irq_save(flags);
1974 disable_local_APIC();
1975 local_irq_restore(flags);
1976 return 0;
1977}
1978
1979static int lapic_resume(struct sys_device *dev)
1980{
1981 unsigned int l, h;
1982 unsigned long flags;
1983 int maxlvt;
1984
1985 if (!apic_pm_state.active)
1986 return 0;
1987
1988 maxlvt = lapic_get_maxlvt();
1989
1990 local_irq_save(flags);
1991
1992#ifdef HAVE_X2APIC
1993 if (x2apic)
1994 enable_x2apic();
1995 else
1996#endif
1997 {
1998 /*
1999 * Make sure the APICBASE points to the right address
2000 *
2001 * FIXME! This will be wrong if we ever support suspend on
2002 * SMP! We'll need to do this as part of the CPU restore!
2003 */
2004 rdmsr(MSR_IA32_APICBASE, l, h);
2005 l &= ~MSR_IA32_APICBASE_BASE;
2006 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2007 wrmsr(MSR_IA32_APICBASE, l, h);
2008 }
2009
2010 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2011 apic_write(APIC_ID, apic_pm_state.apic_id);
2012 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2013 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2014 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2015 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2016 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2017 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2018#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2019 if (maxlvt >= 5)
2020 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2021#endif
2022 if (maxlvt >= 4)
2023 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2024 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2025 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2026 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2027 apic_write(APIC_ESR, 0);
2028 apic_read(APIC_ESR);
2029 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2030 apic_write(APIC_ESR, 0);
2031 apic_read(APIC_ESR);
2032
2033 local_irq_restore(flags);
2034
2035 return 0;
2036}
2037
2038/*
2039 * This device has no shutdown method - fully functioning local APICs
2040 * are needed on every CPU up until machine_halt/restart/poweroff.
2041 */
2042
2043static struct sysdev_class lapic_sysclass = {
2044 .name = "lapic",
2045 .resume = lapic_resume,
2046 .suspend = lapic_suspend,
2047};
2048
2049static struct sys_device device_lapic = {
2050 .id = 0,
2051 .cls = &lapic_sysclass,
2052};
2053
2054static void __cpuinit apic_pm_activate(void)
2055{
2056 apic_pm_state.active = 1;
2057}
2058
2059static int __init init_lapic_sysfs(void)
2060{
2061 int error;
2062
2063 if (!cpu_has_apic)
2064 return 0;
2065 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2066
2067 error = sysdev_class_register(&lapic_sysclass);
2068 if (!error)
2069 error = sysdev_register(&device_lapic);
2070 return error;
2071}
2072device_initcall(init_lapic_sysfs);
2073
2074#else /* CONFIG_PM */
2075
2076static void apic_pm_activate(void) { }
2077
2078#endif /* CONFIG_PM */
2079
2080#ifdef CONFIG_X86_64
2081/*
2082 * apic_is_clustered_box() -- Check if we can expect good TSC
2083 *
2084 * Thus far, the major user of this is IBM's Summit2 series:
2085 *
2086 * Clustered boxes may have unsynced TSC problems if they are
2087 * multi-chassis. Use available data to take a good guess.
2088 * If in doubt, go HPET.
2089 */
2090__cpuinit int apic_is_clustered_box(void)
2091{
2092 int i, clusters, zeros;
2093 unsigned id;
2094 u16 *bios_cpu_apicid;
2095 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2096
2097 /*
2098 * there is not this kind of box with AMD CPU yet.
2099 * Some AMD box with quadcore cpu and 8 sockets apicid
2100 * will be [4, 0x23] or [8, 0x27] could be thought to
2101 * vsmp box still need checking...
2102 */
2103 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2104 return 0;
2105
2106 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2107 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2108
2109 for (i = 0; i < NR_CPUS; i++) {
2110 /* are we being called early in kernel startup? */
2111 if (bios_cpu_apicid) {
2112 id = bios_cpu_apicid[i];
2113 }
2114 else if (i < nr_cpu_ids) {
2115 if (cpu_present(i))
2116 id = per_cpu(x86_bios_cpu_apicid, i);
2117 else
2118 continue;
2119 }
2120 else
2121 break;
2122
2123 if (id != BAD_APICID)
2124 __set_bit(APIC_CLUSTERID(id), clustermap);
2125 }
2126
2127 /* Problem: Partially populated chassis may not have CPUs in some of
2128 * the APIC clusters they have been allocated. Only present CPUs have
2129 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2130 * Since clusters are allocated sequentially, count zeros only if
2131 * they are bounded by ones.
2132 */
2133 clusters = 0;
2134 zeros = 0;
2135 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2136 if (test_bit(i, clustermap)) {
2137 clusters += 1 + zeros;
2138 zeros = 0;
2139 } else
2140 ++zeros;
2141 }
2142
2143 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2144 * not guaranteed to be synced between boards
2145 */
2146 if (is_vsmp_box() && clusters > 1)
2147 return 1;
2148
2149 /*
2150 * If clusters > 2, then should be multi-chassis.
2151 * May have to revisit this when multi-core + hyperthreaded CPUs come
2152 * out, but AFAIK this will work even for them.
2153 */
2154 return (clusters > 2);
2155}
2156#endif
2157
2158/*
2159 * APIC command line parameters
2160 */
2161static int __init setup_disableapic(char *arg)
2162{
2163 disable_apic = 1;
2164 setup_clear_cpu_cap(X86_FEATURE_APIC);
2165 return 0;
2166}
2167early_param("disableapic", setup_disableapic);
2168
2169/* same as disableapic, for compatibility */
2170static int __init setup_nolapic(char *arg)
2171{
2172 return setup_disableapic(arg);
2173}
2174early_param("nolapic", setup_nolapic);
2175
2176static int __init parse_lapic_timer_c2_ok(char *arg)
2177{
2178 local_apic_timer_c2_ok = 1;
2179 return 0;
2180}
2181early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2182
2183static int __init parse_disable_apic_timer(char *arg)
2184{
2185 disable_apic_timer = 1;
2186 return 0;
2187}
2188early_param("noapictimer", parse_disable_apic_timer);
2189
2190static int __init parse_nolapic_timer(char *arg)
2191{
2192 disable_apic_timer = 1;
2193 return 0;
2194}
2195early_param("nolapic_timer", parse_nolapic_timer);
2196
2197static int __init apic_set_verbosity(char *arg)
2198{
2199 if (!arg) {
2200#ifdef CONFIG_X86_64
2201 skip_ioapic_setup = 0;
2202 return 0;
2203#endif
2204 return -EINVAL;
2205 }
2206
2207 if (strcmp("debug", arg) == 0)
2208 apic_verbosity = APIC_DEBUG;
2209 else if (strcmp("verbose", arg) == 0)
2210 apic_verbosity = APIC_VERBOSE;
2211 else {
2212 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
2213 " use apic=verbose or apic=debug\n", arg);
2214 return -EINVAL;
2215 }
2216
2217 return 0;
2218}
2219early_param("apic", apic_set_verbosity);
2220
2221static int __init lapic_insert_resource(void)
2222{
2223 if (!apic_phys)
2224 return -1;
2225
2226 /* Put local APIC into the resource map. */
2227 lapic_resource.start = apic_phys;
2228 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2229 insert_resource(&iomem_resource, &lapic_resource);
2230
2231 return 0;
2232}
2233
2234/*
2235 * need call insert after e820_reserve_resources()
2236 * that is using request_resource
2237 */
2238late_initcall(lapic_insert_resource);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 17:33:06 -0500