1 files changed, 196 insertions, 111 deletions

diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index 479926d9e004..e819362c7068 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -35,6 +35,18 @@ int fallback_aper_force __initdata;
 
 int fix_aperture __initdata = 1;
 
+struct bus_dev_range {
+        int bus;
+        int dev_base;
+        int dev_limit;
+};
+
+static struct bus_dev_range bus_dev_ranges[] __initdata = {
+        { 0x00, 0x18, 0x20},
+        { 0xff, 0x00, 0x20},
+        { 0xfe, 0x00, 0x20}
+};
+
 static struct resource gart_resource = {
         .name   = "GART",
         .flags  = IORESOURCE_MEM,
@@ -55,8 +67,9 @@ static u32 __init allocate_aperture(void)
         u32 aper_size;
         void *p;
 
-        if (fallback_aper_order > 7)
-                fallback_aper_order = 7;
+        /* aper_size should <= 1G */
+        if (fallback_aper_order > 5)
+                fallback_aper_order = 5;
         aper_size = (32 * 1024 * 1024) << fallback_aper_order;
 
         /*
@@ -65,7 +78,20 @@ static u32 __init allocate_aperture(void)
          * memory. Unfortunately we cannot move it up because that would
          * make the IOMMU useless.
          */
-        p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
+        /*
+         * using 512M as goal, in case kexec will load kernel_big
+         * that will do the on position decompress, and  could overlap with
+         * that positon with gart that is used.
+         * sequende:
+         * kernel_small
+         * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
+         * ==> kernel_small(gart area become e820_reserved)
+         * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
+         * ==> kerne_big (uncompressed size will be big than 64M or 128M)
+         * so don't use 512M below as gart iommu, leave the space for kernel
+         * code for safe
+         */
+        p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
         if (!p || __pa(p)+aper_size > 0xffffffff) {
                 printk(KERN_ERR
                         "Cannot allocate aperture memory hole (%p,%uK)\n",
@@ -83,69 +109,53 @@ static u32 __init allocate_aperture(void)
         return (u32)__pa(p);
 }
 
-static int __init aperture_valid(u64 aper_base, u32 aper_size)
-{
-        if (!aper_base)
-                return 0;
-
-        if (aper_base + aper_size > 0x100000000UL) {
-                printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
-                return 0;
-        }
-        if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
-                printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
-                return 0;
-        }
-        if (aper_size < 64*1024*1024) {
-                printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20);
-                return 0;
-        }
-
-        return 1;
-}
 
 /* Find a PCI capability */
-static __u32 __init find_cap(int num, int slot, int func, int cap)
+static u32 __init find_cap(int bus, int slot, int func, int cap)
 {
         int bytes;
         u8 pos;
 
-        if (!(read_pci_config_16(num, slot, func, PCI_STATUS) &
+        if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
                                                 PCI_STATUS_CAP_LIST))
                 return 0;
 
-        pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
+        pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
         for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
                 u8 id;
 
                 pos &= ~3;
-                id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
+                id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
                 if (id == 0xff)
                         break;
                 if (id == cap)
                         return pos;
-                pos = read_pci_config_byte(num, slot, func,
+                pos = read_pci_config_byte(bus, slot, func,
                                                 pos+PCI_CAP_LIST_NEXT);
         }
         return 0;
 }
 
 /* Read a standard AGPv3 bridge header */
-static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
+static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
 {
         u32 apsize;
         u32 apsizereg;
         int nbits;
         u32 aper_low, aper_hi;
         u64 aper;
+        u32 old_order;
 
-        printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
-        apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
+        printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
+        apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
         if (apsizereg == 0xffffffff) {
                 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
                 return 0;
         }
 
+        /* old_order could be the value from NB gart setting */
+        old_order = *order;
+
         apsize = apsizereg & 0xfff;
         /* Some BIOS use weird encodings not in the AGPv3 table. */
         if (apsize & 0xff)
@@ -155,14 +165,26 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
         if ((int)*order < 0) /* < 32MB */
                 *order = 0;
 
-        aper_low = read_pci_config(num, slot, func, 0x10);
-        aper_hi = read_pci_config(num, slot, func, 0x14);
+        aper_low = read_pci_config(bus, slot, func, 0x10);
+        aper_hi = read_pci_config(bus, slot, func, 0x14);
         aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
 
+        /*
+         * On some sick chips, APSIZE is 0. It means it wants 4G
+         * so let double check that order, and lets trust AMD NB settings:
+         */
+        printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
+                        aper, 32 << old_order);
+        if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
+                printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
+                                32 << *order, apsizereg);
+                *order = old_order;
+        }
+
         printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
                         aper, 32 << *order, apsizereg);
 
-        if (!aperture_valid(aper, (32*1024*1024) << *order))
+        if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
                 return 0;
         return (u32)aper;
 }
@@ -180,17 +202,17 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
  * the AGP bridges should be always an own bus on the HT hierarchy,
  * but do it here for future safety.
  */
-static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
+static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
 {
-        int num, slot, func;
+        int bus, slot, func;
 
         /* Poor man's PCI discovery */
-        for (num = 0; num < 256; num++) {
+        for (bus = 0; bus < 256; bus++) {
                 for (slot = 0; slot < 32; slot++) {
                         for (func = 0; func < 8; func++) {
                                 u32 class, cap;
                                 u8 type;
-                                class = read_pci_config(num, slot, func,
+                                class = read_pci_config(bus, slot, func,
                                                         PCI_CLASS_REVISION);
                                 if (class == 0xffffffff)
                                         break;
@@ -199,17 +221,17 @@ static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
                                 case PCI_CLASS_BRIDGE_HOST:
                                 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
                                         /* AGP bridge? */
-                                        cap = find_cap(num, slot, func,
+                                        cap = find_cap(bus, slot, func,
                                                         PCI_CAP_ID_AGP);
                                         if (!cap)
                                                 break;
                                         *valid_agp = 1;
-                                        return read_agp(num, slot, func, cap,
+                                        return read_agp(bus, slot, func, cap,
                                                         order);
                                 }
 
                                 /* No multi-function device? */
-                                type = read_pci_config_byte(num, slot, func,
+                                type = read_pci_config_byte(bus, slot, func,
                                                                PCI_HEADER_TYPE);
                                 if (!(type & 0x80))
                                         break;
@@ -249,36 +271,50 @@ void __init early_gart_iommu_check(void)
          * or BIOS forget to put that in reserved.
          * try to update e820 to make that region as reserved.
          */
-        int fix, num;
+        int i, fix, slot;
         u32 ctl;
         u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
         u64 aper_base = 0, last_aper_base = 0;
-        int aper_enabled = 0, last_aper_enabled = 0;
+        int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
 
         if (!early_pci_allowed())
                 return;
 
+        /* This is mostly duplicate of iommu_hole_init */
         fix = 0;
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                ctl = read_pci_config(0, num, 3, 0x90);
-                aper_enabled = ctl & 1;
-                aper_order = (ctl >> 1) & 7;
-                aper_size = (32 * 1024 * 1024) << aper_order;
-                aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
-                aper_base <<= 25;
-
-                if ((last_aper_order && aper_order != last_aper_order) ||
-                    (last_aper_base && aper_base != last_aper_base) ||
-                    (last_aper_enabled && aper_enabled != last_aper_enabled)) {
-                        fix = 1;
-                        break;
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
+                        aper_enabled = ctl & AMD64_GARTEN;
+                        aper_order = (ctl >> 1) & 7;
+                        aper_size = (32 * 1024 * 1024) << aper_order;
+                        aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
+                        aper_base <<= 25;
+
+                        if (last_valid) {
+                                if ((aper_order != last_aper_order) ||
+                                    (aper_base != last_aper_base) ||
+                                    (aper_enabled != last_aper_enabled)) {
+                                        fix = 1;
+                                        break;
+                                }
+                        }
+
+                        last_aper_order = aper_order;
+                        last_aper_base = aper_base;
+                        last_aper_enabled = aper_enabled;
+                        last_valid = 1;
                 }
-                last_aper_order = aper_order;
-                last_aper_base = aper_base;
-                last_aper_enabled = aper_enabled;
         }
 
         if (!fix && !aper_enabled)
@@ -290,32 +326,46 @@ void __init early_gart_iommu_check(void)
         if (gart_fix_e820 && !fix && aper_enabled) {
                 if (e820_any_mapped(aper_base, aper_base + aper_size,
                                     E820_RAM)) {
-                        /* reserved it, so we can resuse it in second kernel */
+                        /* reserve it, so we can reuse it in second kernel */
                         printk(KERN_INFO "update e820 for GART\n");
                         add_memory_region(aper_base, aper_size, E820_RESERVED);
                         update_e820();
                 }
-                return;
         }
 
+        if (!fix)
+                return;
+
         /* different nodes have different setting, disable them all at first*/
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
 
-                ctl = read_pci_config(0, num, 3, 0x90);
-                ctl &= ~1;
-                write_pci_config(0, num, 3, 0x90, ctl);
+                        ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
+                        ctl &= ~AMD64_GARTEN;
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
+                }
         }
 
 }
 
+static int __initdata printed_gart_size_msg;
+
 void __init gart_iommu_hole_init(void)
 {
+        u32 agp_aper_base = 0, agp_aper_order = 0;
         u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
         u64 aper_base, last_aper_base = 0;
-        int fix, num, valid_agp = 0;
-        int node;
+        int fix, slot, valid_agp = 0;
+        int i, node;
 
         if (gart_iommu_aperture_disabled || !fix_aperture ||
             !early_pci_allowed())
@@ -323,38 +373,63 @@ void __init gart_iommu_hole_init(void)
 
         printk(KERN_INFO  "Checking aperture...\n");
 
+        if (!fallback_aper_force)
+                agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
+
         fix = 0;
         node = 0;
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                iommu_detected = 1;
-                gart_iommu_aperture = 1;
-
-                aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
-                aper_size = (32 * 1024 * 1024) << aper_order;
-                aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
-                aper_base <<= 25;
-
-                printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
-                                node, aper_base, aper_size >> 20);
-                node++;
-
-                if (!aperture_valid(aper_base, aper_size)) {
-                        fix = 1;
-                        break;
-                }
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        iommu_detected = 1;
+                        gart_iommu_aperture = 1;
+
+                        aper_order = (read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL) >> 1) & 7;
+                        aper_size = (32 * 1024 * 1024) << aper_order;
+                        aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
+                        aper_base <<= 25;
+
+                        printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
+                                        node, aper_base, aper_size >> 20);
+                        node++;
+
+                        if (!aperture_valid(aper_base, aper_size, 64<<20)) {
+                                if (valid_agp && agp_aper_base &&
+                                    agp_aper_base == aper_base &&
+                                    agp_aper_order == aper_order) {
+                                        /* the same between two setting from NB and agp */
+                                        if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
+                                                printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
+                                                printk(KERN_ERR "please increase GART size in your BIOS setup\n");
+                                                printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
+                                                printed_gart_size_msg = 1;
+                                        }
+                                } else {
+                                        fix = 1;
+                                        goto out;
+                                }
+                        }
 
-                if ((last_aper_order && aper_order != last_aper_order) ||
-                    (last_aper_base && aper_base != last_aper_base)) {
-                        fix = 1;
-                        break;
+                        if ((last_aper_order && aper_order != last_aper_order) ||
+                            (last_aper_base && aper_base != last_aper_base)) {
+                                fix = 1;
+                                goto out;
+                        }
+                        last_aper_order = aper_order;
+                        last_aper_base = aper_base;
                 }
-                last_aper_order = aper_order;
-                last_aper_base = aper_base;
         }
 
+out:
         if (!fix && !fallback_aper_force) {
                 if (last_aper_base) {
                         unsigned long n = (32 * 1024 * 1024) << last_aper_order;
@@ -364,8 +439,10 @@ void __init gart_iommu_hole_init(void)
                 return;
         }
 
-        if (!fallback_aper_force)
-                aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
+        if (!fallback_aper_force) {
+                aper_alloc = agp_aper_base;
+                aper_order = agp_aper_order;
+        }
 
         if (aper_alloc) {
                 /* Got the aperture from the AGP bridge */
@@ -401,16 +478,24 @@ void __init gart_iommu_hole_init(void)
         }
 
         /* Fix up the north bridges */
-        for (num = 24; num < 32; num++) {
-                if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
-                        continue;
-
-                /*
-                 * Don't enable translation yet. That is done later.
-                 * Assume this BIOS didn't initialise the GART so
-                 * just overwrite all previous bits
-                 */
-                write_pci_config(0, num, 3, 0x90, aper_order<<1);
-                write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
+        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+                int bus;
+                int dev_base, dev_limit;
+
+                bus = bus_dev_ranges[i].bus;
+                dev_base = bus_dev_ranges[i].dev_base;
+                dev_limit = bus_dev_ranges[i].dev_limit;
+                for (slot = dev_base; slot < dev_limit; slot++) {
+                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                                continue;
+
+                        /* Don't enable translation yet. That is done later.
+                           Assume this BIOS didn't initialise the GART so
+                           just overwrite all previous bits */
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, aper_order << 1);
+                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
+                }
         }
+
+        set_up_gart_resume(aper_order, aper_alloc);
 }