1 files changed, 13 insertions, 3 deletions

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index bbbe4bbb6f34..8c44c232efcb 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -34,12 +34,22 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                 flags->bm_check = 1;
         else if (c->x86_vendor == X86_VENDOR_INTEL) {
                 /*
-                 * Today all CPUs that support C3 share cache.
-                 * TBD: This needs to look at cache shared map, once
-                 * multi-core detection patch makes to the base.
+                 * Today all MP CPUs that support C3 share cache.
+                 * And caches should not be flushed by software while
+                 * entering C3 type state.
                  */
                 flags->bm_check = 1;
         }
+
+        /*
+         * On all recent Intel platforms, ARB_DISABLE is a nop.
+         * So, set bm_control to zero to indicate that ARB_DISABLE
+         * is not required while entering C3 type state on
+         * P4, Core and beyond CPUs
+         */
+        if (c->x86_vendor == X86_VENDOR_INTEL &&
+            (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)))
+                        flags->bm_control = 0;
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);