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-rw-r--r--arch/x86/include/asm/alternative-asm.h5
-rw-r--r--arch/x86/include/asm/alternative.h12
-rw-r--r--arch/x86/include/asm/amd_iommu.h35
-rw-r--r--arch/x86/include/asm/amd_iommu_proto.h54
-rw-r--r--arch/x86/include/asm/amd_iommu_types.h580
-rw-r--r--arch/x86/include/asm/apb_timer.h23
-rw-r--r--arch/x86/include/asm/apic.h4
-rw-r--r--arch/x86/include/asm/asm.h5
-rw-r--r--arch/x86/include/asm/atomic.h10
-rw-r--r--arch/x86/include/asm/atomic64_32.h2
-rw-r--r--arch/x86/include/asm/atomic64_64.h2
-rw-r--r--arch/x86/include/asm/bitops.h5
-rw-r--r--arch/x86/include/asm/calling.h130
-rw-r--r--arch/x86/include/asm/clocksource.h18
-rw-r--r--arch/x86/include/asm/cmpxchg_32.h48
-rw-r--r--arch/x86/include/asm/cmpxchg_64.h45
-rw-r--r--arch/x86/include/asm/cpufeature.h12
-rw-r--r--arch/x86/include/asm/delay.h25
-rw-r--r--arch/x86/include/asm/desc.h4
-rw-r--r--arch/x86/include/asm/device.h2
-rw-r--r--arch/x86/include/asm/dma-mapping.h2
-rw-r--r--arch/x86/include/asm/dwarf2.h2
-rw-r--r--arch/x86/include/asm/entry_arch.h4
-rw-r--r--arch/x86/include/asm/fixmap.h1
-rw-r--r--arch/x86/include/asm/frame.h11
-rw-r--r--arch/x86/include/asm/hw_irq.h5
-rw-r--r--arch/x86/include/asm/hyperv.h1
-rw-r--r--arch/x86/include/asm/i8253.h20
-rw-r--r--arch/x86/include/asm/io.h3
-rw-r--r--arch/x86/include/asm/irq_remapping.h6
-rw-r--r--arch/x86/include/asm/irq_vectors.h19
-rw-r--r--arch/x86/include/asm/irqflags.h11
-rw-r--r--arch/x86/include/asm/kdebug.h1
-rw-r--r--arch/x86/include/asm/kvm_emulate.h52
-rw-r--r--arch/x86/include/asm/kvm_host.h46
-rw-r--r--arch/x86/include/asm/kvm_para.h20
-rw-r--r--arch/x86/include/asm/lguest_hcall.h1
-rw-r--r--arch/x86/include/asm/local.h2
-rw-r--r--arch/x86/include/asm/mce.h21
-rw-r--r--arch/x86/include/asm/mmu_context.h2
-rw-r--r--arch/x86/include/asm/mmzone_32.h6
-rw-r--r--arch/x86/include/asm/msr-index.h12
-rw-r--r--arch/x86/include/asm/nmi.h37
-rw-r--r--arch/x86/include/asm/olpc.h51
-rw-r--r--arch/x86/include/asm/paravirt.h9
-rw-r--r--arch/x86/include/asm/paravirt_types.h7
-rw-r--r--arch/x86/include/asm/percpu.h11
-rw-r--r--arch/x86/include/asm/perf_event.h60
-rw-r--r--arch/x86/include/asm/perf_event_p4.h33
-rw-r--r--arch/x86/include/asm/pgtable_types.h6
-rw-r--r--arch/x86/include/asm/processor-flags.h1
-rw-r--r--arch/x86/include/asm/processor.h2
-rw-r--r--arch/x86/include/asm/prom.h13
-rw-r--r--arch/x86/include/asm/ptrace.h19
-rw-r--r--arch/x86/include/asm/pvclock.h2
-rw-r--r--arch/x86/include/asm/reboot.h2
-rw-r--r--arch/x86/include/asm/rwlock.h43
-rw-r--r--arch/x86/include/asm/segment.h2
-rw-r--r--arch/x86/include/asm/smpboot_hooks.h8
-rw-r--r--arch/x86/include/asm/spinlock.h39
-rw-r--r--arch/x86/include/asm/spinlock_types.h6
-rw-r--r--arch/x86/include/asm/thread_info.h2
-rw-r--r--arch/x86/include/asm/time.h6
-rw-r--r--arch/x86/include/asm/traps.h2
-rw-r--r--arch/x86/include/asm/tsc.h4
-rw-r--r--arch/x86/include/asm/uaccess.h3
-rw-r--r--arch/x86/include/asm/unistd_64.h5
-rw-r--r--arch/x86/include/asm/uv/uv_bau.h59
-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h2889
-rw-r--r--arch/x86/include/asm/vgtod.h3
-rw-r--r--arch/x86/include/asm/vmx.h43
-rw-r--r--arch/x86/include/asm/vsyscall.h10
-rw-r--r--arch/x86/include/asm/vvar.h24
-rw-r--r--arch/x86/include/asm/xen/hypercall.h22
-rw-r--r--arch/x86/include/asm/xen/page.h10
-rw-r--r--arch/x86/include/asm/xen/pci.h5
-rw-r--r--arch/x86/include/asm/xen/trace_types.h18
77 files changed, 2364 insertions, 2361 deletions
diff --git a/arch/x86/include/asm/alternative-asm.h b/arch/x86/include/asm/alternative-asm.h
index 94d420b360d1..091508b533b4 100644
--- a/arch/x86/include/asm/alternative-asm.h
+++ b/arch/x86/include/asm/alternative-asm.h
@@ -16,9 +16,8 @@
16#endif 16#endif
17 17
18.macro altinstruction_entry orig alt feature orig_len alt_len 18.macro altinstruction_entry orig alt feature orig_len alt_len
19 .align 8 19 .long \orig - .
20 .quad \orig 20 .long \alt - .
21 .quad \alt
22 .word \feature 21 .word \feature
23 .byte \orig_len 22 .byte \orig_len
24 .byte \alt_len 23 .byte \alt_len
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index bf535f947e8c..37ad100a2210 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -43,14 +43,11 @@
43#endif 43#endif
44 44
45struct alt_instr { 45struct alt_instr {
46 u8 *instr; /* original instruction */ 46 s32 instr_offset; /* original instruction */
47 u8 *replacement; 47 s32 repl_offset; /* offset to replacement instruction */
48 u16 cpuid; /* cpuid bit set for replacement */ 48 u16 cpuid; /* cpuid bit set for replacement */
49 u8 instrlen; /* length of original instruction */ 49 u8 instrlen; /* length of original instruction */
50 u8 replacementlen; /* length of new instruction, <= instrlen */ 50 u8 replacementlen; /* length of new instruction, <= instrlen */
51#ifdef CONFIG_X86_64
52 u32 pad2;
53#endif
54}; 51};
55 52
56extern void alternative_instructions(void); 53extern void alternative_instructions(void);
@@ -83,9 +80,8 @@ static inline int alternatives_text_reserved(void *start, void *end)
83 \ 80 \
84 "661:\n\t" oldinstr "\n662:\n" \ 81 "661:\n\t" oldinstr "\n662:\n" \
85 ".section .altinstructions,\"a\"\n" \ 82 ".section .altinstructions,\"a\"\n" \
86 _ASM_ALIGN "\n" \ 83 " .long 661b - .\n" /* label */ \
87 _ASM_PTR "661b\n" /* label */ \ 84 " .long 663f - .\n" /* new instruction */ \
88 _ASM_PTR "663f\n" /* new instruction */ \
89 " .word " __stringify(feature) "\n" /* feature bit */ \ 85 " .word " __stringify(feature) "\n" /* feature bit */ \
90 " .byte 662b-661b\n" /* sourcelen */ \ 86 " .byte 662b-661b\n" /* sourcelen */ \
91 " .byte 664f-663f\n" /* replacementlen */ \ 87 " .byte 664f-663f\n" /* replacementlen */ \
diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h
deleted file mode 100644
index a6863a2dec1f..000000000000
--- a/arch/x86/include/asm/amd_iommu.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_X86_AMD_IOMMU_H
21#define _ASM_X86_AMD_IOMMU_H
22
23#include <linux/irqreturn.h>
24
25#ifdef CONFIG_AMD_IOMMU
26
27extern int amd_iommu_detect(void);
28
29#else
30
31static inline int amd_iommu_detect(void) { return -ENODEV; }
32
33#endif
34
35#endif /* _ASM_X86_AMD_IOMMU_H */
diff --git a/arch/x86/include/asm/amd_iommu_proto.h b/arch/x86/include/asm/amd_iommu_proto.h
deleted file mode 100644
index 55d95eb789b3..000000000000
--- a/arch/x86/include/asm/amd_iommu_proto.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef _ASM_X86_AMD_IOMMU_PROTO_H
20#define _ASM_X86_AMD_IOMMU_PROTO_H
21
22#include <asm/amd_iommu_types.h>
23
24extern int amd_iommu_init_dma_ops(void);
25extern int amd_iommu_init_passthrough(void);
26extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
27extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
28extern void amd_iommu_apply_erratum_63(u16 devid);
29extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
30extern int amd_iommu_init_devices(void);
31extern void amd_iommu_uninit_devices(void);
32extern void amd_iommu_init_notifier(void);
33extern void amd_iommu_init_api(void);
34#ifndef CONFIG_AMD_IOMMU_STATS
35
36static inline void amd_iommu_stats_init(void) { }
37
38#endif /* !CONFIG_AMD_IOMMU_STATS */
39
40static inline bool is_rd890_iommu(struct pci_dev *pdev)
41{
42 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
43 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
44}
45
46static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)
47{
48 if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
49 return false;
50
51 return !!(iommu->features & f);
52}
53
54#endif /* _ASM_X86_AMD_IOMMU_PROTO_H */
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
deleted file mode 100644
index 4c9982995414..000000000000
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ /dev/null
@@ -1,580 +0,0 @@
1/*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21#define _ASM_X86_AMD_IOMMU_TYPES_H
22
23#include <linux/types.h>
24#include <linux/mutex.h>
25#include <linux/list.h>
26#include <linux/spinlock.h>
27
28/*
29 * Maximum number of IOMMUs supported
30 */
31#define MAX_IOMMUS 32
32
33/*
34 * some size calculation constants
35 */
36#define DEV_TABLE_ENTRY_SIZE 32
37#define ALIAS_TABLE_ENTRY_SIZE 2
38#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
39
40/* Length of the MMIO region for the AMD IOMMU */
41#define MMIO_REGION_LENGTH 0x4000
42
43/* Capability offsets used by the driver */
44#define MMIO_CAP_HDR_OFFSET 0x00
45#define MMIO_RANGE_OFFSET 0x0c
46#define MMIO_MISC_OFFSET 0x10
47
48/* Masks, shifts and macros to parse the device range capability */
49#define MMIO_RANGE_LD_MASK 0xff000000
50#define MMIO_RANGE_FD_MASK 0x00ff0000
51#define MMIO_RANGE_BUS_MASK 0x0000ff00
52#define MMIO_RANGE_LD_SHIFT 24
53#define MMIO_RANGE_FD_SHIFT 16
54#define MMIO_RANGE_BUS_SHIFT 8
55#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58#define MMIO_MSI_NUM(x) ((x) & 0x1f)
59
60/* Flag masks for the AMD IOMMU exclusion range */
61#define MMIO_EXCL_ENABLE_MASK 0x01ULL
62#define MMIO_EXCL_ALLOW_MASK 0x02ULL
63
64/* Used offsets into the MMIO space */
65#define MMIO_DEV_TABLE_OFFSET 0x0000
66#define MMIO_CMD_BUF_OFFSET 0x0008
67#define MMIO_EVT_BUF_OFFSET 0x0010
68#define MMIO_CONTROL_OFFSET 0x0018
69#define MMIO_EXCL_BASE_OFFSET 0x0020
70#define MMIO_EXCL_LIMIT_OFFSET 0x0028
71#define MMIO_EXT_FEATURES 0x0030
72#define MMIO_CMD_HEAD_OFFSET 0x2000
73#define MMIO_CMD_TAIL_OFFSET 0x2008
74#define MMIO_EVT_HEAD_OFFSET 0x2010
75#define MMIO_EVT_TAIL_OFFSET 0x2018
76#define MMIO_STATUS_OFFSET 0x2020
77
78
79/* Extended Feature Bits */
80#define FEATURE_PREFETCH (1ULL<<0)
81#define FEATURE_PPR (1ULL<<1)
82#define FEATURE_X2APIC (1ULL<<2)
83#define FEATURE_NX (1ULL<<3)
84#define FEATURE_GT (1ULL<<4)
85#define FEATURE_IA (1ULL<<6)
86#define FEATURE_GA (1ULL<<7)
87#define FEATURE_HE (1ULL<<8)
88#define FEATURE_PC (1ULL<<9)
89
90/* MMIO status bits */
91#define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
92
93/* event logging constants */
94#define EVENT_ENTRY_SIZE 0x10
95#define EVENT_TYPE_SHIFT 28
96#define EVENT_TYPE_MASK 0xf
97#define EVENT_TYPE_ILL_DEV 0x1
98#define EVENT_TYPE_IO_FAULT 0x2
99#define EVENT_TYPE_DEV_TAB_ERR 0x3
100#define EVENT_TYPE_PAGE_TAB_ERR 0x4
101#define EVENT_TYPE_ILL_CMD 0x5
102#define EVENT_TYPE_CMD_HARD_ERR 0x6
103#define EVENT_TYPE_IOTLB_INV_TO 0x7
104#define EVENT_TYPE_INV_DEV_REQ 0x8
105#define EVENT_DEVID_MASK 0xffff
106#define EVENT_DEVID_SHIFT 0
107#define EVENT_DOMID_MASK 0xffff
108#define EVENT_DOMID_SHIFT 0
109#define EVENT_FLAGS_MASK 0xfff
110#define EVENT_FLAGS_SHIFT 0x10
111
112/* feature control bits */
113#define CONTROL_IOMMU_EN 0x00ULL
114#define CONTROL_HT_TUN_EN 0x01ULL
115#define CONTROL_EVT_LOG_EN 0x02ULL
116#define CONTROL_EVT_INT_EN 0x03ULL
117#define CONTROL_COMWAIT_EN 0x04ULL
118#define CONTROL_PASSPW_EN 0x08ULL
119#define CONTROL_RESPASSPW_EN 0x09ULL
120#define CONTROL_COHERENT_EN 0x0aULL
121#define CONTROL_ISOC_EN 0x0bULL
122#define CONTROL_CMDBUF_EN 0x0cULL
123#define CONTROL_PPFLOG_EN 0x0dULL
124#define CONTROL_PPFINT_EN 0x0eULL
125
126/* command specific defines */
127#define CMD_COMPL_WAIT 0x01
128#define CMD_INV_DEV_ENTRY 0x02
129#define CMD_INV_IOMMU_PAGES 0x03
130#define CMD_INV_IOTLB_PAGES 0x04
131#define CMD_INV_ALL 0x08
132
133#define CMD_COMPL_WAIT_STORE_MASK 0x01
134#define CMD_COMPL_WAIT_INT_MASK 0x02
135#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
136#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
137
138#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
139
140/* macros and definitions for device table entries */
141#define DEV_ENTRY_VALID 0x00
142#define DEV_ENTRY_TRANSLATION 0x01
143#define DEV_ENTRY_IR 0x3d
144#define DEV_ENTRY_IW 0x3e
145#define DEV_ENTRY_NO_PAGE_FAULT 0x62
146#define DEV_ENTRY_EX 0x67
147#define DEV_ENTRY_SYSMGT1 0x68
148#define DEV_ENTRY_SYSMGT2 0x69
149#define DEV_ENTRY_INIT_PASS 0xb8
150#define DEV_ENTRY_EINT_PASS 0xb9
151#define DEV_ENTRY_NMI_PASS 0xba
152#define DEV_ENTRY_LINT0_PASS 0xbe
153#define DEV_ENTRY_LINT1_PASS 0xbf
154#define DEV_ENTRY_MODE_MASK 0x07
155#define DEV_ENTRY_MODE_SHIFT 0x09
156
157/* constants to configure the command buffer */
158#define CMD_BUFFER_SIZE 8192
159#define CMD_BUFFER_UNINITIALIZED 1
160#define CMD_BUFFER_ENTRIES 512
161#define MMIO_CMD_SIZE_SHIFT 56
162#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
163
164/* constants for event buffer handling */
165#define EVT_BUFFER_SIZE 8192 /* 512 entries */
166#define EVT_LEN_MASK (0x9ULL << 56)
167
168#define PAGE_MODE_NONE 0x00
169#define PAGE_MODE_1_LEVEL 0x01
170#define PAGE_MODE_2_LEVEL 0x02
171#define PAGE_MODE_3_LEVEL 0x03
172#define PAGE_MODE_4_LEVEL 0x04
173#define PAGE_MODE_5_LEVEL 0x05
174#define PAGE_MODE_6_LEVEL 0x06
175
176#define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
177#define PM_LEVEL_SIZE(x) (((x) < 6) ? \
178 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
179 (0xffffffffffffffffULL))
180#define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
181#define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
182#define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
183 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
184#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
185
186#define PM_MAP_4k 0
187#define PM_ADDR_MASK 0x000ffffffffff000ULL
188#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
189 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
190#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
191
192/*
193 * Returns the page table level to use for a given page size
194 * Pagesize is expected to be a power-of-two
195 */
196#define PAGE_SIZE_LEVEL(pagesize) \
197 ((__ffs(pagesize) - 12) / 9)
198/*
199 * Returns the number of ptes to use for a given page size
200 * Pagesize is expected to be a power-of-two
201 */
202#define PAGE_SIZE_PTE_COUNT(pagesize) \
203 (1ULL << ((__ffs(pagesize) - 12) % 9))
204
205/*
206 * Aligns a given io-virtual address to a given page size
207 * Pagesize is expected to be a power-of-two
208 */
209#define PAGE_SIZE_ALIGN(address, pagesize) \
210 ((address) & ~((pagesize) - 1))
211/*
212 * Creates an IOMMU PTE for an address an a given pagesize
213 * The PTE has no permission bits set
214 * Pagesize is expected to be a power-of-two larger than 4096
215 */
216#define PAGE_SIZE_PTE(address, pagesize) \
217 (((address) | ((pagesize) - 1)) & \
218 (~(pagesize >> 1)) & PM_ADDR_MASK)
219
220/*
221 * Takes a PTE value with mode=0x07 and returns the page size it maps
222 */
223#define PTE_PAGE_SIZE(pte) \
224 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
225
226#define IOMMU_PTE_P (1ULL << 0)
227#define IOMMU_PTE_TV (1ULL << 1)
228#define IOMMU_PTE_U (1ULL << 59)
229#define IOMMU_PTE_FC (1ULL << 60)
230#define IOMMU_PTE_IR (1ULL << 61)
231#define IOMMU_PTE_IW (1ULL << 62)
232
233#define DTE_FLAG_IOTLB 0x01
234
235#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
236#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
237#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
238#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
239
240#define IOMMU_PROT_MASK 0x03
241#define IOMMU_PROT_IR 0x01
242#define IOMMU_PROT_IW 0x02
243
244/* IOMMU capabilities */
245#define IOMMU_CAP_IOTLB 24
246#define IOMMU_CAP_NPCACHE 26
247#define IOMMU_CAP_EFR 27
248
249#define MAX_DOMAIN_ID 65536
250
251/* FIXME: move this macro to <linux/pci.h> */
252#define PCI_BUS(x) (((x) >> 8) & 0xff)
253
254/* Protection domain flags */
255#define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
256#define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
257 domain for an IOMMU */
258#define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
259 translation */
260
261extern bool amd_iommu_dump;
262#define DUMP_printk(format, arg...) \
263 do { \
264 if (amd_iommu_dump) \
265 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
266 } while(0);
267
268/* global flag if IOMMUs cache non-present entries */
269extern bool amd_iommu_np_cache;
270/* Only true if all IOMMUs support device IOTLBs */
271extern bool amd_iommu_iotlb_sup;
272
273/*
274 * Make iterating over all IOMMUs easier
275 */
276#define for_each_iommu(iommu) \
277 list_for_each_entry((iommu), &amd_iommu_list, list)
278#define for_each_iommu_safe(iommu, next) \
279 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
280
281#define APERTURE_RANGE_SHIFT 27 /* 128 MB */
282#define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
283#define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
284#define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
285#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
286#define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
287
288/*
289 * This structure contains generic data for IOMMU protection domains
290 * independent of their use.
291 */
292struct protection_domain {
293 struct list_head list; /* for list of all protection domains */
294 struct list_head dev_list; /* List of all devices in this domain */
295 spinlock_t lock; /* mostly used to lock the page table*/
296 struct mutex api_lock; /* protect page tables in the iommu-api path */
297 u16 id; /* the domain id written to the device table */
298 int mode; /* paging mode (0-6 levels) */
299 u64 *pt_root; /* page table root pointer */
300 unsigned long flags; /* flags to find out type of domain */
301 bool updated; /* complete domain flush required */
302 unsigned dev_cnt; /* devices assigned to this domain */
303 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
304 void *priv; /* private data */
305
306};
307
308/*
309 * This struct contains device specific data for the IOMMU
310 */
311struct iommu_dev_data {
312 struct list_head list; /* For domain->dev_list */
313 struct device *dev; /* Device this data belong to */
314 struct device *alias; /* The Alias Device */
315 struct protection_domain *domain; /* Domain the device is bound to */
316 atomic_t bind; /* Domain attach reverent count */
317};
318
319/*
320 * For dynamic growth the aperture size is split into ranges of 128MB of
321 * DMA address space each. This struct represents one such range.
322 */
323struct aperture_range {
324
325 /* address allocation bitmap */
326 unsigned long *bitmap;
327
328 /*
329 * Array of PTE pages for the aperture. In this array we save all the
330 * leaf pages of the domain page table used for the aperture. This way
331 * we don't need to walk the page table to find a specific PTE. We can
332 * just calculate its address in constant time.
333 */
334 u64 *pte_pages[64];
335
336 unsigned long offset;
337};
338
339/*
340 * Data container for a dma_ops specific protection domain
341 */
342struct dma_ops_domain {
343 struct list_head list;
344
345 /* generic protection domain information */
346 struct protection_domain domain;
347
348 /* size of the aperture for the mappings */
349 unsigned long aperture_size;
350
351 /* address we start to search for free addresses */
352 unsigned long next_address;
353
354 /* address space relevant data */
355 struct aperture_range *aperture[APERTURE_MAX_RANGES];
356
357 /* This will be set to true when TLB needs to be flushed */
358 bool need_flush;
359
360 /*
361 * if this is a preallocated domain, keep the device for which it was
362 * preallocated in this variable
363 */
364 u16 target_dev;
365};
366
367/*
368 * Structure where we save information about one hardware AMD IOMMU in the
369 * system.
370 */
371struct amd_iommu {
372 struct list_head list;
373
374 /* Index within the IOMMU array */
375 int index;
376
377 /* locks the accesses to the hardware */
378 spinlock_t lock;
379
380 /* Pointer to PCI device of this IOMMU */
381 struct pci_dev *dev;
382
383 /* physical address of MMIO space */
384 u64 mmio_phys;
385 /* virtual address of MMIO space */
386 u8 *mmio_base;
387
388 /* capabilities of that IOMMU read from ACPI */
389 u32 cap;
390
391 /* flags read from acpi table */
392 u8 acpi_flags;
393
394 /* Extended features */
395 u64 features;
396
397 /*
398 * Capability pointer. There could be more than one IOMMU per PCI
399 * device function if there are more than one AMD IOMMU capability
400 * pointers.
401 */
402 u16 cap_ptr;
403
404 /* pci domain of this IOMMU */
405 u16 pci_seg;
406
407 /* first device this IOMMU handles. read from PCI */
408 u16 first_device;
409 /* last device this IOMMU handles. read from PCI */
410 u16 last_device;
411
412 /* start of exclusion range of that IOMMU */
413 u64 exclusion_start;
414 /* length of exclusion range of that IOMMU */
415 u64 exclusion_length;
416
417 /* command buffer virtual address */
418 u8 *cmd_buf;
419 /* size of command buffer */
420 u32 cmd_buf_size;
421
422 /* size of event buffer */
423 u32 evt_buf_size;
424 /* event buffer virtual address */
425 u8 *evt_buf;
426 /* MSI number for event interrupt */
427 u16 evt_msi_num;
428
429 /* true if interrupts for this IOMMU are already enabled */
430 bool int_enabled;
431
432 /* if one, we need to send a completion wait command */
433 bool need_sync;
434
435 /* default dma_ops domain for that IOMMU */
436 struct dma_ops_domain *default_dom;
437
438 /*
439 * We can't rely on the BIOS to restore all values on reinit, so we
440 * need to stash them
441 */
442
443 /* The iommu BAR */
444 u32 stored_addr_lo;
445 u32 stored_addr_hi;
446
447 /*
448 * Each iommu has 6 l1s, each of which is documented as having 0x12
449 * registers
450 */
451 u32 stored_l1[6][0x12];
452
453 /* The l2 indirect registers */
454 u32 stored_l2[0x83];
455};
456
457/*
458 * List with all IOMMUs in the system. This list is not locked because it is
459 * only written and read at driver initialization or suspend time
460 */
461extern struct list_head amd_iommu_list;
462
463/*
464 * Array with pointers to each IOMMU struct
465 * The indices are referenced in the protection domains
466 */
467extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
468
469/* Number of IOMMUs present in the system */
470extern int amd_iommus_present;
471
472/*
473 * Declarations for the global list of all protection domains
474 */
475extern spinlock_t amd_iommu_pd_lock;
476extern struct list_head amd_iommu_pd_list;
477
478/*
479 * Structure defining one entry in the device table
480 */
481struct dev_table_entry {
482 u32 data[8];
483};
484
485/*
486 * One entry for unity mappings parsed out of the ACPI table.
487 */
488struct unity_map_entry {
489 struct list_head list;
490
491 /* starting device id this entry is used for (including) */
492 u16 devid_start;
493 /* end device id this entry is used for (including) */
494 u16 devid_end;
495
496 /* start address to unity map (including) */
497 u64 address_start;
498 /* end address to unity map (including) */
499 u64 address_end;
500
501 /* required protection */
502 int prot;
503};
504
505/*
506 * List of all unity mappings. It is not locked because as runtime it is only
507 * read. It is created at ACPI table parsing time.
508 */
509extern struct list_head amd_iommu_unity_map;
510
511/*
512 * Data structures for device handling
513 */
514
515/*
516 * Device table used by hardware. Read and write accesses by software are
517 * locked with the amd_iommu_pd_table lock.
518 */
519extern struct dev_table_entry *amd_iommu_dev_table;
520
521/*
522 * Alias table to find requestor ids to device ids. Not locked because only
523 * read on runtime.
524 */
525extern u16 *amd_iommu_alias_table;
526
527/*
528 * Reverse lookup table to find the IOMMU which translates a specific device.
529 */
530extern struct amd_iommu **amd_iommu_rlookup_table;
531
532/* size of the dma_ops aperture as power of 2 */
533extern unsigned amd_iommu_aperture_order;
534
535/* largest PCI device id we expect translation requests for */
536extern u16 amd_iommu_last_bdf;
537
538/* allocation bitmap for domain ids */
539extern unsigned long *amd_iommu_pd_alloc_bitmap;
540
541/*
542 * If true, the addresses will be flushed on unmap time, not when
543 * they are reused
544 */
545extern bool amd_iommu_unmap_flush;
546
547/* takes bus and device/function and returns the device id
548 * FIXME: should that be in generic PCI code? */
549static inline u16 calc_devid(u8 bus, u8 devfn)
550{
551 return (((u16)bus) << 8) | devfn;
552}
553
554#ifdef CONFIG_AMD_IOMMU_STATS
555
556struct __iommu_counter {
557 char *name;
558 struct dentry *dent;
559 u64 value;
560};
561
562#define DECLARE_STATS_COUNTER(nm) \
563 static struct __iommu_counter nm = { \
564 .name = #nm, \
565 }
566
567#define INC_STATS_COUNTER(name) name.value += 1
568#define ADD_STATS_COUNTER(name, x) name.value += (x)
569#define SUB_STATS_COUNTER(name, x) name.value -= (x)
570
571#else /* CONFIG_AMD_IOMMU_STATS */
572
573#define DECLARE_STATS_COUNTER(name)
574#define INC_STATS_COUNTER(name)
575#define ADD_STATS_COUNTER(name, x)
576#define SUB_STATS_COUNTER(name, x)
577
578#endif /* CONFIG_AMD_IOMMU_STATS */
579
580#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
diff --git a/arch/x86/include/asm/apb_timer.h b/arch/x86/include/asm/apb_timer.h
index af60d8a2e288..0acbac299e49 100644
--- a/arch/x86/include/asm/apb_timer.h
+++ b/arch/x86/include/asm/apb_timer.h
@@ -18,24 +18,6 @@
18 18
19#ifdef CONFIG_APB_TIMER 19#ifdef CONFIG_APB_TIMER
20 20
21/* Langwell DW APB timer registers */
22#define APBTMR_N_LOAD_COUNT 0x00
23#define APBTMR_N_CURRENT_VALUE 0x04
24#define APBTMR_N_CONTROL 0x08
25#define APBTMR_N_EOI 0x0c
26#define APBTMR_N_INT_STATUS 0x10
27
28#define APBTMRS_INT_STATUS 0xa0
29#define APBTMRS_EOI 0xa4
30#define APBTMRS_RAW_INT_STATUS 0xa8
31#define APBTMRS_COMP_VERSION 0xac
32#define APBTMRS_REG_SIZE 0x14
33
34/* register bits */
35#define APBTMR_CONTROL_ENABLE (1<<0)
36#define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */
37#define APBTMR_CONTROL_INT (1<<2)
38
39/* default memory mapped register base */ 21/* default memory mapped register base */
40#define LNW_SCU_ADDR 0xFF100000 22#define LNW_SCU_ADDR 0xFF100000
41#define LNW_EXT_TIMER_OFFSET 0x1B800 23#define LNW_EXT_TIMER_OFFSET 0x1B800
@@ -43,14 +25,13 @@
43#define LNW_EXT_TIMER_PGOFFSET 0x800 25#define LNW_EXT_TIMER_PGOFFSET 0x800
44 26
45/* APBT clock speed range from PCLK to fabric base, 25-100MHz */ 27/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
46#define APBT_MAX_FREQ 50 28#define APBT_MAX_FREQ 50000000
47#define APBT_MIN_FREQ 1 29#define APBT_MIN_FREQ 1000000
48#define APBT_MMAP_SIZE 1024 30#define APBT_MMAP_SIZE 1024
49 31
50#define APBT_DEV_USED 1 32#define APBT_DEV_USED 1
51 33
52extern void apbt_time_init(void); 34extern void apbt_time_init(void);
53extern struct clock_event_device *global_clock_event;
54extern unsigned long apbt_quick_calibrate(void); 35extern unsigned long apbt_quick_calibrate(void);
55extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu); 36extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
56extern void apbt_setup_secondary_clock(void); 37extern void apbt_setup_secondary_clock(void);
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 4a0b7c7e2cce..9b7273cb2193 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -8,7 +8,7 @@
8#include <asm/cpufeature.h> 8#include <asm/cpufeature.h>
9#include <asm/processor.h> 9#include <asm/processor.h>
10#include <asm/apicdef.h> 10#include <asm/apicdef.h>
11#include <asm/atomic.h> 11#include <linux/atomic.h>
12#include <asm/fixmap.h> 12#include <asm/fixmap.h>
13#include <asm/mpspec.h> 13#include <asm/mpspec.h>
14#include <asm/system.h> 14#include <asm/system.h>
@@ -495,7 +495,7 @@ static inline void default_wait_for_init_deassert(atomic_t *deassert)
495 return; 495 return;
496} 496}
497 497
498extern struct apic *generic_bigsmp_probe(void); 498extern void generic_bigsmp_probe(void);
499 499
500 500
501#ifdef CONFIG_X86_LOCAL_APIC 501#ifdef CONFIG_X86_LOCAL_APIC
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index b3ed1e1460ff..9412d6558c88 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -3,9 +3,11 @@
3 3
4#ifdef __ASSEMBLY__ 4#ifdef __ASSEMBLY__
5# define __ASM_FORM(x) x 5# define __ASM_FORM(x) x
6# define __ASM_FORM_COMMA(x) x,
6# define __ASM_EX_SEC .section __ex_table, "a" 7# define __ASM_EX_SEC .section __ex_table, "a"
7#else 8#else
8# define __ASM_FORM(x) " " #x " " 9# define __ASM_FORM(x) " " #x " "
10# define __ASM_FORM_COMMA(x) " " #x ","
9# define __ASM_EX_SEC " .section __ex_table,\"a\"\n" 11# define __ASM_EX_SEC " .section __ex_table,\"a\"\n"
10#endif 12#endif
11 13
@@ -15,7 +17,8 @@
15# define __ASM_SEL(a,b) __ASM_FORM(b) 17# define __ASM_SEL(a,b) __ASM_FORM(b)
16#endif 18#endif
17 19
18#define __ASM_SIZE(inst) __ASM_SEL(inst##l, inst##q) 20#define __ASM_SIZE(inst, ...) __ASM_SEL(inst##l##__VA_ARGS__, \
21 inst##q##__VA_ARGS__)
19#define __ASM_REG(reg) __ASM_SEL(e##reg, r##reg) 22#define __ASM_REG(reg) __ASM_SEL(e##reg, r##reg)
20 23
21#define _ASM_PTR __ASM_SEL(.long, .quad) 24#define _ASM_PTR __ASM_SEL(.long, .quad)
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 952a826ac4e5..10572e309ab2 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -221,15 +221,15 @@ static inline int atomic_xchg(atomic_t *v, int new)
221} 221}
222 222
223/** 223/**
224 * atomic_add_unless - add unless the number is already a given value 224 * __atomic_add_unless - add unless the number is already a given value
225 * @v: pointer of type atomic_t 225 * @v: pointer of type atomic_t
226 * @a: the amount to add to v... 226 * @a: the amount to add to v...
227 * @u: ...unless v is equal to u. 227 * @u: ...unless v is equal to u.
228 * 228 *
229 * Atomically adds @a to @v, so long as @v was not already @u. 229 * Atomically adds @a to @v, so long as @v was not already @u.
230 * Returns non-zero if @v was not @u, and zero otherwise. 230 * Returns the old value of @v.
231 */ 231 */
232static inline int atomic_add_unless(atomic_t *v, int a, int u) 232static inline int __atomic_add_unless(atomic_t *v, int a, int u)
233{ 233{
234 int c, old; 234 int c, old;
235 c = atomic_read(v); 235 c = atomic_read(v);
@@ -241,10 +241,9 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
241 break; 241 break;
242 c = old; 242 c = old;
243 } 243 }
244 return c != (u); 244 return c;
245} 245}
246 246
247#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
248 247
249/* 248/*
250 * atomic_dec_if_positive - decrement by 1 if old value positive 249 * atomic_dec_if_positive - decrement by 1 if old value positive
@@ -319,5 +318,4 @@ static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
319# include "atomic64_64.h" 318# include "atomic64_64.h"
320#endif 319#endif
321 320
322#include <asm-generic/atomic-long.h>
323#endif /* _ASM_X86_ATOMIC_H */ 321#endif /* _ASM_X86_ATOMIC_H */
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index 2a934aa19a43..24098aafce0d 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -263,7 +263,7 @@ static inline int atomic64_add_negative(long long i, atomic64_t *v)
263 * @u: ...unless v is equal to u. 263 * @u: ...unless v is equal to u.
264 * 264 *
265 * Atomically adds @a to @v, so long as it was not @u. 265 * Atomically adds @a to @v, so long as it was not @u.
266 * Returns non-zero if @v was not @u, and zero otherwise. 266 * Returns the old value of @v.
267 */ 267 */
268static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u) 268static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
269{ 269{
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
index 49fd1ea22951..017594d403f6 100644
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -202,7 +202,7 @@ static inline long atomic64_xchg(atomic64_t *v, long new)
202 * @u: ...unless v is equal to u. 202 * @u: ...unless v is equal to u.
203 * 203 *
204 * Atomically adds @a to @v, so long as it was not @u. 204 * Atomically adds @a to @v, so long as it was not @u.
205 * Returns non-zero if @v was not @u, and zero otherwise. 205 * Returns the old value of @v.
206 */ 206 */
207static inline int atomic64_add_unless(atomic64_t *v, long a, long u) 207static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
208{ 208{
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 69d58131bc8e..1775d6e5920e 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -458,10 +458,7 @@ static inline int fls(int x)
458 458
459#include <asm-generic/bitops/le.h> 459#include <asm-generic/bitops/le.h>
460 460
461#define ext2_set_bit_atomic(lock, nr, addr) \ 461#include <asm-generic/bitops/ext2-atomic-setbit.h>
462 test_and_set_bit((nr), (unsigned long *)(addr))
463#define ext2_clear_bit_atomic(lock, nr, addr) \
464 test_and_clear_bit((nr), (unsigned long *)(addr))
465 462
466#endif /* __KERNEL__ */ 463#endif /* __KERNEL__ */
467#endif /* _ASM_X86_BITOPS_H */ 464#endif /* _ASM_X86_BITOPS_H */
diff --git a/arch/x86/include/asm/calling.h b/arch/x86/include/asm/calling.h
index 30af5a832163..a9e3a740f697 100644
--- a/arch/x86/include/asm/calling.h
+++ b/arch/x86/include/asm/calling.h
@@ -46,6 +46,7 @@ For 32-bit we have the following conventions - kernel is built with
46 46
47*/ 47*/
48 48
49#include "dwarf2.h"
49 50
50/* 51/*
51 * 64-bit system call stack frame layout defines and helpers, for 52 * 64-bit system call stack frame layout defines and helpers, for
@@ -84,72 +85,57 @@ For 32-bit we have the following conventions - kernel is built with
84#define ARGOFFSET R11 85#define ARGOFFSET R11
85#define SWFRAME ORIG_RAX 86#define SWFRAME ORIG_RAX
86 87
87 .macro SAVE_ARGS addskip=0, norcx=0, nor891011=0 88 .macro SAVE_ARGS addskip=0, save_rcx=1, save_r891011=1
88 subq $9*8+\addskip, %rsp 89 subq $9*8+\addskip, %rsp
89 CFI_ADJUST_CFA_OFFSET 9*8+\addskip 90 CFI_ADJUST_CFA_OFFSET 9*8+\addskip
90 movq %rdi, 8*8(%rsp) 91 movq_cfi rdi, 8*8
91 CFI_REL_OFFSET rdi, 8*8 92 movq_cfi rsi, 7*8
92 movq %rsi, 7*8(%rsp) 93 movq_cfi rdx, 6*8
93 CFI_REL_OFFSET rsi, 7*8 94
94 movq %rdx, 6*8(%rsp) 95 .if \save_rcx
95 CFI_REL_OFFSET rdx, 6*8 96 movq_cfi rcx, 5*8
96 .if \norcx
97 .else
98 movq %rcx, 5*8(%rsp)
99 CFI_REL_OFFSET rcx, 5*8
100 .endif 97 .endif
101 movq %rax, 4*8(%rsp) 98
102 CFI_REL_OFFSET rax, 4*8 99 movq_cfi rax, 4*8
103 .if \nor891011 100
104 .else 101 .if \save_r891011
105 movq %r8, 3*8(%rsp) 102 movq_cfi r8, 3*8
106 CFI_REL_OFFSET r8, 3*8 103 movq_cfi r9, 2*8
107 movq %r9, 2*8(%rsp) 104 movq_cfi r10, 1*8
108 CFI_REL_OFFSET r9, 2*8 105 movq_cfi r11, 0*8
109 movq %r10, 1*8(%rsp)
110 CFI_REL_OFFSET r10, 1*8
111 movq %r11, (%rsp)
112 CFI_REL_OFFSET r11, 0*8
113 .endif 106 .endif
107
114 .endm 108 .endm
115 109
116#define ARG_SKIP (9*8) 110#define ARG_SKIP (9*8)
117 111
118 .macro RESTORE_ARGS skiprax=0, addskip=0, skiprcx=0, skipr11=0, \ 112 .macro RESTORE_ARGS rstor_rax=1, addskip=0, rstor_rcx=1, rstor_r11=1, \
119 skipr8910=0, skiprdx=0 113 rstor_r8910=1, rstor_rdx=1
120 .if \skipr11 114 .if \rstor_r11
121 .else 115 movq_cfi_restore 0*8, r11
122 movq (%rsp), %r11
123 CFI_RESTORE r11
124 .endif 116 .endif
125 .if \skipr8910 117
126 .else 118 .if \rstor_r8910
127 movq 1*8(%rsp), %r10 119 movq_cfi_restore 1*8, r10
128 CFI_RESTORE r10 120 movq_cfi_restore 2*8, r9
129 movq 2*8(%rsp), %r9 121 movq_cfi_restore 3*8, r8
130 CFI_RESTORE r9
131 movq 3*8(%rsp), %r8
132 CFI_RESTORE r8
133 .endif 122 .endif
134 .if \skiprax 123
135 .else 124 .if \rstor_rax
136 movq 4*8(%rsp), %rax 125 movq_cfi_restore 4*8, rax
137 CFI_RESTORE rax
138 .endif 126 .endif
139 .if \skiprcx 127
140 .else 128 .if \rstor_rcx
141 movq 5*8(%rsp), %rcx 129 movq_cfi_restore 5*8, rcx
142 CFI_RESTORE rcx
143 .endif 130 .endif
144 .if \skiprdx 131
145 .else 132 .if \rstor_rdx
146 movq 6*8(%rsp), %rdx 133 movq_cfi_restore 6*8, rdx
147 CFI_RESTORE rdx
148 .endif 134 .endif
149 movq 7*8(%rsp), %rsi 135
150 CFI_RESTORE rsi 136 movq_cfi_restore 7*8, rsi
151 movq 8*8(%rsp), %rdi 137 movq_cfi_restore 8*8, rdi
152 CFI_RESTORE rdi 138
153 .if ARG_SKIP+\addskip > 0 139 .if ARG_SKIP+\addskip > 0
154 addq $ARG_SKIP+\addskip, %rsp 140 addq $ARG_SKIP+\addskip, %rsp
155 CFI_ADJUST_CFA_OFFSET -(ARG_SKIP+\addskip) 141 CFI_ADJUST_CFA_OFFSET -(ARG_SKIP+\addskip)
@@ -176,33 +162,21 @@ For 32-bit we have the following conventions - kernel is built with
176 .macro SAVE_REST 162 .macro SAVE_REST
177 subq $REST_SKIP, %rsp 163 subq $REST_SKIP, %rsp
178 CFI_ADJUST_CFA_OFFSET REST_SKIP 164 CFI_ADJUST_CFA_OFFSET REST_SKIP
179 movq %rbx, 5*8(%rsp) 165 movq_cfi rbx, 5*8
180 CFI_REL_OFFSET rbx, 5*8 166 movq_cfi rbp, 4*8
181 movq %rbp, 4*8(%rsp) 167 movq_cfi r12, 3*8
182 CFI_REL_OFFSET rbp, 4*8 168 movq_cfi r13, 2*8
183 movq %r12, 3*8(%rsp) 169 movq_cfi r14, 1*8
184 CFI_REL_OFFSET r12, 3*8 170 movq_cfi r15, 0*8
185 movq %r13, 2*8(%rsp)
186 CFI_REL_OFFSET r13, 2*8
187 movq %r14, 1*8(%rsp)
188 CFI_REL_OFFSET r14, 1*8
189 movq %r15, (%rsp)
190 CFI_REL_OFFSET r15, 0*8
191 .endm 171 .endm
192 172
193 .macro RESTORE_REST 173 .macro RESTORE_REST
194 movq (%rsp), %r15 174 movq_cfi_restore 0*8, r15
195 CFI_RESTORE r15 175 movq_cfi_restore 1*8, r14
196 movq 1*8(%rsp), %r14 176 movq_cfi_restore 2*8, r13
197 CFI_RESTORE r14 177 movq_cfi_restore 3*8, r12
198 movq 2*8(%rsp), %r13 178 movq_cfi_restore 4*8, rbp
199 CFI_RESTORE r13 179 movq_cfi_restore 5*8, rbx
200 movq 3*8(%rsp), %r12
201 CFI_RESTORE r12
202 movq 4*8(%rsp), %rbp
203 CFI_RESTORE rbp
204 movq 5*8(%rsp), %rbx
205 CFI_RESTORE rbx
206 addq $REST_SKIP, %rsp 180 addq $REST_SKIP, %rsp
207 CFI_ADJUST_CFA_OFFSET -(REST_SKIP) 181 CFI_ADJUST_CFA_OFFSET -(REST_SKIP)
208 .endm 182 .endm
@@ -214,7 +188,7 @@ For 32-bit we have the following conventions - kernel is built with
214 188
215 .macro RESTORE_ALL addskip=0 189 .macro RESTORE_ALL addskip=0
216 RESTORE_REST 190 RESTORE_REST
217 RESTORE_ARGS 0, \addskip 191 RESTORE_ARGS 1, \addskip
218 .endm 192 .endm
219 193
220 .macro icebp 194 .macro icebp
diff --git a/arch/x86/include/asm/clocksource.h b/arch/x86/include/asm/clocksource.h
new file mode 100644
index 000000000000..0bdbbb3b9ce7
--- /dev/null
+++ b/arch/x86/include/asm/clocksource.h
@@ -0,0 +1,18 @@
1/* x86-specific clocksource additions */
2
3#ifndef _ASM_X86_CLOCKSOURCE_H
4#define _ASM_X86_CLOCKSOURCE_H
5
6#ifdef CONFIG_X86_64
7
8#define VCLOCK_NONE 0 /* No vDSO clock available. */
9#define VCLOCK_TSC 1 /* vDSO should use vread_tsc. */
10#define VCLOCK_HPET 2 /* vDSO should use vread_hpet. */
11
12struct arch_clocksource_data {
13 int vclock_mode;
14};
15
16#endif /* CONFIG_X86_64 */
17
18#endif /* _ASM_X86_CLOCKSOURCE_H */
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 284a6e8f7ce1..3deb7250624c 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -280,4 +280,52 @@ static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
280 280
281#endif 281#endif
282 282
283#define cmpxchg8b(ptr, o1, o2, n1, n2) \
284({ \
285 char __ret; \
286 __typeof__(o2) __dummy; \
287 __typeof__(*(ptr)) __old1 = (o1); \
288 __typeof__(o2) __old2 = (o2); \
289 __typeof__(*(ptr)) __new1 = (n1); \
290 __typeof__(o2) __new2 = (n2); \
291 asm volatile(LOCK_PREFIX "cmpxchg8b %2; setz %1" \
292 : "=d"(__dummy), "=a" (__ret), "+m" (*ptr)\
293 : "a" (__old1), "d"(__old2), \
294 "b" (__new1), "c" (__new2) \
295 : "memory"); \
296 __ret; })
297
298
299#define cmpxchg8b_local(ptr, o1, o2, n1, n2) \
300({ \
301 char __ret; \
302 __typeof__(o2) __dummy; \
303 __typeof__(*(ptr)) __old1 = (o1); \
304 __typeof__(o2) __old2 = (o2); \
305 __typeof__(*(ptr)) __new1 = (n1); \
306 __typeof__(o2) __new2 = (n2); \
307 asm volatile("cmpxchg8b %2; setz %1" \
308 : "=d"(__dummy), "=a"(__ret), "+m" (*ptr)\
309 : "a" (__old), "d"(__old2), \
310 "b" (__new1), "c" (__new2), \
311 : "memory"); \
312 __ret; })
313
314
315#define cmpxchg_double(ptr, o1, o2, n1, n2) \
316({ \
317 BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
318 VM_BUG_ON((unsigned long)(ptr) % 8); \
319 cmpxchg8b((ptr), (o1), (o2), (n1), (n2)); \
320})
321
322#define cmpxchg_double_local(ptr, o1, o2, n1, n2) \
323({ \
324 BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
325 VM_BUG_ON((unsigned long)(ptr) % 8); \
326 cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2)); \
327})
328
329#define system_has_cmpxchg_double() cpu_has_cx8
330
283#endif /* _ASM_X86_CMPXCHG_32_H */ 331#endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 423ae58aa020..7cf5c0a24434 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -151,4 +151,49 @@ extern void __cmpxchg_wrong_size(void);
151 cmpxchg_local((ptr), (o), (n)); \ 151 cmpxchg_local((ptr), (o), (n)); \
152}) 152})
153 153
154#define cmpxchg16b(ptr, o1, o2, n1, n2) \
155({ \
156 char __ret; \
157 __typeof__(o2) __junk; \
158 __typeof__(*(ptr)) __old1 = (o1); \
159 __typeof__(o2) __old2 = (o2); \
160 __typeof__(*(ptr)) __new1 = (n1); \
161 __typeof__(o2) __new2 = (n2); \
162 asm volatile(LOCK_PREFIX "cmpxchg16b %2;setz %1" \
163 : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
164 : "b"(__new1), "c"(__new2), \
165 "a"(__old1), "d"(__old2)); \
166 __ret; })
167
168
169#define cmpxchg16b_local(ptr, o1, o2, n1, n2) \
170({ \
171 char __ret; \
172 __typeof__(o2) __junk; \
173 __typeof__(*(ptr)) __old1 = (o1); \
174 __typeof__(o2) __old2 = (o2); \
175 __typeof__(*(ptr)) __new1 = (n1); \
176 __typeof__(o2) __new2 = (n2); \
177 asm volatile("cmpxchg16b %2;setz %1" \
178 : "=d"(__junk), "=a"(__ret), "+m" (*ptr) \
179 : "b"(__new1), "c"(__new2), \
180 "a"(__old1), "d"(__old2)); \
181 __ret; })
182
183#define cmpxchg_double(ptr, o1, o2, n1, n2) \
184({ \
185 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
186 VM_BUG_ON((unsigned long)(ptr) % 16); \
187 cmpxchg16b((ptr), (o1), (o2), (n1), (n2)); \
188})
189
190#define cmpxchg_double_local(ptr, o1, o2, n1, n2) \
191({ \
192 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
193 VM_BUG_ON((unsigned long)(ptr) % 16); \
194 cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2)); \
195})
196
197#define system_has_cmpxchg_double() cpu_has_cx16
198
154#endif /* _ASM_X86_CMPXCHG_64_H */ 199#endif /* _ASM_X86_CMPXCHG_64_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 71cc3800712c..88b23a43f340 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -288,6 +288,8 @@ extern const char * const x86_power_flags[32];
288#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) 288#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
289#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) 289#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
290#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) 290#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
291#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
292#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
291 293
292#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) 294#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
293# define cpu_has_invlpg 1 295# define cpu_has_invlpg 1
@@ -330,9 +332,8 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
330 asm goto("1: jmp %l[t_no]\n" 332 asm goto("1: jmp %l[t_no]\n"
331 "2:\n" 333 "2:\n"
332 ".section .altinstructions,\"a\"\n" 334 ".section .altinstructions,\"a\"\n"
333 _ASM_ALIGN "\n" 335 " .long 1b - .\n"
334 _ASM_PTR "1b\n" 336 " .long 0\n" /* no replacement */
335 _ASM_PTR "0\n" /* no replacement */
336 " .word %P0\n" /* feature bit */ 337 " .word %P0\n" /* feature bit */
337 " .byte 2b - 1b\n" /* source len */ 338 " .byte 2b - 1b\n" /* source len */
338 " .byte 0\n" /* replacement len */ 339 " .byte 0\n" /* replacement len */
@@ -348,9 +349,8 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
348 asm volatile("1: movb $0,%0\n" 349 asm volatile("1: movb $0,%0\n"
349 "2:\n" 350 "2:\n"
350 ".section .altinstructions,\"a\"\n" 351 ".section .altinstructions,\"a\"\n"
351 _ASM_ALIGN "\n" 352 " .long 1b - .\n"
352 _ASM_PTR "1b\n" 353 " .long 3f - .\n"
353 _ASM_PTR "3f\n"
354 " .word %P1\n" /* feature bit */ 354 " .word %P1\n" /* feature bit */
355 " .byte 2b - 1b\n" /* source len */ 355 " .byte 2b - 1b\n" /* source len */
356 " .byte 4f - 3f\n" /* replacement len */ 356 " .byte 4f - 3f\n" /* replacement len */
diff --git a/arch/x86/include/asm/delay.h b/arch/x86/include/asm/delay.h
index 409a649204aa..9b3b4f2754c7 100644
--- a/arch/x86/include/asm/delay.h
+++ b/arch/x86/include/asm/delay.h
@@ -1,30 +1,7 @@
1#ifndef _ASM_X86_DELAY_H 1#ifndef _ASM_X86_DELAY_H
2#define _ASM_X86_DELAY_H 2#define _ASM_X86_DELAY_H
3 3
4/* 4#include <asm-generic/delay.h>
5 * Copyright (C) 1993 Linus Torvalds
6 *
7 * Delay routines calling functions in arch/x86/lib/delay.c
8 */
9
10/* Undefined functions to get compile-time errors */
11extern void __bad_udelay(void);
12extern void __bad_ndelay(void);
13
14extern void __udelay(unsigned long usecs);
15extern void __ndelay(unsigned long nsecs);
16extern void __const_udelay(unsigned long xloops);
17extern void __delay(unsigned long loops);
18
19/* 0x10c7 is 2**32 / 1000000 (rounded up) */
20#define udelay(n) (__builtin_constant_p(n) ? \
21 ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c7ul)) : \
22 __udelay(n))
23
24/* 0x5 is 2**32 / 1000000000 (rounded up) */
25#define ndelay(n) (__builtin_constant_p(n) ? \
26 ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
27 __ndelay(n))
28 5
29void use_tsc_delay(void); 6void use_tsc_delay(void);
30 7
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 7b439d9aea2a..41935fadfdfc 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -27,8 +27,8 @@ static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *in
27 27
28 desc->base2 = (info->base_addr & 0xff000000) >> 24; 28 desc->base2 = (info->base_addr & 0xff000000) >> 24;
29 /* 29 /*
30 * Don't allow setting of the lm bit. It is useless anyway 30 * Don't allow setting of the lm bit. It would confuse
31 * because 64bit system calls require __USER_CS: 31 * user_64bit_mode and would get overridden by sysret anyway.
32 */ 32 */
33 desc->l = 0; 33 desc->l = 0;
34} 34}
diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h
index 029f230ab637..63a2a03d7d51 100644
--- a/arch/x86/include/asm/device.h
+++ b/arch/x86/include/asm/device.h
@@ -8,7 +8,7 @@ struct dev_archdata {
8#ifdef CONFIG_X86_64 8#ifdef CONFIG_X86_64
9struct dma_map_ops *dma_ops; 9struct dma_map_ops *dma_ops;
10#endif 10#endif
11#if defined(CONFIG_DMAR) || defined(CONFIG_AMD_IOMMU) 11#if defined(CONFIG_INTEL_IOMMU) || defined(CONFIG_AMD_IOMMU)
12 void *iommu; /* hook for IOMMU specific extension */ 12 void *iommu; /* hook for IOMMU specific extension */
13#endif 13#endif
14}; 14};
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index d4c419f883a0..ed3065fd6314 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -2,7 +2,7 @@
2#define _ASM_X86_DMA_MAPPING_H 2#define _ASM_X86_DMA_MAPPING_H
3 3
4/* 4/*
5 * IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and 5 * IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
6 * Documentation/DMA-API.txt for documentation. 6 * Documentation/DMA-API.txt for documentation.
7 */ 7 */
8 8
diff --git a/arch/x86/include/asm/dwarf2.h b/arch/x86/include/asm/dwarf2.h
index 326099199318..f6f15986df6c 100644
--- a/arch/x86/include/asm/dwarf2.h
+++ b/arch/x86/include/asm/dwarf2.h
@@ -27,6 +27,7 @@
27#define CFI_REMEMBER_STATE .cfi_remember_state 27#define CFI_REMEMBER_STATE .cfi_remember_state
28#define CFI_RESTORE_STATE .cfi_restore_state 28#define CFI_RESTORE_STATE .cfi_restore_state
29#define CFI_UNDEFINED .cfi_undefined 29#define CFI_UNDEFINED .cfi_undefined
30#define CFI_ESCAPE .cfi_escape
30 31
31#ifdef CONFIG_AS_CFI_SIGNAL_FRAME 32#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
32#define CFI_SIGNAL_FRAME .cfi_signal_frame 33#define CFI_SIGNAL_FRAME .cfi_signal_frame
@@ -68,6 +69,7 @@
68#define CFI_REMEMBER_STATE cfi_ignore 69#define CFI_REMEMBER_STATE cfi_ignore
69#define CFI_RESTORE_STATE cfi_ignore 70#define CFI_RESTORE_STATE cfi_ignore
70#define CFI_UNDEFINED cfi_ignore 71#define CFI_UNDEFINED cfi_ignore
72#define CFI_ESCAPE cfi_ignore
71#define CFI_SIGNAL_FRAME cfi_ignore 73#define CFI_SIGNAL_FRAME cfi_ignore
72 74
73#endif 75#endif
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 1cd6d26a0a8d..0baa628e330c 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -53,8 +53,4 @@ BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
53BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR) 53BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
54#endif 54#endif
55 55
56#ifdef CONFIG_X86_MCE
57BUILD_INTERRUPT(mce_self_interrupt,MCE_SELF_VECTOR)
58#endif
59
60#endif 56#endif
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 4729b2b63117..460c74e4852c 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -78,6 +78,7 @@ enum fixed_addresses {
78 VSYSCALL_LAST_PAGE, 78 VSYSCALL_LAST_PAGE,
79 VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE 79 VSYSCALL_FIRST_PAGE = VSYSCALL_LAST_PAGE
80 + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1, 80 + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,
81 VVAR_PAGE,
81 VSYSCALL_HPET, 82 VSYSCALL_HPET,
82#endif 83#endif
83 FIX_DBGP_BASE, 84 FIX_DBGP_BASE,
diff --git a/arch/x86/include/asm/frame.h b/arch/x86/include/asm/frame.h
index 2c6fc9e62812..3b629f47eb65 100644
--- a/arch/x86/include/asm/frame.h
+++ b/arch/x86/include/asm/frame.h
@@ -1,5 +1,6 @@
1#ifdef __ASSEMBLY__ 1#ifdef __ASSEMBLY__
2 2
3#include <asm/asm.h>
3#include <asm/dwarf2.h> 4#include <asm/dwarf2.h>
4 5
5/* The annotation hides the frame from the unwinder and makes it look 6/* The annotation hides the frame from the unwinder and makes it look
@@ -7,13 +8,13 @@
7 frame pointer later */ 8 frame pointer later */
8#ifdef CONFIG_FRAME_POINTER 9#ifdef CONFIG_FRAME_POINTER
9 .macro FRAME 10 .macro FRAME
10 pushl_cfi %ebp 11 __ASM_SIZE(push,_cfi) %__ASM_REG(bp)
11 CFI_REL_OFFSET ebp,0 12 CFI_REL_OFFSET __ASM_REG(bp), 0
12 movl %esp,%ebp 13 __ASM_SIZE(mov) %__ASM_REG(sp), %__ASM_REG(bp)
13 .endm 14 .endm
14 .macro ENDFRAME 15 .macro ENDFRAME
15 popl_cfi %ebp 16 __ASM_SIZE(pop,_cfi) %__ASM_REG(bp)
16 CFI_RESTORE ebp 17 CFI_RESTORE __ASM_REG(bp)
17 .endm 18 .endm
18#else 19#else
19 .macro FRAME 20 .macro FRAME
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index bb9efe8706e2..eb92a6ed2be7 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -21,7 +21,7 @@
21#include <linux/profile.h> 21#include <linux/profile.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23 23
24#include <asm/atomic.h> 24#include <linux/atomic.h>
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <asm/sections.h> 26#include <asm/sections.h>
27 27
@@ -34,7 +34,6 @@ extern void irq_work_interrupt(void);
34extern void spurious_interrupt(void); 34extern void spurious_interrupt(void);
35extern void thermal_interrupt(void); 35extern void thermal_interrupt(void);
36extern void reschedule_interrupt(void); 36extern void reschedule_interrupt(void);
37extern void mce_self_interrupt(void);
38 37
39extern void invalidate_interrupt(void); 38extern void invalidate_interrupt(void);
40extern void invalidate_interrupt0(void); 39extern void invalidate_interrupt0(void);
@@ -120,7 +119,7 @@ struct irq_cfg {
120 cpumask_var_t old_domain; 119 cpumask_var_t old_domain;
121 u8 vector; 120 u8 vector;
122 u8 move_in_progress : 1; 121 u8 move_in_progress : 1;
123#ifdef CONFIG_INTR_REMAP 122#ifdef CONFIG_IRQ_REMAP
124 struct irq_2_iommu irq_2_iommu; 123 struct irq_2_iommu irq_2_iommu;
125#endif 124#endif
126}; 125};
diff --git a/arch/x86/include/asm/hyperv.h b/arch/x86/include/asm/hyperv.h
index 5df477ac3af7..b80420bcd09d 100644
--- a/arch/x86/include/asm/hyperv.h
+++ b/arch/x86/include/asm/hyperv.h
@@ -189,5 +189,6 @@
189#define HV_STATUS_INVALID_HYPERCALL_CODE 2 189#define HV_STATUS_INVALID_HYPERCALL_CODE 2
190#define HV_STATUS_INVALID_HYPERCALL_INPUT 3 190#define HV_STATUS_INVALID_HYPERCALL_INPUT 3
191#define HV_STATUS_INVALID_ALIGNMENT 4 191#define HV_STATUS_INVALID_ALIGNMENT 4
192#define HV_STATUS_INSUFFICIENT_BUFFERS 19
192 193
193#endif 194#endif
diff --git a/arch/x86/include/asm/i8253.h b/arch/x86/include/asm/i8253.h
deleted file mode 100644
index 65aaa91d5850..000000000000
--- a/arch/x86/include/asm/i8253.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef _ASM_X86_I8253_H
2#define _ASM_X86_I8253_H
3
4/* i8253A PIT registers */
5#define PIT_MODE 0x43
6#define PIT_CH0 0x40
7#define PIT_CH2 0x42
8
9#define PIT_LATCH LATCH
10
11extern raw_spinlock_t i8253_lock;
12
13extern struct clock_event_device *global_clock_event;
14
15extern void setup_pit_timer(void);
16
17#define inb_pit inb_p
18#define outb_pit outb_p
19
20#endif /* _ASM_X86_I8253_H */
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index d02804d650c4..d8e8eefbe24c 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -40,8 +40,6 @@
40#include <linux/compiler.h> 40#include <linux/compiler.h>
41#include <asm/page.h> 41#include <asm/page.h>
42 42
43#include <xen/xen.h>
44
45#define build_mmio_read(name, size, type, reg, barrier) \ 43#define build_mmio_read(name, size, type, reg, barrier) \
46static inline type name(const volatile void __iomem *addr) \ 44static inline type name(const volatile void __iomem *addr) \
47{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \ 45{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
@@ -334,6 +332,7 @@ extern void fixup_early_ioremap(void);
334extern bool is_early_ioremap_ptep(pte_t *ptep); 332extern bool is_early_ioremap_ptep(pte_t *ptep);
335 333
336#ifdef CONFIG_XEN 334#ifdef CONFIG_XEN
335#include <xen/xen.h>
337struct bio_vec; 336struct bio_vec;
338 337
339extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, 338extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 1c23360fb2d8..47d99934580f 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -3,7 +3,8 @@
3 3
4#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) 4#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
5 5
6#ifdef CONFIG_INTR_REMAP 6#ifdef CONFIG_IRQ_REMAP
7static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
7static inline void prepare_irte(struct irte *irte, int vector, 8static inline void prepare_irte(struct irte *irte, int vector,
8 unsigned int dest) 9 unsigned int dest)
9{ 10{
@@ -36,6 +37,9 @@ static inline bool irq_remapped(struct irq_cfg *cfg)
36{ 37{
37 return false; 38 return false;
38} 39}
40static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
41{
42}
39#endif 43#endif
40 44
41#endif /* _ASM_X86_IRQ_REMAPPING_H */ 45#endif /* _ASM_X86_IRQ_REMAPPING_H */
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 6e976ee3b3ef..4b4448761e88 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -17,7 +17,7 @@
17 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 17 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events
18 * Vectors 32 ... 127 : device interrupts 18 * Vectors 32 ... 127 : device interrupts
19 * Vector 128 : legacy int80 syscall interface 19 * Vector 128 : legacy int80 syscall interface
20 * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 : device interrupts 20 * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
21 * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts 21 * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
22 * 22 *
23 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 23 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
@@ -109,11 +109,6 @@
109 109
110#define UV_BAU_MESSAGE 0xf5 110#define UV_BAU_MESSAGE 0xf5
111 111
112/*
113 * Self IPI vector for machine checks
114 */
115#define MCE_SELF_VECTOR 0xf4
116
117/* Xen vector callback to receive events in a HVM domain */ 112/* Xen vector callback to receive events in a HVM domain */
118#define XEN_HVM_EVTCHN_CALLBACK 0xf3 113#define XEN_HVM_EVTCHN_CALLBACK 0xf3
119 114
@@ -165,19 +160,11 @@ static inline int invalid_vm86_irq(int irq)
165#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 160#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS )
166 161
167#ifdef CONFIG_X86_IO_APIC 162#ifdef CONFIG_X86_IO_APIC
168# ifdef CONFIG_SPARSE_IRQ 163# define CPU_VECTOR_LIMIT (64 * NR_CPUS)
169# define CPU_VECTOR_LIMIT (64 * NR_CPUS) 164# define NR_IRQS \
170# define NR_IRQS \
171 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 165 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
172 (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 166 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
173 (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 167 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
174# else
175# define CPU_VECTOR_LIMIT (32 * NR_CPUS)
176# define NR_IRQS \
177 (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \
178 (NR_VECTORS + CPU_VECTOR_LIMIT) : \
179 (NR_VECTORS + IO_APIC_VECTOR_LIMIT))
180# endif
181#else /* !CONFIG_X86_IO_APIC: */ 168#else /* !CONFIG_X86_IO_APIC: */
182# define NR_IRQS NR_IRQS_LEGACY 169# define NR_IRQS NR_IRQS_LEGACY
183#endif 170#endif
diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h
index 5745ce8bf108..bba3cf88e624 100644
--- a/arch/x86/include/asm/irqflags.h
+++ b/arch/x86/include/asm/irqflags.h
@@ -60,23 +60,24 @@ static inline void native_halt(void)
60#include <asm/paravirt.h> 60#include <asm/paravirt.h>
61#else 61#else
62#ifndef __ASSEMBLY__ 62#ifndef __ASSEMBLY__
63#include <linux/types.h>
63 64
64static inline unsigned long arch_local_save_flags(void) 65static inline notrace unsigned long arch_local_save_flags(void)
65{ 66{
66 return native_save_fl(); 67 return native_save_fl();
67} 68}
68 69
69static inline void arch_local_irq_restore(unsigned long flags) 70static inline notrace void arch_local_irq_restore(unsigned long flags)
70{ 71{
71 native_restore_fl(flags); 72 native_restore_fl(flags);
72} 73}
73 74
74static inline void arch_local_irq_disable(void) 75static inline notrace void arch_local_irq_disable(void)
75{ 76{
76 native_irq_disable(); 77 native_irq_disable();
77} 78}
78 79
79static inline void arch_local_irq_enable(void) 80static inline notrace void arch_local_irq_enable(void)
80{ 81{
81 native_irq_enable(); 82 native_irq_enable();
82} 83}
@@ -102,7 +103,7 @@ static inline void halt(void)
102/* 103/*
103 * For spinlocks, etc: 104 * For spinlocks, etc:
104 */ 105 */
105static inline unsigned long arch_local_irq_save(void) 106static inline notrace unsigned long arch_local_irq_save(void)
106{ 107{
107 unsigned long flags = arch_local_save_flags(); 108 unsigned long flags = arch_local_save_flags();
108 arch_local_irq_disable(); 109 arch_local_irq_disable();
diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h
index fe2cc6e105fa..d73f1571bde7 100644
--- a/arch/x86/include/asm/kdebug.h
+++ b/arch/x86/include/asm/kdebug.h
@@ -28,7 +28,6 @@ extern void show_registers(struct pt_regs *regs);
28extern void show_trace(struct task_struct *t, struct pt_regs *regs, 28extern void show_trace(struct task_struct *t, struct pt_regs *regs,
29 unsigned long *sp, unsigned long bp); 29 unsigned long *sp, unsigned long bp);
30extern void __show_regs(struct pt_regs *regs, int all); 30extern void __show_regs(struct pt_regs *regs, int all);
31extern void show_regs(struct pt_regs *regs);
32extern unsigned long oops_begin(void); 31extern unsigned long oops_begin(void);
33extern void oops_end(unsigned long, struct pt_regs *, int signr); 32extern void oops_end(unsigned long, struct pt_regs *, int signr);
34#ifdef CONFIG_KEXEC 33#ifdef CONFIG_KEXEC
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 0049211959c0..6040d115ef51 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -229,7 +229,26 @@ struct read_cache {
229 unsigned long end; 229 unsigned long end;
230}; 230};
231 231
232struct decode_cache { 232struct x86_emulate_ctxt {
233 struct x86_emulate_ops *ops;
234
235 /* Register state before/after emulation. */
236 unsigned long eflags;
237 unsigned long eip; /* eip before instruction emulation */
238 /* Emulated execution mode, represented by an X86EMUL_MODE value. */
239 int mode;
240
241 /* interruptibility state, as a result of execution of STI or MOV SS */
242 int interruptibility;
243
244 bool guest_mode; /* guest running a nested guest */
245 bool perm_ok; /* do not check permissions if true */
246 bool only_vendor_specific_insn;
247
248 bool have_exception;
249 struct x86_exception exception;
250
251 /* decode cache */
233 u8 twobyte; 252 u8 twobyte;
234 u8 b; 253 u8 b;
235 u8 intercept; 254 u8 intercept;
@@ -246,8 +265,6 @@ struct decode_cache {
246 unsigned int d; 265 unsigned int d;
247 int (*execute)(struct x86_emulate_ctxt *ctxt); 266 int (*execute)(struct x86_emulate_ctxt *ctxt);
248 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 267 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
249 unsigned long regs[NR_VCPU_REGS];
250 unsigned long eip;
251 /* modrm */ 268 /* modrm */
252 u8 modrm; 269 u8 modrm;
253 u8 modrm_mod; 270 u8 modrm_mod;
@@ -255,34 +272,14 @@ struct decode_cache {
255 u8 modrm_rm; 272 u8 modrm_rm;
256 u8 modrm_seg; 273 u8 modrm_seg;
257 bool rip_relative; 274 bool rip_relative;
275 unsigned long _eip;
276 /* Fields above regs are cleared together. */
277 unsigned long regs[NR_VCPU_REGS];
258 struct fetch_cache fetch; 278 struct fetch_cache fetch;
259 struct read_cache io_read; 279 struct read_cache io_read;
260 struct read_cache mem_read; 280 struct read_cache mem_read;
261}; 281};
262 282
263struct x86_emulate_ctxt {
264 struct x86_emulate_ops *ops;
265
266 /* Register state before/after emulation. */
267 unsigned long eflags;
268 unsigned long eip; /* eip before instruction emulation */
269 /* Emulated execution mode, represented by an X86EMUL_MODE value. */
270 int mode;
271
272 /* interruptibility state, as a result of execution of STI or MOV SS */
273 int interruptibility;
274
275 bool guest_mode; /* guest running a nested guest */
276 bool perm_ok; /* do not check permissions if true */
277 bool only_vendor_specific_insn;
278
279 bool have_exception;
280 struct x86_exception exception;
281
282 /* decode cache */
283 struct decode_cache decode;
284};
285
286/* Repeat String Operation Prefix */ 283/* Repeat String Operation Prefix */
287#define REPE_PREFIX 0xf3 284#define REPE_PREFIX 0xf3
288#define REPNE_PREFIX 0xf2 285#define REPNE_PREFIX 0xf2
@@ -373,6 +370,5 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);
373int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 370int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
374 u16 tss_selector, int reason, 371 u16 tss_selector, int reason,
375 bool has_error_code, u32 error_code); 372 bool has_error_code, u32 error_code);
376int emulate_int_real(struct x86_emulate_ctxt *ctxt, 373int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq);
377 struct x86_emulate_ops *ops, int irq);
378#endif /* _ASM_X86_KVM_X86_EMULATE_H */ 374#endif /* _ASM_X86_KVM_X86_EMULATE_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index d2ac8e2ee897..dd51c83aa5de 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -48,7 +48,7 @@
48 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 48 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
49 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 49 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
50 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ 50 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
51 | X86_CR4_OSXSAVE \ 51 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
52 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) 52 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
53 53
54#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 54#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
@@ -205,6 +205,7 @@ union kvm_mmu_page_role {
205 unsigned invalid:1; 205 unsigned invalid:1;
206 unsigned nxe:1; 206 unsigned nxe:1;
207 unsigned cr0_wp:1; 207 unsigned cr0_wp:1;
208 unsigned smep_andnot_wp:1;
208 }; 209 };
209}; 210};
210 211
@@ -227,15 +228,17 @@ struct kvm_mmu_page {
227 * in this shadow page. 228 * in this shadow page.
228 */ 229 */
229 DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS); 230 DECLARE_BITMAP(slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
230 bool multimapped; /* More than one parent_pte? */
231 bool unsync; 231 bool unsync;
232 int root_count; /* Currently serving as active root */ 232 int root_count; /* Currently serving as active root */
233 unsigned int unsync_children; 233 unsigned int unsync_children;
234 union { 234 unsigned long parent_ptes; /* Reverse mapping for parent_pte */
235 u64 *parent_pte; /* !multimapped */
236 struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
237 };
238 DECLARE_BITMAP(unsync_child_bitmap, 512); 235 DECLARE_BITMAP(unsync_child_bitmap, 512);
236
237#ifdef CONFIG_X86_32
238 int clear_spte_count;
239#endif
240
241 struct rcu_head rcu;
239}; 242};
240 243
241struct kvm_pv_mmu_op_buffer { 244struct kvm_pv_mmu_op_buffer {
@@ -269,8 +272,6 @@ struct kvm_mmu {
269 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, 272 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
270 struct x86_exception *exception); 273 struct x86_exception *exception);
271 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); 274 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access);
272 void (*prefetch_page)(struct kvm_vcpu *vcpu,
273 struct kvm_mmu_page *page);
274 int (*sync_page)(struct kvm_vcpu *vcpu, 275 int (*sync_page)(struct kvm_vcpu *vcpu,
275 struct kvm_mmu_page *sp); 276 struct kvm_mmu_page *sp);
276 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); 277 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
@@ -346,8 +347,7 @@ struct kvm_vcpu_arch {
346 * put it here to avoid allocation */ 347 * put it here to avoid allocation */
347 struct kvm_pv_mmu_op_buffer mmu_op_buffer; 348 struct kvm_pv_mmu_op_buffer mmu_op_buffer;
348 349
349 struct kvm_mmu_memory_cache mmu_pte_chain_cache; 350 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
350 struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
351 struct kvm_mmu_memory_cache mmu_page_cache; 351 struct kvm_mmu_memory_cache mmu_page_cache;
352 struct kvm_mmu_memory_cache mmu_page_header_cache; 352 struct kvm_mmu_memory_cache mmu_page_header_cache;
353 353
@@ -393,6 +393,15 @@ struct kvm_vcpu_arch {
393 unsigned int hw_tsc_khz; 393 unsigned int hw_tsc_khz;
394 unsigned int time_offset; 394 unsigned int time_offset;
395 struct page *time_page; 395 struct page *time_page;
396
397 struct {
398 u64 msr_val;
399 u64 last_steal;
400 u64 accum_steal;
401 struct gfn_to_hva_cache stime;
402 struct kvm_steal_time steal;
403 } st;
404
396 u64 last_guest_tsc; 405 u64 last_guest_tsc;
397 u64 last_kernel_ns; 406 u64 last_kernel_ns;
398 u64 last_tsc_nsec; 407 u64 last_tsc_nsec;
@@ -419,6 +428,11 @@ struct kvm_vcpu_arch {
419 u64 mcg_ctl; 428 u64 mcg_ctl;
420 u64 *mce_banks; 429 u64 *mce_banks;
421 430
431 /* Cache MMIO info */
432 u64 mmio_gva;
433 unsigned access;
434 gfn_t mmio_gfn;
435
422 /* used for guest single stepping over the given code position */ 436 /* used for guest single stepping over the given code position */
423 unsigned long singlestep_rip; 437 unsigned long singlestep_rip;
424 438
@@ -441,6 +455,7 @@ struct kvm_arch {
441 unsigned int n_used_mmu_pages; 455 unsigned int n_used_mmu_pages;
442 unsigned int n_requested_mmu_pages; 456 unsigned int n_requested_mmu_pages;
443 unsigned int n_max_mmu_pages; 457 unsigned int n_max_mmu_pages;
458 unsigned int indirect_shadow_pages;
444 atomic_t invlpg_counter; 459 atomic_t invlpg_counter;
445 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; 460 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
446 /* 461 /*
@@ -477,6 +492,8 @@ struct kvm_arch {
477 u64 hv_guest_os_id; 492 u64 hv_guest_os_id;
478 u64 hv_hypercall; 493 u64 hv_hypercall;
479 494
495 atomic_t reader_counter;
496
480 #ifdef CONFIG_KVM_MMU_AUDIT 497 #ifdef CONFIG_KVM_MMU_AUDIT
481 int audit_point; 498 int audit_point;
482 #endif 499 #endif
@@ -559,7 +576,7 @@ struct kvm_x86_ops {
559 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); 576 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
560 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); 577 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
561 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); 578 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
562 void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); 579 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
563 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); 580 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
564 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 581 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
565 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); 582 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
@@ -636,7 +653,6 @@ void kvm_mmu_module_exit(void);
636void kvm_mmu_destroy(struct kvm_vcpu *vcpu); 653void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
637int kvm_mmu_create(struct kvm_vcpu *vcpu); 654int kvm_mmu_create(struct kvm_vcpu *vcpu);
638int kvm_mmu_setup(struct kvm_vcpu *vcpu); 655int kvm_mmu_setup(struct kvm_vcpu *vcpu);
639void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte);
640void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, 656void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
641 u64 dirty_mask, u64 nx_mask, u64 x_mask); 657 u64 dirty_mask, u64 nx_mask, u64 x_mask);
642 658
@@ -830,11 +846,12 @@ enum {
830asmlinkage void kvm_spurious_fault(void); 846asmlinkage void kvm_spurious_fault(void);
831extern bool kvm_rebooting; 847extern bool kvm_rebooting;
832 848
833#define __kvm_handle_fault_on_reboot(insn) \ 849#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \
834 "666: " insn "\n\t" \ 850 "666: " insn "\n\t" \
835 "668: \n\t" \ 851 "668: \n\t" \
836 ".pushsection .fixup, \"ax\" \n" \ 852 ".pushsection .fixup, \"ax\" \n" \
837 "667: \n\t" \ 853 "667: \n\t" \
854 cleanup_insn "\n\t" \
838 "cmpb $0, kvm_rebooting \n\t" \ 855 "cmpb $0, kvm_rebooting \n\t" \
839 "jne 668b \n\t" \ 856 "jne 668b \n\t" \
840 __ASM_SIZE(push) " $666b \n\t" \ 857 __ASM_SIZE(push) " $666b \n\t" \
@@ -844,6 +861,9 @@ extern bool kvm_rebooting;
844 _ASM_PTR " 666b, 667b \n\t" \ 861 _ASM_PTR " 666b, 667b \n\t" \
845 ".popsection" 862 ".popsection"
846 863
864#define __kvm_handle_fault_on_reboot(insn) \
865 ____kvm_handle_fault_on_reboot(insn, "")
866
847#define KVM_ARCH_WANT_MMU_NOTIFIER 867#define KVM_ARCH_WANT_MMU_NOTIFIER
848int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); 868int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
849int kvm_age_hva(struct kvm *kvm, unsigned long hva); 869int kvm_age_hva(struct kvm *kvm, unsigned long hva);
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index a427bf77a93d..734c3767cfac 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -21,6 +21,7 @@
21 */ 21 */
22#define KVM_FEATURE_CLOCKSOURCE2 3 22#define KVM_FEATURE_CLOCKSOURCE2 3
23#define KVM_FEATURE_ASYNC_PF 4 23#define KVM_FEATURE_ASYNC_PF 4
24#define KVM_FEATURE_STEAL_TIME 5
24 25
25/* The last 8 bits are used to indicate how to interpret the flags field 26/* The last 8 bits are used to indicate how to interpret the flags field
26 * in pvclock structure. If no bits are set, all flags are ignored. 27 * in pvclock structure. If no bits are set, all flags are ignored.
@@ -30,10 +31,23 @@
30#define MSR_KVM_WALL_CLOCK 0x11 31#define MSR_KVM_WALL_CLOCK 0x11
31#define MSR_KVM_SYSTEM_TIME 0x12 32#define MSR_KVM_SYSTEM_TIME 0x12
32 33
34#define KVM_MSR_ENABLED 1
33/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */ 35/* Custom MSRs falls in the range 0x4b564d00-0x4b564dff */
34#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00 36#define MSR_KVM_WALL_CLOCK_NEW 0x4b564d00
35#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01 37#define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
36#define MSR_KVM_ASYNC_PF_EN 0x4b564d02 38#define MSR_KVM_ASYNC_PF_EN 0x4b564d02
39#define MSR_KVM_STEAL_TIME 0x4b564d03
40
41struct kvm_steal_time {
42 __u64 steal;
43 __u32 version;
44 __u32 flags;
45 __u32 pad[12];
46};
47
48#define KVM_STEAL_ALIGNMENT_BITS 5
49#define KVM_STEAL_VALID_BITS ((-1ULL << (KVM_STEAL_ALIGNMENT_BITS + 1)))
50#define KVM_STEAL_RESERVED_MASK (((1 << KVM_STEAL_ALIGNMENT_BITS) - 1 ) << 1)
37 51
38#define KVM_MAX_MMU_OP_BATCH 32 52#define KVM_MAX_MMU_OP_BATCH 32
39 53
@@ -178,6 +192,7 @@ void __init kvm_guest_init(void);
178void kvm_async_pf_task_wait(u32 token); 192void kvm_async_pf_task_wait(u32 token);
179void kvm_async_pf_task_wake(u32 token); 193void kvm_async_pf_task_wake(u32 token);
180u32 kvm_read_and_reset_pf_reason(void); 194u32 kvm_read_and_reset_pf_reason(void);
195extern void kvm_disable_steal_time(void);
181#else 196#else
182#define kvm_guest_init() do { } while (0) 197#define kvm_guest_init() do { } while (0)
183#define kvm_async_pf_task_wait(T) do {} while(0) 198#define kvm_async_pf_task_wait(T) do {} while(0)
@@ -186,6 +201,11 @@ static inline u32 kvm_read_and_reset_pf_reason(void)
186{ 201{
187 return 0; 202 return 0;
188} 203}
204
205static inline void kvm_disable_steal_time(void)
206{
207 return;
208}
189#endif 209#endif
190 210
191#endif /* __KERNEL__ */ 211#endif /* __KERNEL__ */
diff --git a/arch/x86/include/asm/lguest_hcall.h b/arch/x86/include/asm/lguest_hcall.h
index b60f2924c413..879fd7d33877 100644
--- a/arch/x86/include/asm/lguest_hcall.h
+++ b/arch/x86/include/asm/lguest_hcall.h
@@ -61,6 +61,7 @@ hcall(unsigned long call,
61 : "memory"); 61 : "memory");
62 return call; 62 return call;
63} 63}
64/*:*/
64 65
65/* Can't use our min() macro here: needs to be a constant */ 66/* Can't use our min() macro here: needs to be a constant */
66#define LGUEST_IRQS (NR_IRQS < 32 ? NR_IRQS: 32) 67#define LGUEST_IRQS (NR_IRQS < 32 ? NR_IRQS: 32)
diff --git a/arch/x86/include/asm/local.h b/arch/x86/include/asm/local.h
index 2e9972468a5d..9cdae5d47e8f 100644
--- a/arch/x86/include/asm/local.h
+++ b/arch/x86/include/asm/local.h
@@ -4,7 +4,7 @@
4#include <linux/percpu.h> 4#include <linux/percpu.h>
5 5
6#include <asm/system.h> 6#include <asm/system.h>
7#include <asm/atomic.h> 7#include <linux/atomic.h>
8#include <asm/asm.h> 8#include <asm/asm.h>
9 9
10typedef struct { 10typedef struct {
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 021979a6e23f..c9321f34e55b 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -8,6 +8,7 @@
8 * Machine Check support for x86 8 * Machine Check support for x86
9 */ 9 */
10 10
11/* MCG_CAP register defines */
11#define MCG_BANKCNT_MASK 0xff /* Number of Banks */ 12#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
12#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ 13#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
13#define MCG_EXT_P (1ULL<<9) /* Extended registers available */ 14#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
@@ -17,10 +18,12 @@
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 18#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ 19#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
19 20
21/* MCG_STATUS register defines */
20#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 22#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
21#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 23#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
22#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ 24#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
23 25
26/* MCi_STATUS register defines */
24#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ 27#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
25#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ 28#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
26#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ 29#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
@@ -31,12 +34,14 @@
31#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ 34#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
32#define MCI_STATUS_AR (1ULL<<55) /* Action required */ 35#define MCI_STATUS_AR (1ULL<<55) /* Action required */
33 36
34/* MISC register defines */ 37/* MCi_MISC register defines */
35#define MCM_ADDR_SEGOFF 0 /* segment offset */ 38#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
36#define MCM_ADDR_LINEAR 1 /* linear address */ 39#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
37#define MCM_ADDR_PHYS 2 /* physical address */ 40#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
38#define MCM_ADDR_MEM 3 /* memory address */ 41#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
39#define MCM_ADDR_GENERIC 7 /* generic */ 42#define MCI_MISC_ADDR_PHYS 2 /* physical address */
43#define MCI_MISC_ADDR_MEM 3 /* memory address */
44#define MCI_MISC_ADDR_GENERIC 7 /* generic */
40 45
41/* CTL2 register defines */ 46/* CTL2 register defines */
42#define MCI_CTL2_CMCI_EN (1ULL << 30) 47#define MCI_CTL2_CMCI_EN (1ULL << 30)
@@ -119,7 +124,7 @@ extern struct atomic_notifier_head x86_mce_decoder_chain;
119 124
120#include <linux/percpu.h> 125#include <linux/percpu.h>
121#include <linux/init.h> 126#include <linux/init.h>
122#include <asm/atomic.h> 127#include <linux/atomic.h>
123 128
124extern int mce_disabled; 129extern int mce_disabled;
125extern int mce_p5_enabled; 130extern int mce_p5_enabled;
@@ -144,7 +149,7 @@ static inline void enable_p5_mce(void) {}
144 149
145void mce_setup(struct mce *m); 150void mce_setup(struct mce *m);
146void mce_log(struct mce *m); 151void mce_log(struct mce *m);
147DECLARE_PER_CPU(struct sys_device, mce_dev); 152DECLARE_PER_CPU(struct sys_device, mce_sysdev);
148 153
149/* 154/*
150 * Maximum banks number. 155 * Maximum banks number.
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 8b5393ec1080..69021528b43c 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -2,7 +2,7 @@
2#define _ASM_X86_MMU_CONTEXT_H 2#define _ASM_X86_MMU_CONTEXT_H
3 3
4#include <asm/desc.h> 4#include <asm/desc.h>
5#include <asm/atomic.h> 5#include <linux/atomic.h>
6#include <asm/pgalloc.h> 6#include <asm/pgalloc.h>
7#include <asm/tlbflush.h> 7#include <asm/tlbflush.h>
8#include <asm/paravirt.h> 8#include <asm/paravirt.h>
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index ffa037f28d39..55728e121473 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -34,15 +34,15 @@ static inline void resume_map_numa_kva(pgd_t *pgd) {}
34 * 64Gb / 4096bytes/page = 16777216 pages 34 * 64Gb / 4096bytes/page = 16777216 pages
35 */ 35 */
36#define MAX_NR_PAGES 16777216 36#define MAX_NR_PAGES 16777216
37#define MAX_ELEMENTS 1024 37#define MAX_SECTIONS 1024
38#define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS) 38#define PAGES_PER_SECTION (MAX_NR_PAGES/MAX_SECTIONS)
39 39
40extern s8 physnode_map[]; 40extern s8 physnode_map[];
41 41
42static inline int pfn_to_nid(unsigned long pfn) 42static inline int pfn_to_nid(unsigned long pfn)
43{ 43{
44#ifdef CONFIG_NUMA 44#ifdef CONFIG_NUMA
45 return((int) physnode_map[(pfn) / PAGES_PER_ELEMENT]); 45 return((int) physnode_map[(pfn) / PAGES_PER_SECTION]);
46#else 46#else
47 return 0; 47 return 0;
48#endif 48#endif
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d96bdb25ca3d..d52609aeeab8 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -441,6 +441,18 @@
441#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 441#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
442#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 442#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
443#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 443#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
444#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
445#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
446#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
447#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
448
449/* VMX_BASIC bits and bitmasks */
450#define VMX_BASIC_VMCS_SIZE_SHIFT 32
451#define VMX_BASIC_64 0x0001000000000000LLU
452#define VMX_BASIC_MEM_TYPE_SHIFT 50
453#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
454#define VMX_BASIC_MEM_TYPE_WB 6LLU
455#define VMX_BASIC_INOUT 0x0040000000000000LLU
444 456
445/* AMD-V MSRs */ 457/* AMD-V MSRs */
446 458
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index 4886a68f267e..fd3f9f18cf3f 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -22,27 +22,26 @@ void arch_trigger_all_cpu_backtrace(void);
22#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace 22#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
23#endif 23#endif
24 24
25/* 25#define NMI_FLAG_FIRST 1
26 * Define some priorities for the nmi notifier call chain. 26
27 * 27enum {
28 * Create a local nmi bit that has a higher priority than 28 NMI_LOCAL=0,
29 * external nmis, because the local ones are more frequent. 29 NMI_UNKNOWN,
30 * 30 NMI_MAX
31 * Also setup some default high/normal/low settings for 31};
32 * subsystems to registers with. Using 4 bits to separate 32
33 * the priorities. This can go a lot higher if needed be. 33#define NMI_DONE 0
34 */ 34#define NMI_HANDLED 1
35 35
36#define NMI_LOCAL_SHIFT 16 /* randomly picked */ 36typedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);
37#define NMI_LOCAL_BIT (1ULL << NMI_LOCAL_SHIFT) 37
38#define NMI_HIGH_PRIOR (1ULL << 8) 38int register_nmi_handler(unsigned int, nmi_handler_t, unsigned long,
39#define NMI_NORMAL_PRIOR (1ULL << 4) 39 const char *);
40#define NMI_LOW_PRIOR (1ULL << 0) 40
41#define NMI_LOCAL_HIGH_PRIOR (NMI_LOCAL_BIT | NMI_HIGH_PRIOR) 41void unregister_nmi_handler(unsigned int, const char *);
42#define NMI_LOCAL_NORMAL_PRIOR (NMI_LOCAL_BIT | NMI_NORMAL_PRIOR)
43#define NMI_LOCAL_LOW_PRIOR (NMI_LOCAL_BIT | NMI_LOW_PRIOR)
44 42
45void stop_nmi(void); 43void stop_nmi(void);
46void restart_nmi(void); 44void restart_nmi(void);
45void local_touch_nmi(void);
47 46
48#endif /* _ASM_X86_NMI_H */ 47#endif /* _ASM_X86_NMI_H */
diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h
index 5ca6801b75f3..87bdbca72f94 100644
--- a/arch/x86/include/asm/olpc.h
+++ b/arch/x86/include/asm/olpc.h
@@ -13,6 +13,7 @@ struct olpc_platform_t {
13 13
14#define OLPC_F_PRESENT 0x01 14#define OLPC_F_PRESENT 0x01
15#define OLPC_F_DCON 0x02 15#define OLPC_F_DCON 0x02
16#define OLPC_F_EC_WIDE_SCI 0x04
16 17
17#ifdef CONFIG_OLPC 18#ifdef CONFIG_OLPC
18 19
@@ -62,6 +63,13 @@ static inline int olpc_board_at_least(uint32_t rev)
62 return olpc_platform_info.boardrev >= rev; 63 return olpc_platform_info.boardrev >= rev;
63} 64}
64 65
66extern void olpc_ec_wakeup_set(u16 value);
67extern void olpc_ec_wakeup_clear(u16 value);
68extern bool olpc_ec_wakeup_available(void);
69
70extern int olpc_ec_mask_write(u16 bits);
71extern int olpc_ec_sci_query(u16 *sci_value);
72
65#else 73#else
66 74
67static inline int machine_is_olpc(void) 75static inline int machine_is_olpc(void)
@@ -74,6 +82,20 @@ static inline int olpc_has_dcon(void)
74 return 0; 82 return 0;
75} 83}
76 84
85static inline void olpc_ec_wakeup_set(u16 value) { }
86static inline void olpc_ec_wakeup_clear(u16 value) { }
87
88static inline bool olpc_ec_wakeup_available(void)
89{
90 return false;
91}
92
93#endif
94
95#ifdef CONFIG_OLPC_XO1_PM
96extern void do_olpc_suspend_lowlevel(void);
97extern void olpc_xo1_pm_wakeup_set(u16 value);
98extern void olpc_xo1_pm_wakeup_clear(u16 value);
77#endif 99#endif
78 100
79extern int pci_olpc_init(void); 101extern int pci_olpc_init(void);
@@ -83,14 +105,19 @@ extern int pci_olpc_init(void);
83extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, 105extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
84 unsigned char *outbuf, size_t outlen); 106 unsigned char *outbuf, size_t outlen);
85 107
86extern int olpc_ec_mask_set(uint8_t bits);
87extern int olpc_ec_mask_unset(uint8_t bits);
88
89/* EC commands */ 108/* EC commands */
90 109
91#define EC_FIRMWARE_REV 0x08 110#define EC_FIRMWARE_REV 0x08
92#define EC_WLAN_ENTER_RESET 0x35 111#define EC_WRITE_SCI_MASK 0x1b
93#define EC_WLAN_LEAVE_RESET 0x25 112#define EC_WAKE_UP_WLAN 0x24
113#define EC_WLAN_LEAVE_RESET 0x25
114#define EC_READ_EB_MODE 0x2a
115#define EC_SET_SCI_INHIBIT 0x32
116#define EC_SET_SCI_INHIBIT_RELEASE 0x34
117#define EC_WLAN_ENTER_RESET 0x35
118#define EC_WRITE_EXT_SCI_MASK 0x38
119#define EC_SCI_QUERY 0x84
120#define EC_EXT_SCI_QUERY 0x85
94 121
95/* SCI source values */ 122/* SCI source values */
96 123
@@ -99,10 +126,12 @@ extern int olpc_ec_mask_unset(uint8_t bits);
99#define EC_SCI_SRC_BATTERY 0x02 126#define EC_SCI_SRC_BATTERY 0x02
100#define EC_SCI_SRC_BATSOC 0x04 127#define EC_SCI_SRC_BATSOC 0x04
101#define EC_SCI_SRC_BATERR 0x08 128#define EC_SCI_SRC_BATERR 0x08
102#define EC_SCI_SRC_EBOOK 0x10 129#define EC_SCI_SRC_EBOOK 0x10 /* XO-1 only */
103#define EC_SCI_SRC_WLAN 0x20 130#define EC_SCI_SRC_WLAN 0x20 /* XO-1 only */
104#define EC_SCI_SRC_ACPWR 0x40 131#define EC_SCI_SRC_ACPWR 0x40
105#define EC_SCI_SRC_ALL 0x7F 132#define EC_SCI_SRC_BATCRIT 0x80
133#define EC_SCI_SRC_GPWAKE 0x100 /* XO-1.5 only */
134#define EC_SCI_SRC_ALL 0x1FF
106 135
107/* GPIO assignments */ 136/* GPIO assignments */
108 137
@@ -116,7 +145,7 @@ extern int olpc_ec_mask_unset(uint8_t bits);
116#define OLPC_GPIO_SMB_CLK 14 145#define OLPC_GPIO_SMB_CLK 14
117#define OLPC_GPIO_SMB_DATA 15 146#define OLPC_GPIO_SMB_DATA 15
118#define OLPC_GPIO_WORKAUX geode_gpio(24) 147#define OLPC_GPIO_WORKAUX geode_gpio(24)
119#define OLPC_GPIO_LID geode_gpio(26) 148#define OLPC_GPIO_LID 26
120#define OLPC_GPIO_ECSCI geode_gpio(27) 149#define OLPC_GPIO_ECSCI 27
121 150
122#endif /* _ASM_X86_OLPC_H */ 151#endif /* _ASM_X86_OLPC_H */
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index ebbc4d8ab170..a7d2db9a74fb 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -230,6 +230,15 @@ static inline unsigned long long paravirt_sched_clock(void)
230 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); 230 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
231} 231}
232 232
233struct jump_label_key;
234extern struct jump_label_key paravirt_steal_enabled;
235extern struct jump_label_key paravirt_steal_rq_enabled;
236
237static inline u64 paravirt_steal_clock(int cpu)
238{
239 return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu);
240}
241
233static inline unsigned long long paravirt_read_pmc(int counter) 242static inline unsigned long long paravirt_read_pmc(int counter)
234{ 243{
235 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); 244 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 82885099c869..8e8b9a4987ee 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -41,6 +41,7 @@
41 41
42#include <asm/desc_defs.h> 42#include <asm/desc_defs.h>
43#include <asm/kmap_types.h> 43#include <asm/kmap_types.h>
44#include <asm/pgtable_types.h>
44 45
45struct page; 46struct page;
46struct thread_struct; 47struct thread_struct;
@@ -63,6 +64,11 @@ struct paravirt_callee_save {
63struct pv_info { 64struct pv_info {
64 unsigned int kernel_rpl; 65 unsigned int kernel_rpl;
65 int shared_kernel_pmd; 66 int shared_kernel_pmd;
67
68#ifdef CONFIG_X86_64
69 u16 extra_user_64bit_cs; /* __USER_CS if none */
70#endif
71
66 int paravirt_enabled; 72 int paravirt_enabled;
67 const char *name; 73 const char *name;
68}; 74};
@@ -89,6 +95,7 @@ struct pv_lazy_ops {
89 95
90struct pv_time_ops { 96struct pv_time_ops {
91 unsigned long long (*sched_clock)(void); 97 unsigned long long (*sched_clock)(void);
98 unsigned long long (*steal_clock)(int cpu);
92 unsigned long (*get_tsc_khz)(void); 99 unsigned long (*get_tsc_khz)(void);
93}; 100};
94 101
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index a0a9779084d1..3470c9d0ebba 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -388,12 +388,9 @@ do { \
388#define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 388#define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val)
389#define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 389#define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val)
390#define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 390#define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val)
391/* 391#define __this_cpu_xchg_1(pcp, val) percpu_xchg_op(pcp, val)
392 * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much 392#define __this_cpu_xchg_2(pcp, val) percpu_xchg_op(pcp, val)
393 * faster than an xchg with forced lock semantics. 393#define __this_cpu_xchg_4(pcp, val) percpu_xchg_op(pcp, val)
394 */
395#define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
396#define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
397 394
398#define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 395#define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
399#define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 396#define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
@@ -485,6 +482,8 @@ do { \
485#define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 482#define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val)
486#define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 483#define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val)
487#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 484#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
485#define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval)
486#define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval)
488 487
489#define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 488#define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp))
490#define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 489#define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index d9d4dae305f6..f61c62f7d5d8 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,6 +29,9 @@
29#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) 29#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
30#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL 30#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
31 31
32#define AMD_PERFMON_EVENTSEL_GUESTONLY (1ULL << 40)
33#define AMD_PERFMON_EVENTSEL_HOSTONLY (1ULL << 41)
34
32#define AMD64_EVENTSEL_EVENT \ 35#define AMD64_EVENTSEL_EVENT \
33 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) 36 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
34#define INTEL_ARCH_EVENT_MASK \ 37#define INTEL_ARCH_EVENT_MASK \
@@ -43,14 +46,17 @@
43#define AMD64_RAW_EVENT_MASK \ 46#define AMD64_RAW_EVENT_MASK \
44 (X86_RAW_EVENT_MASK | \ 47 (X86_RAW_EVENT_MASK | \
45 AMD64_EVENTSEL_EVENT) 48 AMD64_EVENTSEL_EVENT)
49#define AMD64_NUM_COUNTERS 4
50#define AMD64_NUM_COUNTERS_F15H 6
51#define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H
46 52
47#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c 53#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
48#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) 54#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
49#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 55#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
50#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ 56#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
51 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) 57 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
52 58
53#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 59#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
54 60
55/* 61/*
56 * Intel "Architectural Performance Monitoring" CPUID 62 * Intel "Architectural Performance Monitoring" CPUID
@@ -110,6 +116,35 @@ union cpuid10_edx {
110 */ 116 */
111#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) 117#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
112 118
119/*
120 * IBS cpuid feature detection
121 */
122
123#define IBS_CPUID_FEATURES 0x8000001b
124
125/*
126 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
127 * bit 0 is used to indicate the existence of IBS.
128 */
129#define IBS_CAPS_AVAIL (1U<<0)
130#define IBS_CAPS_FETCHSAM (1U<<1)
131#define IBS_CAPS_OPSAM (1U<<2)
132#define IBS_CAPS_RDWROPCNT (1U<<3)
133#define IBS_CAPS_OPCNT (1U<<4)
134#define IBS_CAPS_BRNTRGT (1U<<5)
135#define IBS_CAPS_OPCNTEXT (1U<<6)
136
137#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
138 | IBS_CAPS_FETCHSAM \
139 | IBS_CAPS_OPSAM)
140
141/*
142 * IBS APIC setup
143 */
144#define IBSCTL 0x1cc
145#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
146#define IBSCTL_LVT_OFFSET_MASK 0x0F
147
113/* IbsFetchCtl bits/masks */ 148/* IbsFetchCtl bits/masks */
114#define IBS_FETCH_RAND_EN (1ULL<<57) 149#define IBS_FETCH_RAND_EN (1ULL<<57)
115#define IBS_FETCH_VAL (1ULL<<49) 150#define IBS_FETCH_VAL (1ULL<<49)
@@ -124,6 +159,8 @@ union cpuid10_edx {
124#define IBS_OP_MAX_CNT 0x0000FFFFULL 159#define IBS_OP_MAX_CNT 0x0000FFFFULL
125#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ 160#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
126 161
162extern u32 get_ibs_caps(void);
163
127#ifdef CONFIG_PERF_EVENTS 164#ifdef CONFIG_PERF_EVENTS
128extern void perf_events_lapic_init(void); 165extern void perf_events_lapic_init(void);
129 166
@@ -152,9 +189,26 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
152 (regs)->bp = caller_frame_pointer(); \ 189 (regs)->bp = caller_frame_pointer(); \
153 (regs)->cs = __KERNEL_CS; \ 190 (regs)->cs = __KERNEL_CS; \
154 regs->flags = 0; \ 191 regs->flags = 0; \
192 asm volatile( \
193 _ASM_MOV "%%"_ASM_SP ", %0\n" \
194 : "=m" ((regs)->sp) \
195 :: "memory" \
196 ); \
155} 197}
156 198
199struct perf_guest_switch_msr {
200 unsigned msr;
201 u64 host, guest;
202};
203
204extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
157#else 205#else
206static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
207{
208 *nr = 0;
209 return NULL;
210}
211
158static inline void perf_events_lapic_init(void) { } 212static inline void perf_events_lapic_init(void) { }
159#endif 213#endif
160 214
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 56fd9e3abbda..4f7e67e2345e 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -102,6 +102,14 @@
102#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 102#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
103 103
104/* 104/*
105 * If an event has alias it should be marked
106 * with a special bit. (Don't forget to check
107 * P4_PEBS_CONFIG_MASK and related bits on
108 * modification.)
109 */
110#define P4_CONFIG_ALIASABLE (1 << 9)
111
112/*
105 * The bits we allow to pass for RAW events 113 * The bits we allow to pass for RAW events
106 */ 114 */
107#define P4_CONFIG_MASK_ESCR \ 115#define P4_CONFIG_MASK_ESCR \
@@ -123,6 +131,31 @@
123 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \ 131 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \
124 (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR)) 132 (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
125 133
134/*
135 * In case of event aliasing we need to preserve some
136 * caller bits, otherwise the mapping won't be complete.
137 */
138#define P4_CONFIG_EVENT_ALIAS_MASK \
139 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR) | \
140 p4_config_pack_cccr(P4_CCCR_EDGE | \
141 P4_CCCR_THRESHOLD_MASK | \
142 P4_CCCR_COMPLEMENT | \
143 P4_CCCR_COMPARE))
144
145#define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS \
146 ((P4_CONFIG_HT) | \
147 p4_config_pack_escr(P4_ESCR_T0_OS | \
148 P4_ESCR_T0_USR | \
149 P4_ESCR_T1_OS | \
150 P4_ESCR_T1_USR) | \
151 p4_config_pack_cccr(P4_CCCR_OVF | \
152 P4_CCCR_CASCADE | \
153 P4_CCCR_FORCE_OVF | \
154 P4_CCCR_THREAD_ANY | \
155 P4_CCCR_OVF_PMI_T0 | \
156 P4_CCCR_OVF_PMI_T1 | \
157 P4_CONFIG_ALIASABLE))
158
126static inline bool p4_is_event_cascaded(u64 config) 159static inline bool p4_is_event_cascaded(u64 config)
127{ 160{
128 u32 cccr = p4_config_unpack_cccr(config); 161 u32 cccr = p4_config_unpack_cccr(config);
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index d56187c6b838..013286a10c2c 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -107,7 +107,8 @@
107#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT) 107#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD | _PAGE_PWT)
108#define __PAGE_KERNEL_UC_MINUS (__PAGE_KERNEL | _PAGE_PCD) 108#define __PAGE_KERNEL_UC_MINUS (__PAGE_KERNEL | _PAGE_PCD)
109#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER) 109#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
110#define __PAGE_KERNEL_VSYSCALL_NOCACHE (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT) 110#define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO | _PAGE_USER)
111#define __PAGE_KERNEL_VVAR_NOCACHE (__PAGE_KERNEL_VVAR | _PAGE_PCD | _PAGE_PWT)
111#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) 112#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
112#define __PAGE_KERNEL_LARGE_NOCACHE (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE) 113#define __PAGE_KERNEL_LARGE_NOCACHE (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
113#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) 114#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
@@ -129,7 +130,8 @@
129#define PAGE_KERNEL_LARGE_NOCACHE __pgprot(__PAGE_KERNEL_LARGE_NOCACHE) 130#define PAGE_KERNEL_LARGE_NOCACHE __pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
130#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC) 131#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
131#define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL) 132#define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL)
132#define PAGE_KERNEL_VSYSCALL_NOCACHE __pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE) 133#define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR)
134#define PAGE_KERNEL_VVAR_NOCACHE __pgprot(__PAGE_KERNEL_VVAR_NOCACHE)
133 135
134#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO) 136#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
135#define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE) 137#define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE)
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index 59ab4dffa377..2dddb317bb39 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -59,6 +59,7 @@
59#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 59#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
60#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 60#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
61#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ 61#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
62#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
62#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 63#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
63#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */ 64#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */
64 65
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 219371546afd..0d1171c97729 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -751,8 +751,6 @@ static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
751 :: "a" (eax), "c" (ecx)); 751 :: "a" (eax), "c" (ecx));
752} 752}
753 753
754extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
755
756extern void select_idle_routine(const struct cpuinfo_x86 *c); 754extern void select_idle_routine(const struct cpuinfo_x86 *c);
757extern void init_amd_e400_c1e_mask(void); 755extern void init_amd_e400_c1e_mask(void);
758 756
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index 971e0b46446e..644dd885f05a 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -19,7 +19,7 @@
19#include <linux/pci.h> 19#include <linux/pci.h>
20 20
21#include <asm/irq.h> 21#include <asm/irq.h>
22#include <asm/atomic.h> 22#include <linux/atomic.h>
23#include <asm/setup.h> 23#include <asm/setup.h>
24#include <asm/irq_controller.h> 24#include <asm/irq_controller.h>
25 25
@@ -30,17 +30,6 @@ extern void add_dtb(u64 data);
30extern void x86_add_irq_domains(void); 30extern void x86_add_irq_domains(void);
31void __cpuinit x86_of_pci_init(void); 31void __cpuinit x86_of_pci_init(void);
32void x86_dtb_init(void); 32void x86_dtb_init(void);
33
34static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
35{
36 return pdev ? pdev->dev.of_node : NULL;
37}
38
39static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
40{
41 return pci_device_to_OF_node(bus->self);
42}
43
44#else 33#else
45static inline void add_dtb(u64 data) { } 34static inline void add_dtb(u64 data) { }
46static inline void x86_add_irq_domains(void) { } 35static inline void x86_add_irq_domains(void) { }
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 94e7618fcac8..35664547125b 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -131,6 +131,9 @@ struct pt_regs {
131#ifdef __KERNEL__ 131#ifdef __KERNEL__
132 132
133#include <linux/init.h> 133#include <linux/init.h>
134#ifdef CONFIG_PARAVIRT
135#include <asm/paravirt_types.h>
136#endif
134 137
135struct cpuinfo_x86; 138struct cpuinfo_x86;
136struct task_struct; 139struct task_struct;
@@ -187,6 +190,22 @@ static inline int v8086_mode(struct pt_regs *regs)
187#endif 190#endif
188} 191}
189 192
193#ifdef CONFIG_X86_64
194static inline bool user_64bit_mode(struct pt_regs *regs)
195{
196#ifndef CONFIG_PARAVIRT
197 /*
198 * On non-paravirt systems, this is the only long mode CPL 3
199 * selector. We do not allow long mode selectors in the LDT.
200 */
201 return regs->cs == __USER_CS;
202#else
203 /* Headers are too twisted for this to go in paravirt.h. */
204 return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs;
205#endif
206}
207#endif
208
190/* 209/*
191 * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode 210 * X86_32 CPUs don't save ss and esp if the CPU is already in kernel mode
192 * when it traps. The previous stack will be directly underneath the saved 211 * when it traps. The previous stack will be directly underneath the saved
diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h
index a518c0a45044..c59cc97fe6c1 100644
--- a/arch/x86/include/asm/pvclock.h
+++ b/arch/x86/include/asm/pvclock.h
@@ -44,7 +44,7 @@ static inline u64 pvclock_scale_delta(u64 delta, u32 mul_frac, int shift)
44 : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) ); 44 : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
45#elif defined(__x86_64__) 45#elif defined(__x86_64__)
46 __asm__ ( 46 __asm__ (
47 "mul %[mul_frac] ; shrd $32, %[hi], %[lo]" 47 "mulq %[mul_frac] ; shrd $32, %[hi], %[lo]"
48 : [lo]"=a"(product), 48 : [lo]"=a"(product),
49 [hi]"=d"(tmp) 49 [hi]"=d"(tmp)
50 : "0"(delta), 50 : "0"(delta),
diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h
index 3250e3d605d9..92f297069e87 100644
--- a/arch/x86/include/asm/reboot.h
+++ b/arch/x86/include/asm/reboot.h
@@ -23,7 +23,7 @@ void machine_real_restart(unsigned int type);
23#define MRR_BIOS 0 23#define MRR_BIOS 0
24#define MRR_APM 1 24#define MRR_APM 1
25 25
26typedef void (*nmi_shootdown_cb)(int, struct die_args*); 26typedef void (*nmi_shootdown_cb)(int, struct pt_regs*);
27void nmi_shootdown_cpus(nmi_shootdown_cb callback); 27void nmi_shootdown_cpus(nmi_shootdown_cb callback);
28 28
29#endif /* _ASM_X86_REBOOT_H */ 29#endif /* _ASM_X86_REBOOT_H */
diff --git a/arch/x86/include/asm/rwlock.h b/arch/x86/include/asm/rwlock.h
index 6a8c0d645108..a5370a03d90c 100644
--- a/arch/x86/include/asm/rwlock.h
+++ b/arch/x86/include/asm/rwlock.h
@@ -1,7 +1,48 @@
1#ifndef _ASM_X86_RWLOCK_H 1#ifndef _ASM_X86_RWLOCK_H
2#define _ASM_X86_RWLOCK_H 2#define _ASM_X86_RWLOCK_H
3 3
4#define RW_LOCK_BIAS 0x01000000 4#include <asm/asm.h>
5
6#if CONFIG_NR_CPUS <= 2048
7
8#ifndef __ASSEMBLY__
9typedef union {
10 s32 lock;
11 s32 write;
12} arch_rwlock_t;
13#endif
14
15#define RW_LOCK_BIAS 0x00100000
16#define READ_LOCK_SIZE(insn) __ASM_FORM(insn##l)
17#define READ_LOCK_ATOMIC(n) atomic_##n
18#define WRITE_LOCK_ADD(n) __ASM_FORM_COMMA(addl n)
19#define WRITE_LOCK_SUB(n) __ASM_FORM_COMMA(subl n)
20#define WRITE_LOCK_CMP RW_LOCK_BIAS
21
22#else /* CONFIG_NR_CPUS > 2048 */
23
24#include <linux/const.h>
25
26#ifndef __ASSEMBLY__
27typedef union {
28 s64 lock;
29 struct {
30 u32 read;
31 s32 write;
32 };
33} arch_rwlock_t;
34#endif
35
36#define RW_LOCK_BIAS (_AC(1,L) << 32)
37#define READ_LOCK_SIZE(insn) __ASM_FORM(insn##q)
38#define READ_LOCK_ATOMIC(n) atomic64_##n
39#define WRITE_LOCK_ADD(n) __ASM_FORM(incl)
40#define WRITE_LOCK_SUB(n) __ASM_FORM(decl)
41#define WRITE_LOCK_CMP 1
42
43#endif /* CONFIG_NR_CPUS */
44
45#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
5 46
6/* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */ 47/* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */
7 48
diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h
index cd84f7208f76..5e641715c3fe 100644
--- a/arch/x86/include/asm/segment.h
+++ b/arch/x86/include/asm/segment.h
@@ -162,7 +162,7 @@
162#define GDT_ENTRY_DEFAULT_USER32_CS 4 162#define GDT_ENTRY_DEFAULT_USER32_CS 4
163#define GDT_ENTRY_DEFAULT_USER_DS 5 163#define GDT_ENTRY_DEFAULT_USER_DS 5
164#define GDT_ENTRY_DEFAULT_USER_CS 6 164#define GDT_ENTRY_DEFAULT_USER_CS 6
165#define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS * 8 + 3) 165#define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS*8+3)
166#define __USER32_DS __USER_DS 166#define __USER32_DS __USER_DS
167 167
168#define GDT_ENTRY_TSS 8 /* needs two entries */ 168#define GDT_ENTRY_TSS 8 /* needs two entries */
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 725b77831993..49adfd7bb4a4 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -10,7 +10,11 @@ static inline void smpboot_clear_io_apic_irqs(void)
10 10
11static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 11static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
12{ 12{
13 unsigned long flags;
14
15 spin_lock_irqsave(&rtc_lock, flags);
13 CMOS_WRITE(0xa, 0xf); 16 CMOS_WRITE(0xa, 0xf);
17 spin_unlock_irqrestore(&rtc_lock, flags);
14 local_flush_tlb(); 18 local_flush_tlb();
15 pr_debug("1.\n"); 19 pr_debug("1.\n");
16 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) = 20 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) =
@@ -23,6 +27,8 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
23 27
24static inline void smpboot_restore_warm_reset_vector(void) 28static inline void smpboot_restore_warm_reset_vector(void)
25{ 29{
30 unsigned long flags;
31
26 /* 32 /*
27 * Install writable page 0 entry to set BIOS data area. 33 * Install writable page 0 entry to set BIOS data area.
28 */ 34 */
@@ -32,7 +38,9 @@ static inline void smpboot_restore_warm_reset_vector(void)
32 * Paranoid: Set warm reset code and vector here back 38 * Paranoid: Set warm reset code and vector here back
33 * to default values. 39 * to default values.
34 */ 40 */
41 spin_lock_irqsave(&rtc_lock, flags);
35 CMOS_WRITE(0, 0xf); 42 CMOS_WRITE(0, 0xf);
43 spin_unlock_irqrestore(&rtc_lock, flags);
36 44
37 *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0; 45 *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0;
38} 46}
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index 3089f70c0c52..ee67edf86fdd 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -1,8 +1,7 @@
1#ifndef _ASM_X86_SPINLOCK_H 1#ifndef _ASM_X86_SPINLOCK_H
2#define _ASM_X86_SPINLOCK_H 2#define _ASM_X86_SPINLOCK_H
3 3
4#include <asm/atomic.h> 4#include <linux/atomic.h>
5#include <asm/rwlock.h>
6#include <asm/page.h> 5#include <asm/page.h>
7#include <asm/processor.h> 6#include <asm/processor.h>
8#include <linux/compiler.h> 7#include <linux/compiler.h>
@@ -234,7 +233,7 @@ static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
234 */ 233 */
235static inline int arch_read_can_lock(arch_rwlock_t *lock) 234static inline int arch_read_can_lock(arch_rwlock_t *lock)
236{ 235{
237 return (int)(lock)->lock > 0; 236 return lock->lock > 0;
238} 237}
239 238
240/** 239/**
@@ -243,12 +242,12 @@ static inline int arch_read_can_lock(arch_rwlock_t *lock)
243 */ 242 */
244static inline int arch_write_can_lock(arch_rwlock_t *lock) 243static inline int arch_write_can_lock(arch_rwlock_t *lock)
245{ 244{
246 return (lock)->lock == RW_LOCK_BIAS; 245 return lock->write == WRITE_LOCK_CMP;
247} 246}
248 247
249static inline void arch_read_lock(arch_rwlock_t *rw) 248static inline void arch_read_lock(arch_rwlock_t *rw)
250{ 249{
251 asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t" 250 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t"
252 "jns 1f\n" 251 "jns 1f\n"
253 "call __read_lock_failed\n\t" 252 "call __read_lock_failed\n\t"
254 "1:\n" 253 "1:\n"
@@ -257,47 +256,55 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
257 256
258static inline void arch_write_lock(arch_rwlock_t *rw) 257static inline void arch_write_lock(arch_rwlock_t *rw)
259{ 258{
260 asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t" 259 asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t"
261 "jz 1f\n" 260 "jz 1f\n"
262 "call __write_lock_failed\n\t" 261 "call __write_lock_failed\n\t"
263 "1:\n" 262 "1:\n"
264 ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory"); 263 ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS)
264 : "memory");
265} 265}
266 266
267static inline int arch_read_trylock(arch_rwlock_t *lock) 267static inline int arch_read_trylock(arch_rwlock_t *lock)
268{ 268{
269 atomic_t *count = (atomic_t *)lock; 269 READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock;
270 270
271 if (atomic_dec_return(count) >= 0) 271 if (READ_LOCK_ATOMIC(dec_return)(count) >= 0)
272 return 1; 272 return 1;
273 atomic_inc(count); 273 READ_LOCK_ATOMIC(inc)(count);
274 return 0; 274 return 0;
275} 275}
276 276
277static inline int arch_write_trylock(arch_rwlock_t *lock) 277static inline int arch_write_trylock(arch_rwlock_t *lock)
278{ 278{
279 atomic_t *count = (atomic_t *)lock; 279 atomic_t *count = (atomic_t *)&lock->write;
280 280
281 if (atomic_sub_and_test(RW_LOCK_BIAS, count)) 281 if (atomic_sub_and_test(WRITE_LOCK_CMP, count))
282 return 1; 282 return 1;
283 atomic_add(RW_LOCK_BIAS, count); 283 atomic_add(WRITE_LOCK_CMP, count);
284 return 0; 284 return 0;
285} 285}
286 286
287static inline void arch_read_unlock(arch_rwlock_t *rw) 287static inline void arch_read_unlock(arch_rwlock_t *rw)
288{ 288{
289 asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory"); 289 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0"
290 :"+m" (rw->lock) : : "memory");
290} 291}
291 292
292static inline void arch_write_unlock(arch_rwlock_t *rw) 293static inline void arch_write_unlock(arch_rwlock_t *rw)
293{ 294{
294 asm volatile(LOCK_PREFIX "addl %1, %0" 295 asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0"
295 : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory"); 296 : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory");
296} 297}
297 298
298#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 299#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
299#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 300#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
300 301
302#undef READ_LOCK_SIZE
303#undef READ_LOCK_ATOMIC
304#undef WRITE_LOCK_ADD
305#undef WRITE_LOCK_SUB
306#undef WRITE_LOCK_CMP
307
301#define arch_spin_relax(lock) cpu_relax() 308#define arch_spin_relax(lock) cpu_relax()
302#define arch_read_relax(lock) cpu_relax() 309#define arch_read_relax(lock) cpu_relax()
303#define arch_write_relax(lock) cpu_relax() 310#define arch_write_relax(lock) cpu_relax()
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index dcb48b2edc11..7c7a486fcb68 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -11,10 +11,6 @@ typedef struct arch_spinlock {
11 11
12#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } 12#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
13 13
14typedef struct { 14#include <asm/rwlock.h>
15 unsigned int lock;
16} arch_rwlock_t;
17
18#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
19 15
20#endif /* _ASM_X86_SPINLOCK_TYPES_H */ 16#endif /* _ASM_X86_SPINLOCK_TYPES_H */
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 1f2e61e28981..a1fe5c127b52 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -21,7 +21,7 @@ struct task_struct;
21struct exec_domain; 21struct exec_domain;
22#include <asm/processor.h> 22#include <asm/processor.h>
23#include <asm/ftrace.h> 23#include <asm/ftrace.h>
24#include <asm/atomic.h> 24#include <linux/atomic.h>
25 25
26struct thread_info { 26struct thread_info {
27 struct task_struct *task; /* main task structure */ 27 struct task_struct *task; /* main task structure */
diff --git a/arch/x86/include/asm/time.h b/arch/x86/include/asm/time.h
index 7bdec4e9b739..92b8aec06970 100644
--- a/arch/x86/include/asm/time.h
+++ b/arch/x86/include/asm/time.h
@@ -1,10 +1,12 @@
1#ifndef _ASM_X86_TIME_H 1#ifndef _ASM_X86_TIME_H
2#define _ASM_X86_TIME_H 2#define _ASM_X86_TIME_H
3 3
4extern void hpet_time_init(void); 4#include <linux/clocksource.h>
5
6#include <asm/mc146818rtc.h> 5#include <asm/mc146818rtc.h>
7 6
7extern void hpet_time_init(void);
8extern void time_init(void); 8extern void time_init(void);
9 9
10extern struct clock_event_device *global_clock_event;
11
10#endif /* _ASM_X86_TIME_H */ 12#endif /* _ASM_X86_TIME_H */
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index 0310da67307f..0012d0902c5f 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -1,6 +1,8 @@
1#ifndef _ASM_X86_TRAPS_H 1#ifndef _ASM_X86_TRAPS_H
2#define _ASM_X86_TRAPS_H 2#define _ASM_X86_TRAPS_H
3 3
4#include <linux/kprobes.h>
5
4#include <asm/debugreg.h> 6#include <asm/debugreg.h>
5#include <asm/siginfo.h> /* TRAP_TRACE, ... */ 7#include <asm/siginfo.h> /* TRAP_TRACE, ... */
6 8
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 9db5583b6d38..83e2efd181e2 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,10 +51,6 @@ extern int unsynchronized_tsc(void);
51extern int check_tsc_unstable(void); 51extern int check_tsc_unstable(void);
52extern unsigned long native_calibrate_tsc(void); 52extern unsigned long native_calibrate_tsc(void);
53 53
54#ifdef CONFIG_X86_64
55extern cycles_t vread_tsc(void);
56#endif
57
58/* 54/*
59 * Boot-time check whether the TSCs are synchronized across 55 * Boot-time check whether the TSCs are synchronized across
60 * all CPUs/cores: 56 * all CPUs/cores:
diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h
index 99ddd148a760..36361bf6fdd1 100644
--- a/arch/x86/include/asm/uaccess.h
+++ b/arch/x86/include/asm/uaccess.h
@@ -555,6 +555,9 @@ struct __large_struct { unsigned long buf[100]; };
555 555
556#endif /* CONFIG_X86_WP_WORKS_OK */ 556#endif /* CONFIG_X86_WP_WORKS_OK */
557 557
558extern unsigned long
559copy_from_user_nmi(void *to, const void __user *from, unsigned long n);
560
558/* 561/*
559 * movsl can be slow when source and dest are not both 8-byte aligned 562 * movsl can be slow when source and dest are not both 8-byte aligned
560 */ 563 */
diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h
index 705bf139288c..0a6ba337a2eb 100644
--- a/arch/x86/include/asm/unistd_64.h
+++ b/arch/x86/include/asm/unistd_64.h
@@ -414,7 +414,7 @@ __SYSCALL(__NR_query_module, sys_ni_syscall)
414__SYSCALL(__NR_quotactl, sys_quotactl) 414__SYSCALL(__NR_quotactl, sys_quotactl)
415 415
416#define __NR_nfsservctl 180 416#define __NR_nfsservctl 180
417__SYSCALL(__NR_nfsservctl, sys_nfsservctl) 417__SYSCALL(__NR_nfsservctl, sys_ni_syscall)
418 418
419/* reserved for LiS/STREAMS */ 419/* reserved for LiS/STREAMS */
420#define __NR_getpmsg 181 420#define __NR_getpmsg 181
@@ -624,7 +624,6 @@ __SYSCALL(__NR_vmsplice, sys_vmsplice)
624__SYSCALL(__NR_move_pages, sys_move_pages) 624__SYSCALL(__NR_move_pages, sys_move_pages)
625#define __NR_utimensat 280 625#define __NR_utimensat 280
626__SYSCALL(__NR_utimensat, sys_utimensat) 626__SYSCALL(__NR_utimensat, sys_utimensat)
627#define __IGNORE_getcpu /* implemented as a vsyscall */
628#define __NR_epoll_pwait 281 627#define __NR_epoll_pwait 281
629__SYSCALL(__NR_epoll_pwait, sys_epoll_pwait) 628__SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
630#define __NR_signalfd 282 629#define __NR_signalfd 282
@@ -681,6 +680,8 @@ __SYSCALL(__NR_syncfs, sys_syncfs)
681__SYSCALL(__NR_sendmmsg, sys_sendmmsg) 680__SYSCALL(__NR_sendmmsg, sys_sendmmsg)
682#define __NR_setns 308 681#define __NR_setns 308
683__SYSCALL(__NR_setns, sys_setns) 682__SYSCALL(__NR_setns, sys_setns)
683#define __NR_getcpu 309
684__SYSCALL(__NR_getcpu, sys_getcpu)
684 685
685#ifndef __NO_STUBS 686#ifndef __NO_STUBS
686#define __ARCH_WANT_OLD_READDIR 687#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index a291c40efd43..37d369859c8e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -67,7 +67,7 @@
67 * we're using 655us, similar to UV1: 65 units of 10us 67 * we're using 655us, similar to UV1: 65 units of 10us
68 */ 68 */
69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) 69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL) 70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
71 71
72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ 72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ 73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
@@ -106,12 +106,20 @@
106#define DS_SOURCE_TIMEOUT 3 106#define DS_SOURCE_TIMEOUT 3
107/* 107/*
108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
109 * values 1 and 5 will not occur 109 * values 1 and 3 will not occur
110 * Decoded meaning ERROR BUSY AUX ERR
111 * ------------------------------- ---- ----- -------
112 * IDLE 0 0 0
113 * BUSY (active) 0 1 0
114 * SW Ack Timeout (destination) 1 0 0
115 * SW Ack INTD rejected (strong NACK) 1 0 1
116 * Source Side Time Out Detected 1 1 0
117 * Destination Side PUT Failed 1 1 1
110 */ 118 */
111#define UV2H_DESC_IDLE 0 119#define UV2H_DESC_IDLE 0
112#define UV2H_DESC_DEST_TIMEOUT 2 120#define UV2H_DESC_BUSY 2
113#define UV2H_DESC_DEST_STRONG_NACK 3 121#define UV2H_DESC_DEST_TIMEOUT 4
114#define UV2H_DESC_BUSY 4 122#define UV2H_DESC_DEST_STRONG_NACK 5
115#define UV2H_DESC_SOURCE_TIMEOUT 6 123#define UV2H_DESC_SOURCE_TIMEOUT 6
116#define UV2H_DESC_DEST_PUT_ERR 7 124#define UV2H_DESC_DEST_PUT_ERR 7
117 125
@@ -183,7 +191,7 @@
183 * 'base_dest_nasid' field of the header corresponds to the 191 * 'base_dest_nasid' field of the header corresponds to the
184 * destination nodeID associated with that specified bit. 192 * destination nodeID associated with that specified bit.
185 */ 193 */
186struct bau_targ_hubmask { 194struct pnmask {
187 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; 195 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
188}; 196};
189 197
@@ -314,7 +322,7 @@ struct bau_msg_header {
314 * Should be 64 bytes 322 * Should be 64 bytes
315 */ 323 */
316struct bau_desc { 324struct bau_desc {
317 struct bau_targ_hubmask distribution; 325 struct pnmask distribution;
318 /* 326 /*
319 * message template, consisting of header and payload: 327 * message template, consisting of header and payload:
320 */ 328 */
@@ -488,6 +496,7 @@ struct bau_control {
488 struct bau_control *uvhub_master; 496 struct bau_control *uvhub_master;
489 struct bau_control *socket_master; 497 struct bau_control *socket_master;
490 struct ptc_stats *statp; 498 struct ptc_stats *statp;
499 cpumask_t *cpumask;
491 unsigned long timeout_interval; 500 unsigned long timeout_interval;
492 unsigned long set_bau_on_time; 501 unsigned long set_bau_on_time;
493 atomic_t active_descriptor_count; 502 atomic_t active_descriptor_count;
@@ -526,90 +535,90 @@ struct bau_control {
526 struct hub_and_pnode *thp; 535 struct hub_and_pnode *thp;
527}; 536};
528 537
529static unsigned long read_mmr_uv2_status(void) 538static inline unsigned long read_mmr_uv2_status(void)
530{ 539{
531 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2); 540 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
532} 541}
533 542
534static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) 543static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
535{ 544{
536 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); 545 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
537} 546}
538 547
539static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) 548static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
540{ 549{
541 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); 550 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
542} 551}
543 552
544static void write_mmr_activation(unsigned long index) 553static inline void write_mmr_activation(unsigned long index)
545{ 554{
546 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); 555 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
547} 556}
548 557
549static void write_gmmr_activation(int pnode, unsigned long mmr_image) 558static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
550{ 559{
551 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); 560 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
552} 561}
553 562
554static void write_mmr_payload_first(int pnode, unsigned long mmr_image) 563static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
555{ 564{
556 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); 565 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
557} 566}
558 567
559static void write_mmr_payload_tail(int pnode, unsigned long mmr_image) 568static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
560{ 569{
561 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); 570 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
562} 571}
563 572
564static void write_mmr_payload_last(int pnode, unsigned long mmr_image) 573static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
565{ 574{
566 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); 575 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
567} 576}
568 577
569static void write_mmr_misc_control(int pnode, unsigned long mmr_image) 578static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
570{ 579{
571 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); 580 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
572} 581}
573 582
574static unsigned long read_mmr_misc_control(int pnode) 583static inline unsigned long read_mmr_misc_control(int pnode)
575{ 584{
576 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); 585 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
577} 586}
578 587
579static void write_mmr_sw_ack(unsigned long mr) 588static inline void write_mmr_sw_ack(unsigned long mr)
580{ 589{
581 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); 590 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
582} 591}
583 592
584static unsigned long read_mmr_sw_ack(void) 593static inline unsigned long read_mmr_sw_ack(void)
585{ 594{
586 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 595 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
587} 596}
588 597
589static unsigned long read_gmmr_sw_ack(int pnode) 598static inline unsigned long read_gmmr_sw_ack(int pnode)
590{ 599{
591 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); 600 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
592} 601}
593 602
594static void write_mmr_data_config(int pnode, unsigned long mr) 603static inline void write_mmr_data_config(int pnode, unsigned long mr)
595{ 604{
596 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); 605 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
597} 606}
598 607
599static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp) 608static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
600{ 609{
601 return constant_test_bit(uvhub, &dstp->bits[0]); 610 return constant_test_bit(uvhub, &dstp->bits[0]);
602} 611}
603static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp) 612static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
604{ 613{
605 __set_bit(pnode, &dstp->bits[0]); 614 __set_bit(pnode, &dstp->bits[0]);
606} 615}
607static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp, 616static inline void bau_uvhubs_clear(struct pnmask *dstp,
608 int nbits) 617 int nbits)
609{ 618{
610 bitmap_zero(&dstp->bits[0], nbits); 619 bitmap_zero(&dstp->bits[0], nbits);
611} 620}
612static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp) 621static inline int bau_uvhub_weight(struct pnmask *dstp)
613{ 622{
614 return bitmap_weight((unsigned long *)&dstp->bits[0], 623 return bitmap_weight((unsigned long *)&dstp->bits[0],
615 UV_DISTRIBUTION_SIZE); 624 UV_DISTRIBUTION_SIZE);
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index 4be52c863448..10474fb1185d 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -61,1689 +61,2016 @@
61/* Compat: if this #define is present, UV headers support UV2 */ 61/* Compat: if this #define is present, UV headers support UV2 */
62#define UV2_HUB_IS_SUPPORTED 1 62#define UV2_HUB_IS_SUPPORTED 1
63 63
64/* KABI compat: if this #define is present, KABI hacks are present */
65#define UV2_HUB_KABI_HACKS 1
66
67/* ========================================================================= */ 64/* ========================================================================= */
68/* UVH_BAU_DATA_BROADCAST */ 65/* UVH_BAU_DATA_BROADCAST */
69/* ========================================================================= */ 66/* ========================================================================= */
70#define UVH_BAU_DATA_BROADCAST 0x61688UL 67#define UVH_BAU_DATA_BROADCAST 0x61688UL
71#define UVH_BAU_DATA_BROADCAST_32 0x440 68#define UVH_BAU_DATA_BROADCAST_32 0x440
72 69
73#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 70#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
74#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 71#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
75 72
76union uvh_bau_data_broadcast_u { 73union uvh_bau_data_broadcast_u {
77 unsigned long v; 74 unsigned long v;
78 struct uvh_bau_data_broadcast_s { 75 struct uvh_bau_data_broadcast_s {
79 unsigned long enable : 1; /* RW */ 76 unsigned long enable:1; /* RW */
80 unsigned long rsvd_1_63: 63; /* */ 77 unsigned long rsvd_1_63:63;
81 } s; 78 } s;
82}; 79};
83 80
84/* ========================================================================= */ 81/* ========================================================================= */
85/* UVH_BAU_DATA_CONFIG */ 82/* UVH_BAU_DATA_CONFIG */
86/* ========================================================================= */ 83/* ========================================================================= */
87#define UVH_BAU_DATA_CONFIG 0x61680UL 84#define UVH_BAU_DATA_CONFIG 0x61680UL
88#define UVH_BAU_DATA_CONFIG_32 0x438 85#define UVH_BAU_DATA_CONFIG_32 0x438
89 86
90#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 87#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
91#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 88#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
92#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 89#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
93#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 90#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
94#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 91#define UVH_BAU_DATA_CONFIG_P_SHFT 13
95#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 92#define UVH_BAU_DATA_CONFIG_T_SHFT 15
96#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 93#define UVH_BAU_DATA_CONFIG_M_SHFT 16
97#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 94#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
98#define UVH_BAU_DATA_CONFIG_P_SHFT 13 95#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
99#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 96#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
100#define UVH_BAU_DATA_CONFIG_T_SHFT 15 97#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
101#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 98#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
102#define UVH_BAU_DATA_CONFIG_M_SHFT 16 99#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
103#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 100#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
104#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 101#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
105#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 102#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
106 103
107union uvh_bau_data_config_u { 104union uvh_bau_data_config_u {
108 unsigned long v; 105 unsigned long v;
109 struct uvh_bau_data_config_s { 106 struct uvh_bau_data_config_s {
110 unsigned long vector_ : 8; /* RW */ 107 unsigned long vector_:8; /* RW */
111 unsigned long dm : 3; /* RW */ 108 unsigned long dm:3; /* RW */
112 unsigned long destmode : 1; /* RW */ 109 unsigned long destmode:1; /* RW */
113 unsigned long status : 1; /* RO */ 110 unsigned long status:1; /* RO */
114 unsigned long p : 1; /* RO */ 111 unsigned long p:1; /* RO */
115 unsigned long rsvd_14 : 1; /* */ 112 unsigned long rsvd_14:1;
116 unsigned long t : 1; /* RO */ 113 unsigned long t:1; /* RO */
117 unsigned long m : 1; /* RW */ 114 unsigned long m:1; /* RW */
118 unsigned long rsvd_17_31: 15; /* */ 115 unsigned long rsvd_17_31:15;
119 unsigned long apic_id : 32; /* RW */ 116 unsigned long apic_id:32; /* RW */
120 } s; 117 } s;
121}; 118};
122 119
123/* ========================================================================= */ 120/* ========================================================================= */
124/* UVH_EVENT_OCCURRED0 */ 121/* UVH_EVENT_OCCURRED0 */
125/* ========================================================================= */ 122/* ========================================================================= */
126#define UVH_EVENT_OCCURRED0 0x70000UL 123#define UVH_EVENT_OCCURRED0 0x70000UL
127#define UVH_EVENT_OCCURRED0_32 0x5e8 124#define UVH_EVENT_OCCURRED0_32 0x5e8
128 125
129#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 126#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
130#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 127#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
131#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 128#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
132#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 129#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
133#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 130#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
134#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 131#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
135#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 132#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
136#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 133#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
137#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 134#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
138#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 135#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
139#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 136#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
140#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 137#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
141#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 138#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
142#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 139#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
143#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 140#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
144#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 141#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
145#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 142#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
146#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 143#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
147#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 144#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
148#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 145#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
149#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 146#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
150#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 147#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
151#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 148#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
152#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 149#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
153#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 150#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
154#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 151#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
155#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 152#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
156#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 153#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
157#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 154#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
158#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 155#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
159#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 156#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
160#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 157#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
161#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 158#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
162#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 159#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
163#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 160#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
164#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 161#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
165#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 162#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
166#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 163#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
167#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 164#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
168#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 165#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
169#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 166#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
170#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 167#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
171#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 168#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
172#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 169#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
173#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 170#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
174#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 171#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
175#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 172#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
176#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 173#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
177#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 174#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
178#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 175#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
179#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 176#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
180#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 177#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
181#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 178#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
182#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 179#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
183#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 180#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
184#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 181#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
185#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 182#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
186#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 183#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
187#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 184#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
188#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 185#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
189#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 186#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
190#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 187#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
191#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 188#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
192#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 189#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
193#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 190#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
194#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 191#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
195#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 192#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
196#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 193#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
197#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 194#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
198#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 195#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
199#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 196#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
200#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 197#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
201#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 198#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
202#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 199#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
203#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 200#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
204#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 201#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
205#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 202#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
206#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 203#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
207#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 204#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
208#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 205#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
209#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 206#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
210#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 207#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
211#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 208#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
212#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 209#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
213#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 210#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
214#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 211#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
215#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 212#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
216#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 213#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
217#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 214#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
218#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 215#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
219#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 216#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
220#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 217#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
221#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 218#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
222#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 219#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
223#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 220#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
224#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 221#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
225#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 222#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
226#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 223#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
227#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 224#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
228#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 225#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
229#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 226#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
230#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 227#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
231#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 228#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
232#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 229#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
233#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 230#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
234#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 231#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
235#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 232#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
236#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 233#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
237#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 234#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
238#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 235#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
239#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 236#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
240#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 237#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
241#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 238#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
242#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 239#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
243 240
244#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0 241#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
245#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 242#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
246#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 243#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
247#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 244#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
248#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2 245#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
249#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 246#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
250#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 247#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
251#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 248#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
252#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 249#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
253#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 250#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
254#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 251#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
255#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 252#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
256#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 253#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
257#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 254#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
258#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 255#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
259#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 256#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
260#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 257#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
261#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 258#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
262#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 259#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
263#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 260#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
264#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 261#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
265#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 262#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
266#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 263#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
267#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 264#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
268#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 265#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
269#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 266#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
270#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 267#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
271#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 268#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
272#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 269#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
273#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 270#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
274#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 271#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
275#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 272#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
276#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 273#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
277#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 274#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
278#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 275#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
279#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 276#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
280#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 277#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
281#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 278#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
282#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 279#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
283#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 280#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
284#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 281#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
285#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 282#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
286#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 283#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
287#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 284#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
288#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 285#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
289#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 286#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
290#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 287#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
291#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 288#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
292#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 289#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
293#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 290#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
294#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 291#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
295#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 292#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
296#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 293#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
297#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 294#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
298#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 295#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
299#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 296#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
300#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 297#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
301#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 298#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
302#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 299#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
303#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 300#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
304#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 301#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
305#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 302#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
306#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 303#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
307#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 304#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
308#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 305#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
309#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 306#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
310#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 307#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
311#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 308#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
312#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 309#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
313#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 310#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
314#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 311#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
315#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 312#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
316#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 313#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
317#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 314#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
318#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 315#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
319#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 316#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
320#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 317#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
321#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 318#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
322#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 319#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
323#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 320#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
324#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 321#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
325#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 322#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
326#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 323#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
327#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 324#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
328#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 325#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
329#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 326#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
330#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 327#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
331#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 328#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
332#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 329#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
333#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 330#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
334#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 331#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
335#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 332#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
336#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 333#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
337#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 334#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
338#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 335#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
339#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 336#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
340#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 337#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
341#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 338#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
342#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 339#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
343#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 340#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
344#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 341#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
345#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 342#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
346#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 343#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
347#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 344#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
348#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 345#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
349#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 346#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
350#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 347#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
351#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 348#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
352#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 349#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
353#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 350#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
354#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 351#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
355#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 352#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
356#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 353#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
357#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 354#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
358#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 355#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
359#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 356#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
360#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 357#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
361#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 358#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
362 359
363union uvh_event_occurred0_u { 360union uvh_event_occurred0_u {
364 unsigned long v; 361 unsigned long v;
365 struct uv1h_event_occurred0_s { 362 struct uv1h_event_occurred0_s {
366 unsigned long lb_hcerr : 1; /* RW, W1C */ 363 unsigned long lb_hcerr:1; /* RW, W1C */
367 unsigned long gr0_hcerr : 1; /* RW, W1C */ 364 unsigned long gr0_hcerr:1; /* RW, W1C */
368 unsigned long gr1_hcerr : 1; /* RW, W1C */ 365 unsigned long gr1_hcerr:1; /* RW, W1C */
369 unsigned long lh_hcerr : 1; /* RW, W1C */ 366 unsigned long lh_hcerr:1; /* RW, W1C */
370 unsigned long rh_hcerr : 1; /* RW, W1C */ 367 unsigned long rh_hcerr:1; /* RW, W1C */
371 unsigned long xn_hcerr : 1; /* RW, W1C */ 368 unsigned long xn_hcerr:1; /* RW, W1C */
372 unsigned long si_hcerr : 1; /* RW, W1C */ 369 unsigned long si_hcerr:1; /* RW, W1C */
373 unsigned long lb_aoerr0 : 1; /* RW, W1C */ 370 unsigned long lb_aoerr0:1; /* RW, W1C */
374 unsigned long gr0_aoerr0 : 1; /* RW, W1C */ 371 unsigned long gr0_aoerr0:1; /* RW, W1C */
375 unsigned long gr1_aoerr0 : 1; /* RW, W1C */ 372 unsigned long gr1_aoerr0:1; /* RW, W1C */
376 unsigned long lh_aoerr0 : 1; /* RW, W1C */ 373 unsigned long lh_aoerr0:1; /* RW, W1C */
377 unsigned long rh_aoerr0 : 1; /* RW, W1C */ 374 unsigned long rh_aoerr0:1; /* RW, W1C */
378 unsigned long xn_aoerr0 : 1; /* RW, W1C */ 375 unsigned long xn_aoerr0:1; /* RW, W1C */
379 unsigned long si_aoerr0 : 1; /* RW, W1C */ 376 unsigned long si_aoerr0:1; /* RW, W1C */
380 unsigned long lb_aoerr1 : 1; /* RW, W1C */ 377 unsigned long lb_aoerr1:1; /* RW, W1C */
381 unsigned long gr0_aoerr1 : 1; /* RW, W1C */ 378 unsigned long gr0_aoerr1:1; /* RW, W1C */
382 unsigned long gr1_aoerr1 : 1; /* RW, W1C */ 379 unsigned long gr1_aoerr1:1; /* RW, W1C */
383 unsigned long lh_aoerr1 : 1; /* RW, W1C */ 380 unsigned long lh_aoerr1:1; /* RW, W1C */
384 unsigned long rh_aoerr1 : 1; /* RW, W1C */ 381 unsigned long rh_aoerr1:1; /* RW, W1C */
385 unsigned long xn_aoerr1 : 1; /* RW, W1C */ 382 unsigned long xn_aoerr1:1; /* RW, W1C */
386 unsigned long si_aoerr1 : 1; /* RW, W1C */ 383 unsigned long si_aoerr1:1; /* RW, W1C */
387 unsigned long rh_vpi_int : 1; /* RW, W1C */ 384 unsigned long rh_vpi_int:1; /* RW, W1C */
388 unsigned long system_shutdown_int : 1; /* RW, W1C */ 385 unsigned long system_shutdown_int:1; /* RW, W1C */
389 unsigned long lb_irq_int_0 : 1; /* RW, W1C */ 386 unsigned long lb_irq_int_0:1; /* RW, W1C */
390 unsigned long lb_irq_int_1 : 1; /* RW, W1C */ 387 unsigned long lb_irq_int_1:1; /* RW, W1C */
391 unsigned long lb_irq_int_2 : 1; /* RW, W1C */ 388 unsigned long lb_irq_int_2:1; /* RW, W1C */
392 unsigned long lb_irq_int_3 : 1; /* RW, W1C */ 389 unsigned long lb_irq_int_3:1; /* RW, W1C */
393 unsigned long lb_irq_int_4 : 1; /* RW, W1C */ 390 unsigned long lb_irq_int_4:1; /* RW, W1C */
394 unsigned long lb_irq_int_5 : 1; /* RW, W1C */ 391 unsigned long lb_irq_int_5:1; /* RW, W1C */
395 unsigned long lb_irq_int_6 : 1; /* RW, W1C */ 392 unsigned long lb_irq_int_6:1; /* RW, W1C */
396 unsigned long lb_irq_int_7 : 1; /* RW, W1C */ 393 unsigned long lb_irq_int_7:1; /* RW, W1C */
397 unsigned long lb_irq_int_8 : 1; /* RW, W1C */ 394 unsigned long lb_irq_int_8:1; /* RW, W1C */
398 unsigned long lb_irq_int_9 : 1; /* RW, W1C */ 395 unsigned long lb_irq_int_9:1; /* RW, W1C */
399 unsigned long lb_irq_int_10 : 1; /* RW, W1C */ 396 unsigned long lb_irq_int_10:1; /* RW, W1C */
400 unsigned long lb_irq_int_11 : 1; /* RW, W1C */ 397 unsigned long lb_irq_int_11:1; /* RW, W1C */
401 unsigned long lb_irq_int_12 : 1; /* RW, W1C */ 398 unsigned long lb_irq_int_12:1; /* RW, W1C */
402 unsigned long lb_irq_int_13 : 1; /* RW, W1C */ 399 unsigned long lb_irq_int_13:1; /* RW, W1C */
403 unsigned long lb_irq_int_14 : 1; /* RW, W1C */ 400 unsigned long lb_irq_int_14:1; /* RW, W1C */
404 unsigned long lb_irq_int_15 : 1; /* RW, W1C */ 401 unsigned long lb_irq_int_15:1; /* RW, W1C */
405 unsigned long l1_nmi_int : 1; /* RW, W1C */ 402 unsigned long l1_nmi_int:1; /* RW, W1C */
406 unsigned long stop_clock : 1; /* RW, W1C */ 403 unsigned long stop_clock:1; /* RW, W1C */
407 unsigned long asic_to_l1 : 1; /* RW, W1C */ 404 unsigned long asic_to_l1:1; /* RW, W1C */
408 unsigned long l1_to_asic : 1; /* RW, W1C */ 405 unsigned long l1_to_asic:1; /* RW, W1C */
409 unsigned long ltc_int : 1; /* RW, W1C */ 406 unsigned long ltc_int:1; /* RW, W1C */
410 unsigned long la_seq_trigger : 1; /* RW, W1C */ 407 unsigned long la_seq_trigger:1; /* RW, W1C */
411 unsigned long ipi_int : 1; /* RW, W1C */ 408 unsigned long ipi_int:1; /* RW, W1C */
412 unsigned long extio_int0 : 1; /* RW, W1C */ 409 unsigned long extio_int0:1; /* RW, W1C */
413 unsigned long extio_int1 : 1; /* RW, W1C */ 410 unsigned long extio_int1:1; /* RW, W1C */
414 unsigned long extio_int2 : 1; /* RW, W1C */ 411 unsigned long extio_int2:1; /* RW, W1C */
415 unsigned long extio_int3 : 1; /* RW, W1C */ 412 unsigned long extio_int3:1; /* RW, W1C */
416 unsigned long profile_int : 1; /* RW, W1C */ 413 unsigned long profile_int:1; /* RW, W1C */
417 unsigned long rtc0 : 1; /* RW, W1C */ 414 unsigned long rtc0:1; /* RW, W1C */
418 unsigned long rtc1 : 1; /* RW, W1C */ 415 unsigned long rtc1:1; /* RW, W1C */
419 unsigned long rtc2 : 1; /* RW, W1C */ 416 unsigned long rtc2:1; /* RW, W1C */
420 unsigned long rtc3 : 1; /* RW, W1C */ 417 unsigned long rtc3:1; /* RW, W1C */
421 unsigned long bau_data : 1; /* RW, W1C */ 418 unsigned long bau_data:1; /* RW, W1C */
422 unsigned long power_management_req : 1; /* RW, W1C */ 419 unsigned long power_management_req:1; /* RW, W1C */
423 unsigned long rsvd_57_63 : 7; /* */ 420 unsigned long rsvd_57_63:7;
424 } s1; 421 } s1;
425 struct uv2h_event_occurred0_s { 422 struct uv2h_event_occurred0_s {
426 unsigned long lb_hcerr : 1; /* RW */ 423 unsigned long lb_hcerr:1; /* RW */
427 unsigned long qp_hcerr : 1; /* RW */ 424 unsigned long qp_hcerr:1; /* RW */
428 unsigned long rh_hcerr : 1; /* RW */ 425 unsigned long rh_hcerr:1; /* RW */
429 unsigned long lh0_hcerr : 1; /* RW */ 426 unsigned long lh0_hcerr:1; /* RW */
430 unsigned long lh1_hcerr : 1; /* RW */ 427 unsigned long lh1_hcerr:1; /* RW */
431 unsigned long gr0_hcerr : 1; /* RW */ 428 unsigned long gr0_hcerr:1; /* RW */
432 unsigned long gr1_hcerr : 1; /* RW */ 429 unsigned long gr1_hcerr:1; /* RW */
433 unsigned long ni0_hcerr : 1; /* RW */ 430 unsigned long ni0_hcerr:1; /* RW */
434 unsigned long ni1_hcerr : 1; /* RW */ 431 unsigned long ni1_hcerr:1; /* RW */
435 unsigned long lb_aoerr0 : 1; /* RW */ 432 unsigned long lb_aoerr0:1; /* RW */
436 unsigned long qp_aoerr0 : 1; /* RW */ 433 unsigned long qp_aoerr0:1; /* RW */
437 unsigned long rh_aoerr0 : 1; /* RW */ 434 unsigned long rh_aoerr0:1; /* RW */
438 unsigned long lh0_aoerr0 : 1; /* RW */ 435 unsigned long lh0_aoerr0:1; /* RW */
439 unsigned long lh1_aoerr0 : 1; /* RW */ 436 unsigned long lh1_aoerr0:1; /* RW */
440 unsigned long gr0_aoerr0 : 1; /* RW */ 437 unsigned long gr0_aoerr0:1; /* RW */
441 unsigned long gr1_aoerr0 : 1; /* RW */ 438 unsigned long gr1_aoerr0:1; /* RW */
442 unsigned long xb_aoerr0 : 1; /* RW */ 439 unsigned long xb_aoerr0:1; /* RW */
443 unsigned long rt_aoerr0 : 1; /* RW */ 440 unsigned long rt_aoerr0:1; /* RW */
444 unsigned long ni0_aoerr0 : 1; /* RW */ 441 unsigned long ni0_aoerr0:1; /* RW */
445 unsigned long ni1_aoerr0 : 1; /* RW */ 442 unsigned long ni1_aoerr0:1; /* RW */
446 unsigned long lb_aoerr1 : 1; /* RW */ 443 unsigned long lb_aoerr1:1; /* RW */
447 unsigned long qp_aoerr1 : 1; /* RW */ 444 unsigned long qp_aoerr1:1; /* RW */
448 unsigned long rh_aoerr1 : 1; /* RW */ 445 unsigned long rh_aoerr1:1; /* RW */
449 unsigned long lh0_aoerr1 : 1; /* RW */ 446 unsigned long lh0_aoerr1:1; /* RW */
450 unsigned long lh1_aoerr1 : 1; /* RW */ 447 unsigned long lh1_aoerr1:1; /* RW */
451 unsigned long gr0_aoerr1 : 1; /* RW */ 448 unsigned long gr0_aoerr1:1; /* RW */
452 unsigned long gr1_aoerr1 : 1; /* RW */ 449 unsigned long gr1_aoerr1:1; /* RW */
453 unsigned long xb_aoerr1 : 1; /* RW */ 450 unsigned long xb_aoerr1:1; /* RW */
454 unsigned long rt_aoerr1 : 1; /* RW */ 451 unsigned long rt_aoerr1:1; /* RW */
455 unsigned long ni0_aoerr1 : 1; /* RW */ 452 unsigned long ni0_aoerr1:1; /* RW */
456 unsigned long ni1_aoerr1 : 1; /* RW */ 453 unsigned long ni1_aoerr1:1; /* RW */
457 unsigned long system_shutdown_int : 1; /* RW */ 454 unsigned long system_shutdown_int:1; /* RW */
458 unsigned long lb_irq_int_0 : 1; /* RW */ 455 unsigned long lb_irq_int_0:1; /* RW */
459 unsigned long lb_irq_int_1 : 1; /* RW */ 456 unsigned long lb_irq_int_1:1; /* RW */
460 unsigned long lb_irq_int_2 : 1; /* RW */ 457 unsigned long lb_irq_int_2:1; /* RW */
461 unsigned long lb_irq_int_3 : 1; /* RW */ 458 unsigned long lb_irq_int_3:1; /* RW */
462 unsigned long lb_irq_int_4 : 1; /* RW */ 459 unsigned long lb_irq_int_4:1; /* RW */
463 unsigned long lb_irq_int_5 : 1; /* RW */ 460 unsigned long lb_irq_int_5:1; /* RW */
464 unsigned long lb_irq_int_6 : 1; /* RW */ 461 unsigned long lb_irq_int_6:1; /* RW */
465 unsigned long lb_irq_int_7 : 1; /* RW */ 462 unsigned long lb_irq_int_7:1; /* RW */
466 unsigned long lb_irq_int_8 : 1; /* RW */ 463 unsigned long lb_irq_int_8:1; /* RW */
467 unsigned long lb_irq_int_9 : 1; /* RW */ 464 unsigned long lb_irq_int_9:1; /* RW */
468 unsigned long lb_irq_int_10 : 1; /* RW */ 465 unsigned long lb_irq_int_10:1; /* RW */
469 unsigned long lb_irq_int_11 : 1; /* RW */ 466 unsigned long lb_irq_int_11:1; /* RW */
470 unsigned long lb_irq_int_12 : 1; /* RW */ 467 unsigned long lb_irq_int_12:1; /* RW */
471 unsigned long lb_irq_int_13 : 1; /* RW */ 468 unsigned long lb_irq_int_13:1; /* RW */
472 unsigned long lb_irq_int_14 : 1; /* RW */ 469 unsigned long lb_irq_int_14:1; /* RW */
473 unsigned long lb_irq_int_15 : 1; /* RW */ 470 unsigned long lb_irq_int_15:1; /* RW */
474 unsigned long l1_nmi_int : 1; /* RW */ 471 unsigned long l1_nmi_int:1; /* RW */
475 unsigned long stop_clock : 1; /* RW */ 472 unsigned long stop_clock:1; /* RW */
476 unsigned long asic_to_l1 : 1; /* RW */ 473 unsigned long asic_to_l1:1; /* RW */
477 unsigned long l1_to_asic : 1; /* RW */ 474 unsigned long l1_to_asic:1; /* RW */
478 unsigned long la_seq_trigger : 1; /* RW */ 475 unsigned long la_seq_trigger:1; /* RW */
479 unsigned long ipi_int : 1; /* RW */ 476 unsigned long ipi_int:1; /* RW */
480 unsigned long extio_int0 : 1; /* RW */ 477 unsigned long extio_int0:1; /* RW */
481 unsigned long extio_int1 : 1; /* RW */ 478 unsigned long extio_int1:1; /* RW */
482 unsigned long extio_int2 : 1; /* RW */ 479 unsigned long extio_int2:1; /* RW */
483 unsigned long extio_int3 : 1; /* RW */ 480 unsigned long extio_int3:1; /* RW */
484 unsigned long profile_int : 1; /* RW */ 481 unsigned long profile_int:1; /* RW */
485 unsigned long rsvd_59_63 : 5; /* */ 482 unsigned long rsvd_59_63:5;
486 } s2; 483 } s2;
487}; 484};
488 485
489/* ========================================================================= */ 486/* ========================================================================= */
490/* UVH_EVENT_OCCURRED0_ALIAS */ 487/* UVH_EVENT_OCCURRED0_ALIAS */
491/* ========================================================================= */ 488/* ========================================================================= */
492#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL 489#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
493#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 490#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
494 491
495/* ========================================================================= */ 492/* ========================================================================= */
496/* UVH_GR0_TLB_INT0_CONFIG */ 493/* UVH_GR0_TLB_INT0_CONFIG */
497/* ========================================================================= */ 494/* ========================================================================= */
498#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 495#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
499 496
500#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 497#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
501#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 498#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
502#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 499#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
503#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 500#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
504#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 501#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
505#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 502#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
506#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 503#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
507#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 504#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
508#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 505#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
509#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 506#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
510#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 507#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
511#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 508#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
512#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 509#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
513#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 510#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
514#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 511#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
515#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 512#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
516 513
517union uvh_gr0_tlb_int0_config_u { 514union uvh_gr0_tlb_int0_config_u {
518 unsigned long v; 515 unsigned long v;
519 struct uvh_gr0_tlb_int0_config_s { 516 struct uvh_gr0_tlb_int0_config_s {
520 unsigned long vector_ : 8; /* RW */ 517 unsigned long vector_:8; /* RW */
521 unsigned long dm : 3; /* RW */ 518 unsigned long dm:3; /* RW */
522 unsigned long destmode : 1; /* RW */ 519 unsigned long destmode:1; /* RW */
523 unsigned long status : 1; /* RO */ 520 unsigned long status:1; /* RO */
524 unsigned long p : 1; /* RO */ 521 unsigned long p:1; /* RO */
525 unsigned long rsvd_14 : 1; /* */ 522 unsigned long rsvd_14:1;
526 unsigned long t : 1; /* RO */ 523 unsigned long t:1; /* RO */
527 unsigned long m : 1; /* RW */ 524 unsigned long m:1; /* RW */
528 unsigned long rsvd_17_31: 15; /* */ 525 unsigned long rsvd_17_31:15;
529 unsigned long apic_id : 32; /* RW */ 526 unsigned long apic_id:32; /* RW */
530 } s; 527 } s;
531}; 528};
532 529
533/* ========================================================================= */ 530/* ========================================================================= */
534/* UVH_GR0_TLB_INT1_CONFIG */ 531/* UVH_GR0_TLB_INT1_CONFIG */
535/* ========================================================================= */ 532/* ========================================================================= */
536#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 533#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
537 534
538#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 535#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
539#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 536#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
540#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 537#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
541#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 538#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
542#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 539#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
543#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 540#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
544#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 541#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
545#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 542#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
546#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 543#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
547#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 544#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
548#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 545#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
549#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 546#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
550#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 547#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
551#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 548#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
552#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 549#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
553#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 550#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
554 551
555union uvh_gr0_tlb_int1_config_u { 552union uvh_gr0_tlb_int1_config_u {
556 unsigned long v; 553 unsigned long v;
557 struct uvh_gr0_tlb_int1_config_s { 554 struct uvh_gr0_tlb_int1_config_s {
558 unsigned long vector_ : 8; /* RW */ 555 unsigned long vector_:8; /* RW */
559 unsigned long dm : 3; /* RW */ 556 unsigned long dm:3; /* RW */
560 unsigned long destmode : 1; /* RW */ 557 unsigned long destmode:1; /* RW */
561 unsigned long status : 1; /* RO */ 558 unsigned long status:1; /* RO */
562 unsigned long p : 1; /* RO */ 559 unsigned long p:1; /* RO */
563 unsigned long rsvd_14 : 1; /* */ 560 unsigned long rsvd_14:1;
564 unsigned long t : 1; /* RO */ 561 unsigned long t:1; /* RO */
565 unsigned long m : 1; /* RW */ 562 unsigned long m:1; /* RW */
566 unsigned long rsvd_17_31: 15; /* */ 563 unsigned long rsvd_17_31:15;
567 unsigned long apic_id : 32; /* RW */ 564 unsigned long apic_id:32; /* RW */
568 } s; 565 } s;
566};
567
568/* ========================================================================= */
569/* UVH_GR0_TLB_MMR_CONTROL */
570/* ========================================================================= */
571#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
572#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
573#define UVH_GR0_TLB_MMR_CONTROL (is_uv1_hub() ? \
574 UV1H_GR0_TLB_MMR_CONTROL : \
575 UV2H_GR0_TLB_MMR_CONTROL)
576
577#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
578#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
579#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
580#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
581#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
582#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
583#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
584#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
585#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
586#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
587#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
588#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
589
590#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
591#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
592#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
593#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
594#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
595#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
596#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
597#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
598#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
599#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
600#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
601#define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
602#define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
603#define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
604#define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
605#define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
606#define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
607#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
608#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
609#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
610#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
611#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
612
613#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
614#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
615#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
616#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
617#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
618#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
619#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
620#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
621#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
622#define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
623#define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
624#define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
625#define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
626#define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
627#define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
628#define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
629#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
630#define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
631
632union uvh_gr0_tlb_mmr_control_u {
633 unsigned long v;
634 struct uvh_gr0_tlb_mmr_control_s {
635 unsigned long index:12; /* RW */
636 unsigned long mem_sel:2; /* RW */
637 unsigned long rsvd_14_15:2;
638 unsigned long auto_valid_en:1; /* RW */
639 unsigned long rsvd_17_19:3;
640 unsigned long mmr_hash_index_en:1; /* RW */
641 unsigned long rsvd_21_29:9;
642 unsigned long mmr_write:1; /* WP */
643 unsigned long mmr_read:1; /* WP */
644 unsigned long rsvd_32_63:32;
645 } s;
646 struct uv1h_gr0_tlb_mmr_control_s {
647 unsigned long index:12; /* RW */
648 unsigned long mem_sel:2; /* RW */
649 unsigned long rsvd_14_15:2;
650 unsigned long auto_valid_en:1; /* RW */
651 unsigned long rsvd_17_19:3;
652 unsigned long mmr_hash_index_en:1; /* RW */
653 unsigned long rsvd_21_29:9;
654 unsigned long mmr_write:1; /* WP */
655 unsigned long mmr_read:1; /* WP */
656 unsigned long rsvd_32_47:16;
657 unsigned long mmr_inj_con:1; /* RW */
658 unsigned long rsvd_49_51:3;
659 unsigned long mmr_inj_tlbram:1; /* RW */
660 unsigned long rsvd_53:1;
661 unsigned long mmr_inj_tlbpgsize:1; /* RW */
662 unsigned long rsvd_55:1;
663 unsigned long mmr_inj_tlbrreg:1; /* RW */
664 unsigned long rsvd_57_59:3;
665 unsigned long mmr_inj_tlblruv:1; /* RW */
666 unsigned long rsvd_61_63:3;
667 } s1;
668 struct uv2h_gr0_tlb_mmr_control_s {
669 unsigned long index:12; /* RW */
670 unsigned long mem_sel:2; /* RW */
671 unsigned long rsvd_14_15:2;
672 unsigned long auto_valid_en:1; /* RW */
673 unsigned long rsvd_17_19:3;
674 unsigned long mmr_hash_index_en:1; /* RW */
675 unsigned long rsvd_21_29:9;
676 unsigned long mmr_write:1; /* WP */
677 unsigned long mmr_read:1; /* WP */
678 unsigned long mmr_op_done:1; /* RW */
679 unsigned long rsvd_33_47:15;
680 unsigned long mmr_inj_con:1; /* RW */
681 unsigned long rsvd_49_51:3;
682 unsigned long mmr_inj_tlbram:1; /* RW */
683 unsigned long rsvd_53_63:11;
684 } s2;
685};
686
687/* ========================================================================= */
688/* UVH_GR0_TLB_MMR_READ_DATA_HI */
689/* ========================================================================= */
690#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
691#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
692#define UVH_GR0_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
693 UV1H_GR0_TLB_MMR_READ_DATA_HI : \
694 UV2H_GR0_TLB_MMR_READ_DATA_HI)
695
696#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
697#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
698#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
699#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
700#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
701#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
702#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
703#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
704
705union uvh_gr0_tlb_mmr_read_data_hi_u {
706 unsigned long v;
707 struct uvh_gr0_tlb_mmr_read_data_hi_s {
708 unsigned long pfn:41; /* RO */
709 unsigned long gaa:2; /* RO */
710 unsigned long dirty:1; /* RO */
711 unsigned long larger:1; /* RO */
712 unsigned long rsvd_45_63:19;
713 } s;
714};
715
716/* ========================================================================= */
717/* UVH_GR0_TLB_MMR_READ_DATA_LO */
718/* ========================================================================= */
719#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
720#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
721#define UVH_GR0_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
722 UV1H_GR0_TLB_MMR_READ_DATA_LO : \
723 UV2H_GR0_TLB_MMR_READ_DATA_LO)
724
725#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
726#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
727#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
728#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
729#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
730#define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
731
732union uvh_gr0_tlb_mmr_read_data_lo_u {
733 unsigned long v;
734 struct uvh_gr0_tlb_mmr_read_data_lo_s {
735 unsigned long vpn:39; /* RO */
736 unsigned long asid:24; /* RO */
737 unsigned long valid:1; /* RO */
738 } s;
569}; 739};
570 740
571/* ========================================================================= */ 741/* ========================================================================= */
572/* UVH_GR1_TLB_INT0_CONFIG */ 742/* UVH_GR1_TLB_INT0_CONFIG */
573/* ========================================================================= */ 743/* ========================================================================= */
574#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 744#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
575 745
576#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 746#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
577#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 747#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
578#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 748#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
579#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 749#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
580#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 750#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
581#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 751#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
582#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 752#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
583#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 753#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
584#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 754#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
585#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 755#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
586#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 756#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
587#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 757#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
588#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 758#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
589#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 759#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
590#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 760#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
591#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 761#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
592 762
593union uvh_gr1_tlb_int0_config_u { 763union uvh_gr1_tlb_int0_config_u {
594 unsigned long v; 764 unsigned long v;
595 struct uvh_gr1_tlb_int0_config_s { 765 struct uvh_gr1_tlb_int0_config_s {
596 unsigned long vector_ : 8; /* RW */ 766 unsigned long vector_:8; /* RW */
597 unsigned long dm : 3; /* RW */ 767 unsigned long dm:3; /* RW */
598 unsigned long destmode : 1; /* RW */ 768 unsigned long destmode:1; /* RW */
599 unsigned long status : 1; /* RO */ 769 unsigned long status:1; /* RO */
600 unsigned long p : 1; /* RO */ 770 unsigned long p:1; /* RO */
601 unsigned long rsvd_14 : 1; /* */ 771 unsigned long rsvd_14:1;
602 unsigned long t : 1; /* RO */ 772 unsigned long t:1; /* RO */
603 unsigned long m : 1; /* RW */ 773 unsigned long m:1; /* RW */
604 unsigned long rsvd_17_31: 15; /* */ 774 unsigned long rsvd_17_31:15;
605 unsigned long apic_id : 32; /* RW */ 775 unsigned long apic_id:32; /* RW */
606 } s; 776 } s;
607}; 777};
608 778
609/* ========================================================================= */ 779/* ========================================================================= */
610/* UVH_GR1_TLB_INT1_CONFIG */ 780/* UVH_GR1_TLB_INT1_CONFIG */
611/* ========================================================================= */ 781/* ========================================================================= */
612#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 782#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
613 783
614#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 784#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
615#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 785#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
616#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 786#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
617#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 787#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
618#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 788#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
619#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 789#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
620#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 790#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
621#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 791#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
622#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 792#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
623#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 793#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
624#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 794#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
625#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 795#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
626#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 796#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
627#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 797#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
628#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 798#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
629#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 799#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
630 800
631union uvh_gr1_tlb_int1_config_u { 801union uvh_gr1_tlb_int1_config_u {
632 unsigned long v; 802 unsigned long v;
633 struct uvh_gr1_tlb_int1_config_s { 803 struct uvh_gr1_tlb_int1_config_s {
634 unsigned long vector_ : 8; /* RW */ 804 unsigned long vector_:8; /* RW */
635 unsigned long dm : 3; /* RW */ 805 unsigned long dm:3; /* RW */
636 unsigned long destmode : 1; /* RW */ 806 unsigned long destmode:1; /* RW */
637 unsigned long status : 1; /* RO */ 807 unsigned long status:1; /* RO */
638 unsigned long p : 1; /* RO */ 808 unsigned long p:1; /* RO */
639 unsigned long rsvd_14 : 1; /* */ 809 unsigned long rsvd_14:1;
640 unsigned long t : 1; /* RO */ 810 unsigned long t:1; /* RO */
641 unsigned long m : 1; /* RW */ 811 unsigned long m:1; /* RW */
642 unsigned long rsvd_17_31: 15; /* */ 812 unsigned long rsvd_17_31:15;
643 unsigned long apic_id : 32; /* RW */ 813 unsigned long apic_id:32; /* RW */
644 } s; 814 } s;
815};
816
817/* ========================================================================= */
818/* UVH_GR1_TLB_MMR_CONTROL */
819/* ========================================================================= */
820#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
821#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
822#define UVH_GR1_TLB_MMR_CONTROL (is_uv1_hub() ? \
823 UV1H_GR1_TLB_MMR_CONTROL : \
824 UV2H_GR1_TLB_MMR_CONTROL)
825
826#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
827#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
828#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
829#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
830#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
831#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
832#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
833#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
834#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
835#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
836#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
837#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
838
839#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
840#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
841#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
842#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
843#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
844#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
845#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
846#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
847#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54
848#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56
849#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60
850#define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
851#define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
852#define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
853#define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
854#define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
855#define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
856#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
857#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
858#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL
859#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL
860#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
861
862#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
863#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
864#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
865#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
866#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
867#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
868#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
869#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48
870#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52
871#define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
872#define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
873#define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
874#define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
875#define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
876#define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
877#define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
878#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL
879#define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL
880
881union uvh_gr1_tlb_mmr_control_u {
882 unsigned long v;
883 struct uvh_gr1_tlb_mmr_control_s {
884 unsigned long index:12; /* RW */
885 unsigned long mem_sel:2; /* RW */
886 unsigned long rsvd_14_15:2;
887 unsigned long auto_valid_en:1; /* RW */
888 unsigned long rsvd_17_19:3;
889 unsigned long mmr_hash_index_en:1; /* RW */
890 unsigned long rsvd_21_29:9;
891 unsigned long mmr_write:1; /* WP */
892 unsigned long mmr_read:1; /* WP */
893 unsigned long rsvd_32_63:32;
894 } s;
895 struct uv1h_gr1_tlb_mmr_control_s {
896 unsigned long index:12; /* RW */
897 unsigned long mem_sel:2; /* RW */
898 unsigned long rsvd_14_15:2;
899 unsigned long auto_valid_en:1; /* RW */
900 unsigned long rsvd_17_19:3;
901 unsigned long mmr_hash_index_en:1; /* RW */
902 unsigned long rsvd_21_29:9;
903 unsigned long mmr_write:1; /* WP */
904 unsigned long mmr_read:1; /* WP */
905 unsigned long rsvd_32_47:16;
906 unsigned long mmr_inj_con:1; /* RW */
907 unsigned long rsvd_49_51:3;
908 unsigned long mmr_inj_tlbram:1; /* RW */
909 unsigned long rsvd_53:1;
910 unsigned long mmr_inj_tlbpgsize:1; /* RW */
911 unsigned long rsvd_55:1;
912 unsigned long mmr_inj_tlbrreg:1; /* RW */
913 unsigned long rsvd_57_59:3;
914 unsigned long mmr_inj_tlblruv:1; /* RW */
915 unsigned long rsvd_61_63:3;
916 } s1;
917 struct uv2h_gr1_tlb_mmr_control_s {
918 unsigned long index:12; /* RW */
919 unsigned long mem_sel:2; /* RW */
920 unsigned long rsvd_14_15:2;
921 unsigned long auto_valid_en:1; /* RW */
922 unsigned long rsvd_17_19:3;
923 unsigned long mmr_hash_index_en:1; /* RW */
924 unsigned long rsvd_21_29:9;
925 unsigned long mmr_write:1; /* WP */
926 unsigned long mmr_read:1; /* WP */
927 unsigned long mmr_op_done:1; /* RW */
928 unsigned long rsvd_33_47:15;
929 unsigned long mmr_inj_con:1; /* RW */
930 unsigned long rsvd_49_51:3;
931 unsigned long mmr_inj_tlbram:1; /* RW */
932 unsigned long rsvd_53_63:11;
933 } s2;
934};
935
936/* ========================================================================= */
937/* UVH_GR1_TLB_MMR_READ_DATA_HI */
938/* ========================================================================= */
939#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
940#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
941#define UVH_GR1_TLB_MMR_READ_DATA_HI (is_uv1_hub() ? \
942 UV1H_GR1_TLB_MMR_READ_DATA_HI : \
943 UV2H_GR1_TLB_MMR_READ_DATA_HI)
944
945#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
946#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
947#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
948#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
949#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
950#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
951#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
952#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
953
954union uvh_gr1_tlb_mmr_read_data_hi_u {
955 unsigned long v;
956 struct uvh_gr1_tlb_mmr_read_data_hi_s {
957 unsigned long pfn:41; /* RO */
958 unsigned long gaa:2; /* RO */
959 unsigned long dirty:1; /* RO */
960 unsigned long larger:1; /* RO */
961 unsigned long rsvd_45_63:19;
962 } s;
963};
964
965/* ========================================================================= */
966/* UVH_GR1_TLB_MMR_READ_DATA_LO */
967/* ========================================================================= */
968#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
969#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
970#define UVH_GR1_TLB_MMR_READ_DATA_LO (is_uv1_hub() ? \
971 UV1H_GR1_TLB_MMR_READ_DATA_LO : \
972 UV2H_GR1_TLB_MMR_READ_DATA_LO)
973
974#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
975#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
976#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
977#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
978#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
979#define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
980
981union uvh_gr1_tlb_mmr_read_data_lo_u {
982 unsigned long v;
983 struct uvh_gr1_tlb_mmr_read_data_lo_s {
984 unsigned long vpn:39; /* RO */
985 unsigned long asid:24; /* RO */
986 unsigned long valid:1; /* RO */
987 } s;
645}; 988};
646 989
647/* ========================================================================= */ 990/* ========================================================================= */
648/* UVH_INT_CMPB */ 991/* UVH_INT_CMPB */
649/* ========================================================================= */ 992/* ========================================================================= */
650#define UVH_INT_CMPB 0x22080UL 993#define UVH_INT_CMPB 0x22080UL
651 994
652#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 995#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
653#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 996#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
654 997
655union uvh_int_cmpb_u { 998union uvh_int_cmpb_u {
656 unsigned long v; 999 unsigned long v;
657 struct uvh_int_cmpb_s { 1000 struct uvh_int_cmpb_s {
658 unsigned long real_time_cmpb : 56; /* RW */ 1001 unsigned long real_time_cmpb:56; /* RW */
659 unsigned long rsvd_56_63 : 8; /* */ 1002 unsigned long rsvd_56_63:8;
660 } s; 1003 } s;
661}; 1004};
662 1005
663/* ========================================================================= */ 1006/* ========================================================================= */
664/* UVH_INT_CMPC */ 1007/* UVH_INT_CMPC */
665/* ========================================================================= */ 1008/* ========================================================================= */
666#define UVH_INT_CMPC 0x22100UL 1009#define UVH_INT_CMPC 0x22100UL
667 1010
668#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1011#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
669#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1012#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
670#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT (is_uv1_hub() ? \
671 UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT : \
672 UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
673#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
674#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK 0xffffffffffffffUL
675#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK (is_uv1_hub() ? \
676 UV1H_INT_CMPC_REAL_TIME_CMPC_MASK : \
677 UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
678 1013
679union uvh_int_cmpc_u { 1014union uvh_int_cmpc_u {
680 unsigned long v; 1015 unsigned long v;
681 struct uvh_int_cmpc_s { 1016 struct uvh_int_cmpc_s {
682 unsigned long real_time_cmpc : 56; /* RW */ 1017 unsigned long real_time_cmpc:56; /* RW */
683 unsigned long rsvd_56_63 : 8; /* */ 1018 unsigned long rsvd_56_63:8;
684 } s; 1019 } s;
685}; 1020};
686 1021
687/* ========================================================================= */ 1022/* ========================================================================= */
688/* UVH_INT_CMPD */ 1023/* UVH_INT_CMPD */
689/* ========================================================================= */ 1024/* ========================================================================= */
690#define UVH_INT_CMPD 0x22180UL 1025#define UVH_INT_CMPD 0x22180UL
691 1026
692#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1027#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
693#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1028#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
694#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT (is_uv1_hub() ? \
695 UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT : \
696 UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
697#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
698#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK 0xffffffffffffffUL
699#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK (is_uv1_hub() ? \
700 UV1H_INT_CMPD_REAL_TIME_CMPD_MASK : \
701 UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
702 1029
703union uvh_int_cmpd_u { 1030union uvh_int_cmpd_u {
704 unsigned long v; 1031 unsigned long v;
705 struct uvh_int_cmpd_s { 1032 struct uvh_int_cmpd_s {
706 unsigned long real_time_cmpd : 56; /* RW */ 1033 unsigned long real_time_cmpd:56; /* RW */
707 unsigned long rsvd_56_63 : 8; /* */ 1034 unsigned long rsvd_56_63:8;
708 } s; 1035 } s;
709}; 1036};
710 1037
711/* ========================================================================= */ 1038/* ========================================================================= */
712/* UVH_IPI_INT */ 1039/* UVH_IPI_INT */
713/* ========================================================================= */ 1040/* ========================================================================= */
714#define UVH_IPI_INT 0x60500UL 1041#define UVH_IPI_INT 0x60500UL
715#define UVH_IPI_INT_32 0x348 1042#define UVH_IPI_INT_32 0x348
716 1043
717#define UVH_IPI_INT_VECTOR_SHFT 0 1044#define UVH_IPI_INT_VECTOR_SHFT 0
718#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1045#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
719#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1046#define UVH_IPI_INT_DESTMODE_SHFT 11
720#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1047#define UVH_IPI_INT_APIC_ID_SHFT 16
721#define UVH_IPI_INT_DESTMODE_SHFT 11 1048#define UVH_IPI_INT_SEND_SHFT 63
722#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1049#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
723#define UVH_IPI_INT_APIC_ID_SHFT 16 1050#define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
724#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1051#define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
725#define UVH_IPI_INT_SEND_SHFT 63 1052#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
726#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1053#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
727 1054
728union uvh_ipi_int_u { 1055union uvh_ipi_int_u {
729 unsigned long v; 1056 unsigned long v;
730 struct uvh_ipi_int_s { 1057 struct uvh_ipi_int_s {
731 unsigned long vector_ : 8; /* RW */ 1058 unsigned long vector_:8; /* RW */
732 unsigned long delivery_mode : 3; /* RW */ 1059 unsigned long delivery_mode:3; /* RW */
733 unsigned long destmode : 1; /* RW */ 1060 unsigned long destmode:1; /* RW */
734 unsigned long rsvd_12_15 : 4; /* */ 1061 unsigned long rsvd_12_15:4;
735 unsigned long apic_id : 32; /* RW */ 1062 unsigned long apic_id:32; /* RW */
736 unsigned long rsvd_48_62 : 15; /* */ 1063 unsigned long rsvd_48_62:15;
737 unsigned long send : 1; /* WP */ 1064 unsigned long send:1; /* WP */
738 } s; 1065 } s;
739}; 1066};
740 1067
741/* ========================================================================= */ 1068/* ========================================================================= */
742/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1069/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
743/* ========================================================================= */ 1070/* ========================================================================= */
744#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1071#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
745#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1072#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
746 1073
747#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1074#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
748#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
749#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1075#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1076#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
750#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1077#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
751 1078
752union uvh_lb_bau_intd_payload_queue_first_u { 1079union uvh_lb_bau_intd_payload_queue_first_u {
753 unsigned long v; 1080 unsigned long v;
754 struct uvh_lb_bau_intd_payload_queue_first_s { 1081 struct uvh_lb_bau_intd_payload_queue_first_s {
755 unsigned long rsvd_0_3: 4; /* */ 1082 unsigned long rsvd_0_3:4;
756 unsigned long address : 39; /* RW */ 1083 unsigned long address:39; /* RW */
757 unsigned long rsvd_43_48: 6; /* */ 1084 unsigned long rsvd_43_48:6;
758 unsigned long node_id : 14; /* RW */ 1085 unsigned long node_id:14; /* RW */
759 unsigned long rsvd_63 : 1; /* */ 1086 unsigned long rsvd_63:1;
760 } s; 1087 } s;
761}; 1088};
762 1089
763/* ========================================================================= */ 1090/* ========================================================================= */
764/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1091/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
765/* ========================================================================= */ 1092/* ========================================================================= */
766#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1093#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
767#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1094#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
768 1095
769#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1096#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
770#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1097#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
771 1098
772union uvh_lb_bau_intd_payload_queue_last_u { 1099union uvh_lb_bau_intd_payload_queue_last_u {
773 unsigned long v; 1100 unsigned long v;
774 struct uvh_lb_bau_intd_payload_queue_last_s { 1101 struct uvh_lb_bau_intd_payload_queue_last_s {
775 unsigned long rsvd_0_3: 4; /* */ 1102 unsigned long rsvd_0_3:4;
776 unsigned long address : 39; /* RW */ 1103 unsigned long address:39; /* RW */
777 unsigned long rsvd_43_63: 21; /* */ 1104 unsigned long rsvd_43_63:21;
778 } s; 1105 } s;
779}; 1106};
780 1107
781/* ========================================================================= */ 1108/* ========================================================================= */
782/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1109/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
783/* ========================================================================= */ 1110/* ========================================================================= */
784#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1111#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
785#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1112#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
786 1113
787#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1114#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
788#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1115#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
789 1116
790union uvh_lb_bau_intd_payload_queue_tail_u { 1117union uvh_lb_bau_intd_payload_queue_tail_u {
791 unsigned long v; 1118 unsigned long v;
792 struct uvh_lb_bau_intd_payload_queue_tail_s { 1119 struct uvh_lb_bau_intd_payload_queue_tail_s {
793 unsigned long rsvd_0_3: 4; /* */ 1120 unsigned long rsvd_0_3:4;
794 unsigned long address : 39; /* RW */ 1121 unsigned long address:39; /* RW */
795 unsigned long rsvd_43_63: 21; /* */ 1122 unsigned long rsvd_43_63:21;
796 } s; 1123 } s;
797}; 1124};
798 1125
799/* ========================================================================= */ 1126/* ========================================================================= */
800/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1127/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
801/* ========================================================================= */ 1128/* ========================================================================= */
802#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1129#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
803#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1130#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
804 1131
805#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1132#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
806#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
807#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1133#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
808#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
809#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1134#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
810#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
811#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1135#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
812#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
813#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1136#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
814#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
815#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1137#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
816#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
817#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1138#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
818#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
819#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1139#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
820#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
821#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1140#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
822#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
823#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1141#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
824#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
825#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1142#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
826#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
827#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1143#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
828#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
829#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1144#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
830#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
831#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1145#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
832#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
833#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1146#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
834#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
835#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1147#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
1148#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
1149#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
1150#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
1151#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
1152#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
1153#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
1154#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
1155#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
1156#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
1157#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
1158#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
1159#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
1160#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
1161#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
1162#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
836#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1163#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
837 1164
838union uvh_lb_bau_intd_software_acknowledge_u { 1165union uvh_lb_bau_intd_software_acknowledge_u {
839 unsigned long v; 1166 unsigned long v;
840 struct uvh_lb_bau_intd_software_acknowledge_s { 1167 struct uvh_lb_bau_intd_software_acknowledge_s {
841 unsigned long pending_0 : 1; /* RW, W1C */ 1168 unsigned long pending_0:1; /* RW, W1C */
842 unsigned long pending_1 : 1; /* RW, W1C */ 1169 unsigned long pending_1:1; /* RW, W1C */
843 unsigned long pending_2 : 1; /* RW, W1C */ 1170 unsigned long pending_2:1; /* RW, W1C */
844 unsigned long pending_3 : 1; /* RW, W1C */ 1171 unsigned long pending_3:1; /* RW, W1C */
845 unsigned long pending_4 : 1; /* RW, W1C */ 1172 unsigned long pending_4:1; /* RW, W1C */
846 unsigned long pending_5 : 1; /* RW, W1C */ 1173 unsigned long pending_5:1; /* RW, W1C */
847 unsigned long pending_6 : 1; /* RW, W1C */ 1174 unsigned long pending_6:1; /* RW, W1C */
848 unsigned long pending_7 : 1; /* RW, W1C */ 1175 unsigned long pending_7:1; /* RW, W1C */
849 unsigned long timeout_0 : 1; /* RW, W1C */ 1176 unsigned long timeout_0:1; /* RW, W1C */
850 unsigned long timeout_1 : 1; /* RW, W1C */ 1177 unsigned long timeout_1:1; /* RW, W1C */
851 unsigned long timeout_2 : 1; /* RW, W1C */ 1178 unsigned long timeout_2:1; /* RW, W1C */
852 unsigned long timeout_3 : 1; /* RW, W1C */ 1179 unsigned long timeout_3:1; /* RW, W1C */
853 unsigned long timeout_4 : 1; /* RW, W1C */ 1180 unsigned long timeout_4:1; /* RW, W1C */
854 unsigned long timeout_5 : 1; /* RW, W1C */ 1181 unsigned long timeout_5:1; /* RW, W1C */
855 unsigned long timeout_6 : 1; /* RW, W1C */ 1182 unsigned long timeout_6:1; /* RW, W1C */
856 unsigned long timeout_7 : 1; /* RW, W1C */ 1183 unsigned long timeout_7:1; /* RW, W1C */
857 unsigned long rsvd_16_63: 48; /* */ 1184 unsigned long rsvd_16_63:48;
858 } s; 1185 } s;
859}; 1186};
860 1187
861/* ========================================================================= */ 1188/* ========================================================================= */
862/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 1189/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
863/* ========================================================================= */ 1190/* ========================================================================= */
864#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 1191#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
865#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 1192#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
866 1193
867/* ========================================================================= */ 1194/* ========================================================================= */
868/* UVH_LB_BAU_MISC_CONTROL */ 1195/* UVH_LB_BAU_MISC_CONTROL */
869/* ========================================================================= */ 1196/* ========================================================================= */
870#define UVH_LB_BAU_MISC_CONTROL 0x320170UL 1197#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
871#define UVH_LB_BAU_MISC_CONTROL_32 0xa10 1198#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
872 1199
873#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1200#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
874#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1201#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
875#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1202#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
876#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1203#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
877#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
878#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
879#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
880#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
881#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1204#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
882#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
883#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1205#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
884#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
885#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1206#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
886#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
887#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1207#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
888#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
889#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1208#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
890#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
891#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1209#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
892#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
893#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1210#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
894#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
895#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1211#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
896#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
897#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1212#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
898#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
899#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1213#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
900#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
901#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1214#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1215#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1216#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1217#define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1218#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1219#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1220#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1221#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1222#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1223#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1224#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1225#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1226#define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1227#define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1228#define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
902#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1229#define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
903 1230
904#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1231#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
905#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1232#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
906#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1233#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
907#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1234#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
908#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
909#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
910#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
911#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
912#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1235#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
913#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
914#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1236#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
915#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
916#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1237#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
917#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
918#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1238#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
919#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
920#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1239#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
921#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
922#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1240#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
923#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
924#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1241#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
925#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
926#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1242#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
927#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
928#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1243#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
929#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
930#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1244#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
931#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
932#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1245#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
1246#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1247#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1248#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1249#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1250#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1251#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1252#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1253#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1254#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1255#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1256#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1257#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1258#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1259#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1260#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
933#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1261#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
934#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1262#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
935#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1263
936 1264#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
937#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1265#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
938#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1266#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
939#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1267#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
940#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
941#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
942#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
943#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
944#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
945#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1268#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
946#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
947#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1269#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
948#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
949#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1270#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
950#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
951#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1271#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
952#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
953#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1272#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
954#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
955#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1273#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
956#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
957#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1274#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
958#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
959#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1275#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
960#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
961#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1276#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
962#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
963#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1277#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
964#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
965#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1278#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
966#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
967#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1279#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
968#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1280#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
969#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
970#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
971#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1281#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
972#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
973#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1282#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
974#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
975#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1283#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
976#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
977#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1284#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
978#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
979#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1285#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
1286#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
1287#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
1288#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
1289#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
1290#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1291#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1292#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1293#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1294#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1295#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1296#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1297#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
1298#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
1299#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
1300#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
1301#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
1302#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
1303#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
1304#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
1305#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
1306#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
1307#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
980#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1308#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
981#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1309#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
982#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
983 1310
984union uvh_lb_bau_misc_control_u { 1311union uvh_lb_bau_misc_control_u {
985 unsigned long v; 1312 unsigned long v;
986 struct uvh_lb_bau_misc_control_s { 1313 struct uvh_lb_bau_misc_control_s {
987 unsigned long rejection_delay : 8; /* RW */ 1314 unsigned long rejection_delay:8; /* RW */
988 unsigned long apic_mode : 1; /* RW */ 1315 unsigned long apic_mode:1; /* RW */
989 unsigned long force_broadcast : 1; /* RW */ 1316 unsigned long force_broadcast:1; /* RW */
990 unsigned long force_lock_nop : 1; /* RW */ 1317 unsigned long force_lock_nop:1; /* RW */
991 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1318 unsigned long qpi_agent_presence_vector:3; /* RW */
992 unsigned long descriptor_fetch_mode : 1; /* RW */ 1319 unsigned long descriptor_fetch_mode:1; /* RW */
993 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1320 unsigned long enable_intd_soft_ack_mode:1; /* RW */
994 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1321 unsigned long intd_soft_ack_timeout_period:4; /* RW */
995 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1322 unsigned long enable_dual_mapping_mode:1; /* RW */
996 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1323 unsigned long vga_io_port_decode_enable:1; /* RW */
997 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1324 unsigned long vga_io_port_16_bit_decode:1; /* RW */
998 unsigned long suppress_dest_registration : 1; /* RW */ 1325 unsigned long suppress_dest_registration:1; /* RW */
999 unsigned long programmed_initial_priority : 3; /* RW */ 1326 unsigned long programmed_initial_priority:3; /* RW */
1000 unsigned long use_incoming_priority : 1; /* RW */ 1327 unsigned long use_incoming_priority:1; /* RW */
1001 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1328 unsigned long enable_programmed_initial_priority:1;/* RW */
1002 unsigned long rsvd_29_63 : 35; 1329 unsigned long rsvd_29_63:35;
1003 } s; 1330 } s;
1004 struct uv1h_lb_bau_misc_control_s { 1331 struct uv1h_lb_bau_misc_control_s {
1005 unsigned long rejection_delay : 8; /* RW */ 1332 unsigned long rejection_delay:8; /* RW */
1006 unsigned long apic_mode : 1; /* RW */ 1333 unsigned long apic_mode:1; /* RW */
1007 unsigned long force_broadcast : 1; /* RW */ 1334 unsigned long force_broadcast:1; /* RW */
1008 unsigned long force_lock_nop : 1; /* RW */ 1335 unsigned long force_lock_nop:1; /* RW */
1009 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1336 unsigned long qpi_agent_presence_vector:3; /* RW */
1010 unsigned long descriptor_fetch_mode : 1; /* RW */ 1337 unsigned long descriptor_fetch_mode:1; /* RW */
1011 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1338 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1012 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1339 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1013 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1340 unsigned long enable_dual_mapping_mode:1; /* RW */
1014 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1341 unsigned long vga_io_port_decode_enable:1; /* RW */
1015 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1342 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1016 unsigned long suppress_dest_registration : 1; /* RW */ 1343 unsigned long suppress_dest_registration:1; /* RW */
1017 unsigned long programmed_initial_priority : 3; /* RW */ 1344 unsigned long programmed_initial_priority:3; /* RW */
1018 unsigned long use_incoming_priority : 1; /* RW */ 1345 unsigned long use_incoming_priority:1; /* RW */
1019 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1346 unsigned long enable_programmed_initial_priority:1;/* RW */
1020 unsigned long rsvd_29_47 : 19; /* */ 1347 unsigned long rsvd_29_47:19;
1021 unsigned long fun : 16; /* RW */ 1348 unsigned long fun:16; /* RW */
1022 } s1; 1349 } s1;
1023 struct uv2h_lb_bau_misc_control_s { 1350 struct uv2h_lb_bau_misc_control_s {
1024 unsigned long rejection_delay : 8; /* RW */ 1351 unsigned long rejection_delay:8; /* RW */
1025 unsigned long apic_mode : 1; /* RW */ 1352 unsigned long apic_mode:1; /* RW */
1026 unsigned long force_broadcast : 1; /* RW */ 1353 unsigned long force_broadcast:1; /* RW */
1027 unsigned long force_lock_nop : 1; /* RW */ 1354 unsigned long force_lock_nop:1; /* RW */
1028 unsigned long qpi_agent_presence_vector : 3; /* RW */ 1355 unsigned long qpi_agent_presence_vector:3; /* RW */
1029 unsigned long descriptor_fetch_mode : 1; /* RW */ 1356 unsigned long descriptor_fetch_mode:1; /* RW */
1030 unsigned long enable_intd_soft_ack_mode : 1; /* RW */ 1357 unsigned long enable_intd_soft_ack_mode:1; /* RW */
1031 unsigned long intd_soft_ack_timeout_period : 4; /* RW */ 1358 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1032 unsigned long enable_dual_mapping_mode : 1; /* RW */ 1359 unsigned long enable_dual_mapping_mode:1; /* RW */
1033 unsigned long vga_io_port_decode_enable : 1; /* RW */ 1360 unsigned long vga_io_port_decode_enable:1; /* RW */
1034 unsigned long vga_io_port_16_bit_decode : 1; /* RW */ 1361 unsigned long vga_io_port_16_bit_decode:1; /* RW */
1035 unsigned long suppress_dest_registration : 1; /* RW */ 1362 unsigned long suppress_dest_registration:1; /* RW */
1036 unsigned long programmed_initial_priority : 3; /* RW */ 1363 unsigned long programmed_initial_priority:3; /* RW */
1037 unsigned long use_incoming_priority : 1; /* RW */ 1364 unsigned long use_incoming_priority:1; /* RW */
1038 unsigned long enable_programmed_initial_priority : 1; /* RW */ 1365 unsigned long enable_programmed_initial_priority:1;/* RW */
1039 unsigned long enable_automatic_apic_mode_selection : 1; /* RW */ 1366 unsigned long enable_automatic_apic_mode_selection:1;/* RW */
1040 unsigned long apic_mode_status : 1; /* RO */ 1367 unsigned long apic_mode_status:1; /* RO */
1041 unsigned long suppress_interrupts_to_self : 1; /* RW */ 1368 unsigned long suppress_interrupts_to_self:1; /* RW */
1042 unsigned long enable_lock_based_system_flush : 1; /* RW */ 1369 unsigned long enable_lock_based_system_flush:1;/* RW */
1043 unsigned long enable_extended_sb_status : 1; /* RW */ 1370 unsigned long enable_extended_sb_status:1; /* RW */
1044 unsigned long suppress_int_prio_udt_to_self : 1; /* RW */ 1371 unsigned long suppress_int_prio_udt_to_self:1;/* RW */
1045 unsigned long use_legacy_descriptor_formats : 1; /* RW */ 1372 unsigned long use_legacy_descriptor_formats:1;/* RW */
1046 unsigned long rsvd_36_47 : 12; /* */ 1373 unsigned long rsvd_36_47:12;
1047 unsigned long fun : 16; /* RW */ 1374 unsigned long fun:16; /* RW */
1048 } s2; 1375 } s2;
1049}; 1376};
1050 1377
1051/* ========================================================================= */ 1378/* ========================================================================= */
1052/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1379/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
1053/* ========================================================================= */ 1380/* ========================================================================= */
1054#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1381#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1055#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1382#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
1056 1383
1057#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1384#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
1058#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 1385#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
1059#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 1386#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
1060#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 1387#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
1061#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 1388#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
1062#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 1389#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
1063 1390
1064union uvh_lb_bau_sb_activation_control_u { 1391union uvh_lb_bau_sb_activation_control_u {
1065 unsigned long v; 1392 unsigned long v;
1066 struct uvh_lb_bau_sb_activation_control_s { 1393 struct uvh_lb_bau_sb_activation_control_s {
1067 unsigned long index : 6; /* RW */ 1394 unsigned long index:6; /* RW */
1068 unsigned long rsvd_6_61: 56; /* */ 1395 unsigned long rsvd_6_61:56;
1069 unsigned long push : 1; /* WP */ 1396 unsigned long push:1; /* WP */
1070 unsigned long init : 1; /* WP */ 1397 unsigned long init:1; /* WP */
1071 } s; 1398 } s;
1072}; 1399};
1073 1400
1074/* ========================================================================= */ 1401/* ========================================================================= */
1075/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1402/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
1076/* ========================================================================= */ 1403/* ========================================================================= */
1077#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1404#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1078#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1405#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
1079 1406
1080#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1407#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
1081#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1408#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
1082 1409
1083union uvh_lb_bau_sb_activation_status_0_u { 1410union uvh_lb_bau_sb_activation_status_0_u {
1084 unsigned long v; 1411 unsigned long v;
1085 struct uvh_lb_bau_sb_activation_status_0_s { 1412 struct uvh_lb_bau_sb_activation_status_0_s {
1086 unsigned long status : 64; /* RW */ 1413 unsigned long status:64; /* RW */
1087 } s; 1414 } s;
1088}; 1415};
1089 1416
1090/* ========================================================================= */ 1417/* ========================================================================= */
1091/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1418/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
1092/* ========================================================================= */ 1419/* ========================================================================= */
1093#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1420#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1094#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1421#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
1095 1422
1096#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1423#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
1097#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1424#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
1098 1425
1099union uvh_lb_bau_sb_activation_status_1_u { 1426union uvh_lb_bau_sb_activation_status_1_u {
1100 unsigned long v; 1427 unsigned long v;
1101 struct uvh_lb_bau_sb_activation_status_1_s { 1428 struct uvh_lb_bau_sb_activation_status_1_s {
1102 unsigned long status : 64; /* RW */ 1429 unsigned long status:64; /* RW */
1103 } s; 1430 } s;
1104}; 1431};
1105 1432
1106/* ========================================================================= */ 1433/* ========================================================================= */
1107/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1434/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
1108/* ========================================================================= */ 1435/* ========================================================================= */
1109#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1436#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1110#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1437#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
1111 1438
1112#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1439#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1113#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 1440#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
1114#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 1441#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1115#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 1442#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
1116 1443
1117union uvh_lb_bau_sb_descriptor_base_u { 1444union uvh_lb_bau_sb_descriptor_base_u {
1118 unsigned long v; 1445 unsigned long v;
1119 struct uvh_lb_bau_sb_descriptor_base_s { 1446 struct uvh_lb_bau_sb_descriptor_base_s {
1120 unsigned long rsvd_0_11 : 12; /* */ 1447 unsigned long rsvd_0_11:12;
1121 unsigned long page_address : 31; /* RW */ 1448 unsigned long page_address:31; /* RW */
1122 unsigned long rsvd_43_48 : 6; /* */ 1449 unsigned long rsvd_43_48:6;
1123 unsigned long node_id : 14; /* RW */ 1450 unsigned long node_id:14; /* RW */
1124 unsigned long rsvd_63 : 1; /* */ 1451 unsigned long rsvd_63:1;
1125 } s; 1452 } s;
1126}; 1453};
1127 1454
1128/* ========================================================================= */ 1455/* ========================================================================= */
1129/* UVH_NODE_ID */ 1456/* UVH_NODE_ID */
1130/* ========================================================================= */ 1457/* ========================================================================= */
1131#define UVH_NODE_ID 0x0UL 1458#define UVH_NODE_ID 0x0UL
1132 1459
1133#define UVH_NODE_ID_FORCE1_SHFT 0 1460#define UVH_NODE_ID_FORCE1_SHFT 0
1134#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1461#define UVH_NODE_ID_MANUFACTURER_SHFT 1
1135#define UVH_NODE_ID_MANUFACTURER_SHFT 1 1462#define UVH_NODE_ID_PART_NUMBER_SHFT 12
1136#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1463#define UVH_NODE_ID_REVISION_SHFT 28
1137#define UVH_NODE_ID_PART_NUMBER_SHFT 12 1464#define UVH_NODE_ID_NODE_ID_SHFT 32
1138#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1465#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1139#define UVH_NODE_ID_REVISION_SHFT 28 1466#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1140#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1467#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1141#define UVH_NODE_ID_NODE_ID_SHFT 32 1468#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1142#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1469#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1143 1470
1144#define UV1H_NODE_ID_FORCE1_SHFT 0 1471#define UV1H_NODE_ID_FORCE1_SHFT 0
1145#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1472#define UV1H_NODE_ID_MANUFACTURER_SHFT 1
1146#define UV1H_NODE_ID_MANUFACTURER_SHFT 1 1473#define UV1H_NODE_ID_PART_NUMBER_SHFT 12
1147#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1474#define UV1H_NODE_ID_REVISION_SHFT 28
1148#define UV1H_NODE_ID_PART_NUMBER_SHFT 12 1475#define UV1H_NODE_ID_NODE_ID_SHFT 32
1149#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1476#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
1150#define UV1H_NODE_ID_REVISION_SHFT 28 1477#define UV1H_NODE_ID_NI_PORT_SHFT 56
1151#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1478#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1152#define UV1H_NODE_ID_NODE_ID_SHFT 32 1479#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1153#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1480#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1154#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 1481#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1155#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 1482#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1156#define UV1H_NODE_ID_NI_PORT_SHFT 56 1483#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
1157#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 1484#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
1158 1485
1159#define UV2H_NODE_ID_FORCE1_SHFT 0 1486#define UV2H_NODE_ID_FORCE1_SHFT 0
1160#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 1487#define UV2H_NODE_ID_MANUFACTURER_SHFT 1
1161#define UV2H_NODE_ID_MANUFACTURER_SHFT 1 1488#define UV2H_NODE_ID_PART_NUMBER_SHFT 12
1162#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 1489#define UV2H_NODE_ID_REVISION_SHFT 28
1163#define UV2H_NODE_ID_PART_NUMBER_SHFT 12 1490#define UV2H_NODE_ID_NODE_ID_SHFT 32
1164#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 1491#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
1165#define UV2H_NODE_ID_REVISION_SHFT 28 1492#define UV2H_NODE_ID_NI_PORT_SHFT 57
1166#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 1493#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
1167#define UV2H_NODE_ID_NODE_ID_SHFT 32 1494#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
1168#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 1495#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
1169#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 1496#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
1170#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 1497#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
1171#define UV2H_NODE_ID_NI_PORT_SHFT 57 1498#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
1172#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 1499#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
1173 1500
1174union uvh_node_id_u { 1501union uvh_node_id_u {
1175 unsigned long v; 1502 unsigned long v;
1176 struct uvh_node_id_s { 1503 struct uvh_node_id_s {
1177 unsigned long force1 : 1; /* RO */ 1504 unsigned long force1:1; /* RO */
1178 unsigned long manufacturer : 11; /* RO */ 1505 unsigned long manufacturer:11; /* RO */
1179 unsigned long part_number : 16; /* RO */ 1506 unsigned long part_number:16; /* RO */
1180 unsigned long revision : 4; /* RO */ 1507 unsigned long revision:4; /* RO */
1181 unsigned long node_id : 15; /* RW */ 1508 unsigned long node_id:15; /* RW */
1182 unsigned long rsvd_47_63 : 17; 1509 unsigned long rsvd_47_63:17;
1183 } s; 1510 } s;
1184 struct uv1h_node_id_s { 1511 struct uv1h_node_id_s {
1185 unsigned long force1 : 1; /* RO */ 1512 unsigned long force1:1; /* RO */
1186 unsigned long manufacturer : 11; /* RO */ 1513 unsigned long manufacturer:11; /* RO */
1187 unsigned long part_number : 16; /* RO */ 1514 unsigned long part_number:16; /* RO */
1188 unsigned long revision : 4; /* RO */ 1515 unsigned long revision:4; /* RO */
1189 unsigned long node_id : 15; /* RW */ 1516 unsigned long node_id:15; /* RW */
1190 unsigned long rsvd_47 : 1; /* */ 1517 unsigned long rsvd_47:1;
1191 unsigned long nodes_per_bit : 7; /* RW */ 1518 unsigned long nodes_per_bit:7; /* RW */
1192 unsigned long rsvd_55 : 1; /* */ 1519 unsigned long rsvd_55:1;
1193 unsigned long ni_port : 4; /* RO */ 1520 unsigned long ni_port:4; /* RO */
1194 unsigned long rsvd_60_63 : 4; /* */ 1521 unsigned long rsvd_60_63:4;
1195 } s1; 1522 } s1;
1196 struct uv2h_node_id_s { 1523 struct uv2h_node_id_s {
1197 unsigned long force1 : 1; /* RO */ 1524 unsigned long force1:1; /* RO */
1198 unsigned long manufacturer : 11; /* RO */ 1525 unsigned long manufacturer:11; /* RO */
1199 unsigned long part_number : 16; /* RO */ 1526 unsigned long part_number:16; /* RO */
1200 unsigned long revision : 4; /* RO */ 1527 unsigned long revision:4; /* RO */
1201 unsigned long node_id : 15; /* RW */ 1528 unsigned long node_id:15; /* RW */
1202 unsigned long rsvd_47_49 : 3; /* */ 1529 unsigned long rsvd_47_49:3;
1203 unsigned long nodes_per_bit : 7; /* RO */ 1530 unsigned long nodes_per_bit:7; /* RO */
1204 unsigned long ni_port : 5; /* RO */ 1531 unsigned long ni_port:5; /* RO */
1205 unsigned long rsvd_62_63 : 2; /* */ 1532 unsigned long rsvd_62_63:2;
1206 } s2; 1533 } s2;
1207}; 1534};
1208 1535
1209/* ========================================================================= */ 1536/* ========================================================================= */
1210/* UVH_NODE_PRESENT_TABLE */ 1537/* UVH_NODE_PRESENT_TABLE */
1211/* ========================================================================= */ 1538/* ========================================================================= */
1212#define UVH_NODE_PRESENT_TABLE 0x1400UL 1539#define UVH_NODE_PRESENT_TABLE 0x1400UL
1213#define UVH_NODE_PRESENT_TABLE_DEPTH 16 1540#define UVH_NODE_PRESENT_TABLE_DEPTH 16
1214 1541
1215#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 1542#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
1216#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 1543#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
1217 1544
1218union uvh_node_present_table_u { 1545union uvh_node_present_table_u {
1219 unsigned long v; 1546 unsigned long v;
1220 struct uvh_node_present_table_s { 1547 struct uvh_node_present_table_s {
1221 unsigned long nodes : 64; /* RW */ 1548 unsigned long nodes:64; /* RW */
1222 } s; 1549 } s;
1223}; 1550};
1224 1551
1225/* ========================================================================= */ 1552/* ========================================================================= */
1226/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 1553/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
1227/* ========================================================================= */ 1554/* ========================================================================= */
1228#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 1555#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
1229 1556
1230#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 1557#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
1231#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1232#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 1558#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
1233#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1234#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 1559#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
1560#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
1561#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
1235#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 1562#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
1236 1563
1237union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 1564union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
1238 unsigned long v; 1565 unsigned long v;
1239 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 1566 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
1240 unsigned long rsvd_0_23: 24; /* */ 1567 unsigned long rsvd_0_23:24;
1241 unsigned long base : 8; /* RW */ 1568 unsigned long base:8; /* RW */
1242 unsigned long rsvd_32_47: 16; /* */ 1569 unsigned long rsvd_32_47:16;
1243 unsigned long m_alias : 5; /* RW */ 1570 unsigned long m_alias:5; /* RW */
1244 unsigned long rsvd_53_62: 10; /* */ 1571 unsigned long rsvd_53_62:10;
1245 unsigned long enable : 1; /* RW */ 1572 unsigned long enable:1; /* RW */
1246 } s; 1573 } s;
1247}; 1574};
1248 1575
1249/* ========================================================================= */ 1576/* ========================================================================= */
1250/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 1577/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
1251/* ========================================================================= */ 1578/* ========================================================================= */
1252#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 1579#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
1253 1580
1254#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 1581#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
1255#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1256#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 1582#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
1257#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1258#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 1583#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
1584#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
1585#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
1259#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 1586#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
1260 1587
1261union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 1588union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
1262 unsigned long v; 1589 unsigned long v;
1263 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 1590 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
1264 unsigned long rsvd_0_23: 24; /* */ 1591 unsigned long rsvd_0_23:24;
1265 unsigned long base : 8; /* RW */ 1592 unsigned long base:8; /* RW */
1266 unsigned long rsvd_32_47: 16; /* */ 1593 unsigned long rsvd_32_47:16;
1267 unsigned long m_alias : 5; /* RW */ 1594 unsigned long m_alias:5; /* RW */
1268 unsigned long rsvd_53_62: 10; /* */ 1595 unsigned long rsvd_53_62:10;
1269 unsigned long enable : 1; /* RW */ 1596 unsigned long enable:1; /* RW */
1270 } s; 1597 } s;
1271}; 1598};
1272 1599
1273/* ========================================================================= */ 1600/* ========================================================================= */
1274/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 1601/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
1275/* ========================================================================= */ 1602/* ========================================================================= */
1276#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 1603#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
1277 1604
1278#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 1605#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
1279#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1280#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 1606#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
1281#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1282#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 1607#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
1608#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
1609#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
1283#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 1610#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
1284 1611
1285union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 1612union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
1286 unsigned long v; 1613 unsigned long v;
1287 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 1614 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
1288 unsigned long rsvd_0_23: 24; /* */ 1615 unsigned long rsvd_0_23:24;
1289 unsigned long base : 8; /* RW */ 1616 unsigned long base:8; /* RW */
1290 unsigned long rsvd_32_47: 16; /* */ 1617 unsigned long rsvd_32_47:16;
1291 unsigned long m_alias : 5; /* RW */ 1618 unsigned long m_alias:5; /* RW */
1292 unsigned long rsvd_53_62: 10; /* */ 1619 unsigned long rsvd_53_62:10;
1293 unsigned long enable : 1; /* RW */ 1620 unsigned long enable:1; /* RW */
1294 } s; 1621 } s;
1295}; 1622};
1296 1623
1297/* ========================================================================= */ 1624/* ========================================================================= */
1298/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 1625/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
1299/* ========================================================================= */ 1626/* ========================================================================= */
1300#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 1627#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
1301 1628
1302#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 1629#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
1303#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1630#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1304 1631
1305union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 1632union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
1306 unsigned long v; 1633 unsigned long v;
1307 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 1634 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
1308 unsigned long rsvd_0_23 : 24; /* */ 1635 unsigned long rsvd_0_23:24;
1309 unsigned long dest_base : 22; /* RW */ 1636 unsigned long dest_base:22; /* RW */
1310 unsigned long rsvd_46_63: 18; /* */ 1637 unsigned long rsvd_46_63:18;
1311 } s; 1638 } s;
1312}; 1639};
1313 1640
1314/* ========================================================================= */ 1641/* ========================================================================= */
1315/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 1642/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
1316/* ========================================================================= */ 1643/* ========================================================================= */
1317#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 1644#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
1318 1645
1319#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 1646#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
1320#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1647#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1321 1648
1322union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 1649union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
1323 unsigned long v; 1650 unsigned long v;
1324 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 1651 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
1325 unsigned long rsvd_0_23 : 24; /* */ 1652 unsigned long rsvd_0_23:24;
1326 unsigned long dest_base : 22; /* RW */ 1653 unsigned long dest_base:22; /* RW */
1327 unsigned long rsvd_46_63: 18; /* */ 1654 unsigned long rsvd_46_63:18;
1328 } s; 1655 } s;
1329}; 1656};
1330 1657
1331/* ========================================================================= */ 1658/* ========================================================================= */
1332/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 1659/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
1333/* ========================================================================= */ 1660/* ========================================================================= */
1334#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 1661#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
1335 1662
1336#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 1663#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
1337#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 1664#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
1338 1665
1339union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 1666union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
1340 unsigned long v; 1667 unsigned long v;
1341 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 1668 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
1342 unsigned long rsvd_0_23 : 24; /* */ 1669 unsigned long rsvd_0_23:24;
1343 unsigned long dest_base : 22; /* RW */ 1670 unsigned long dest_base:22; /* RW */
1344 unsigned long rsvd_46_63: 18; /* */ 1671 unsigned long rsvd_46_63:18;
1345 } s; 1672 } s;
1346}; 1673};
1347 1674
1348/* ========================================================================= */ 1675/* ========================================================================= */
1349/* UVH_RH_GAM_CONFIG_MMR */ 1676/* UVH_RH_GAM_CONFIG_MMR */
1350/* ========================================================================= */ 1677/* ========================================================================= */
1351#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL 1678#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
1352 1679
1353#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1680#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1354#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1681#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1355#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1682#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1356#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1683#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1357 1684
1358#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1685#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1359#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1686#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1360#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1687#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
1361#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1688#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1362#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 1689#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1363#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 1690#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
1364 1691
1365#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 1692#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
1366#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 1693#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
1367#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 1694#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
1368#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 1695#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
1369 1696
1370union uvh_rh_gam_config_mmr_u { 1697union uvh_rh_gam_config_mmr_u {
1371 unsigned long v; 1698 unsigned long v;
1372 struct uvh_rh_gam_config_mmr_s { 1699 struct uvh_rh_gam_config_mmr_s {
1373 unsigned long m_skt : 6; /* RW */ 1700 unsigned long m_skt:6; /* RW */
1374 unsigned long n_skt : 4; /* RW */ 1701 unsigned long n_skt:4; /* RW */
1375 unsigned long rsvd_10_63 : 54; 1702 unsigned long rsvd_10_63:54;
1376 } s; 1703 } s;
1377 struct uv1h_rh_gam_config_mmr_s { 1704 struct uv1h_rh_gam_config_mmr_s {
1378 unsigned long m_skt : 6; /* RW */ 1705 unsigned long m_skt:6; /* RW */
1379 unsigned long n_skt : 4; /* RW */ 1706 unsigned long n_skt:4; /* RW */
1380 unsigned long rsvd_10_11: 2; /* */ 1707 unsigned long rsvd_10_11:2;
1381 unsigned long mmiol_cfg : 1; /* RW */ 1708 unsigned long mmiol_cfg:1; /* RW */
1382 unsigned long rsvd_13_63: 51; /* */ 1709 unsigned long rsvd_13_63:51;
1383 } s1; 1710 } s1;
1384 struct uv2h_rh_gam_config_mmr_s { 1711 struct uv2h_rh_gam_config_mmr_s {
1385 unsigned long m_skt : 6; /* RW */ 1712 unsigned long m_skt:6; /* RW */
1386 unsigned long n_skt : 4; /* RW */ 1713 unsigned long n_skt:4; /* RW */
1387 unsigned long rsvd_10_63: 54; /* */ 1714 unsigned long rsvd_10_63:54;
1388 } s2; 1715 } s2;
1389}; 1716};
1390 1717
1391/* ========================================================================= */ 1718/* ========================================================================= */
1392/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 1719/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
1393/* ========================================================================= */ 1720/* ========================================================================= */
1394#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 1721#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
1395 1722
1396#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1723#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1397#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1724#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1398 1725
1399#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1726#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1400#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1727#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
1401#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 1728#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1402#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 1729#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1403#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1730#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1404#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1731#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
1405#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1732#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1406#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1733#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1407 1734
1408#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 1735#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
1409#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 1736#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
1410#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 1737#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1411#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 1738#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
1412#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1739#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
1413#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1740#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1414 1741
1415union uvh_rh_gam_gru_overlay_config_mmr_u { 1742union uvh_rh_gam_gru_overlay_config_mmr_u {
1416 unsigned long v; 1743 unsigned long v;
1417 struct uvh_rh_gam_gru_overlay_config_mmr_s { 1744 struct uvh_rh_gam_gru_overlay_config_mmr_s {
1418 unsigned long rsvd_0_27: 28; /* */ 1745 unsigned long rsvd_0_27:28;
1419 unsigned long base : 18; /* RW */ 1746 unsigned long base:18; /* RW */
1420 unsigned long rsvd_46_62 : 17; 1747 unsigned long rsvd_46_62:17;
1421 unsigned long enable : 1; /* RW */ 1748 unsigned long enable:1; /* RW */
1422 } s; 1749 } s;
1423 struct uv1h_rh_gam_gru_overlay_config_mmr_s { 1750 struct uv1h_rh_gam_gru_overlay_config_mmr_s {
1424 unsigned long rsvd_0_27: 28; /* */ 1751 unsigned long rsvd_0_27:28;
1425 unsigned long base : 18; /* RW */ 1752 unsigned long base:18; /* RW */
1426 unsigned long rsvd_46_47: 2; /* */ 1753 unsigned long rsvd_46_47:2;
1427 unsigned long gr4 : 1; /* RW */ 1754 unsigned long gr4:1; /* RW */
1428 unsigned long rsvd_49_51: 3; /* */ 1755 unsigned long rsvd_49_51:3;
1429 unsigned long n_gru : 4; /* RW */ 1756 unsigned long n_gru:4; /* RW */
1430 unsigned long rsvd_56_62: 7; /* */ 1757 unsigned long rsvd_56_62:7;
1431 unsigned long enable : 1; /* RW */ 1758 unsigned long enable:1; /* RW */
1432 } s1; 1759 } s1;
1433 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 1760 struct uv2h_rh_gam_gru_overlay_config_mmr_s {
1434 unsigned long rsvd_0_27: 28; /* */ 1761 unsigned long rsvd_0_27:28;
1435 unsigned long base : 18; /* RW */ 1762 unsigned long base:18; /* RW */
1436 unsigned long rsvd_46_51: 6; /* */ 1763 unsigned long rsvd_46_51:6;
1437 unsigned long n_gru : 4; /* RW */ 1764 unsigned long n_gru:4; /* RW */
1438 unsigned long rsvd_56_62: 7; /* */ 1765 unsigned long rsvd_56_62:7;
1439 unsigned long enable : 1; /* RW */ 1766 unsigned long enable:1; /* RW */
1440 } s2; 1767 } s2;
1441}; 1768};
1442 1769
1443/* ========================================================================= */ 1770/* ========================================================================= */
1444/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 1771/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1445/* ========================================================================= */ 1772/* ========================================================================= */
1446#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 1773#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1447 1774
1448#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 1775#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1449#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 1776#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1450#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1777#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1451#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1452#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1453#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1454#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1778#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1779#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1780#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1781#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1455#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1782#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1456 1783
1457#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 1784#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
1458#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 1785#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1459#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 1786#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1460#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1461#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1462#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1463#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1787#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1788#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
1789#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1790#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1464#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1791#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1465 1792
1466union uvh_rh_gam_mmioh_overlay_config_mmr_u { 1793union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1467 unsigned long v; 1794 unsigned long v;
1468 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 1795 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
1469 unsigned long rsvd_0_29: 30; /* */ 1796 unsigned long rsvd_0_29:30;
1470 unsigned long base : 16; /* RW */ 1797 unsigned long base:16; /* RW */
1471 unsigned long m_io : 6; /* RW */ 1798 unsigned long m_io:6; /* RW */
1472 unsigned long n_io : 4; /* RW */ 1799 unsigned long n_io:4; /* RW */
1473 unsigned long rsvd_56_62: 7; /* */ 1800 unsigned long rsvd_56_62:7;
1474 unsigned long enable : 1; /* RW */ 1801 unsigned long enable:1; /* RW */
1475 } s1; 1802 } s1;
1476 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 1803 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
1477 unsigned long rsvd_0_26: 27; /* */ 1804 unsigned long rsvd_0_26:27;
1478 unsigned long base : 19; /* RW */ 1805 unsigned long base:19; /* RW */
1479 unsigned long m_io : 6; /* RW */ 1806 unsigned long m_io:6; /* RW */
1480 unsigned long n_io : 4; /* RW */ 1807 unsigned long n_io:4; /* RW */
1481 unsigned long rsvd_56_62: 7; /* */ 1808 unsigned long rsvd_56_62:7;
1482 unsigned long enable : 1; /* RW */ 1809 unsigned long enable:1; /* RW */
1483 } s2; 1810 } s2;
1484}; 1811};
1485 1812
1486/* ========================================================================= */ 1813/* ========================================================================= */
1487/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 1814/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
1488/* ========================================================================= */ 1815/* ========================================================================= */
1489#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 1816#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
1490 1817
1491#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1818#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1492#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1819#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1493 1820
1494#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1821#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1495#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1496#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 1822#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
1823#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1824#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1497#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 1825#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
1498#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1826#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1499#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1500 1827
1501#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 1828#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
1502#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 1829#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1503#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 1830#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
1504#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 1831#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1505 1832
1506union uvh_rh_gam_mmr_overlay_config_mmr_u { 1833union uvh_rh_gam_mmr_overlay_config_mmr_u {
1507 unsigned long v; 1834 unsigned long v;
1508 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 1835 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
1509 unsigned long rsvd_0_25: 26; /* */ 1836 unsigned long rsvd_0_25:26;
1510 unsigned long base : 20; /* RW */ 1837 unsigned long base:20; /* RW */
1511 unsigned long rsvd_46_62 : 17; 1838 unsigned long rsvd_46_62:17;
1512 unsigned long enable : 1; /* RW */ 1839 unsigned long enable:1; /* RW */
1513 } s; 1840 } s;
1514 struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 1841 struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
1515 unsigned long rsvd_0_25: 26; /* */ 1842 unsigned long rsvd_0_25:26;
1516 unsigned long base : 20; /* RW */ 1843 unsigned long base:20; /* RW */
1517 unsigned long dual_hub : 1; /* RW */ 1844 unsigned long dual_hub:1; /* RW */
1518 unsigned long rsvd_47_62: 16; /* */ 1845 unsigned long rsvd_47_62:16;
1519 unsigned long enable : 1; /* RW */ 1846 unsigned long enable:1; /* RW */
1520 } s1; 1847 } s1;
1521 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 1848 struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
1522 unsigned long rsvd_0_25: 26; /* */ 1849 unsigned long rsvd_0_25:26;
1523 unsigned long base : 20; /* RW */ 1850 unsigned long base:20; /* RW */
1524 unsigned long rsvd_46_62: 17; /* */ 1851 unsigned long rsvd_46_62:17;
1525 unsigned long enable : 1; /* RW */ 1852 unsigned long enable:1; /* RW */
1526 } s2; 1853 } s2;
1527}; 1854};
1528 1855
1529/* ========================================================================= */ 1856/* ========================================================================= */
1530/* UVH_RTC */ 1857/* UVH_RTC */
1531/* ========================================================================= */ 1858/* ========================================================================= */
1532#define UVH_RTC 0x340000UL 1859#define UVH_RTC 0x340000UL
1533 1860
1534#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 1861#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
1535#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 1862#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
1536 1863
1537union uvh_rtc_u { 1864union uvh_rtc_u {
1538 unsigned long v; 1865 unsigned long v;
1539 struct uvh_rtc_s { 1866 struct uvh_rtc_s {
1540 unsigned long real_time_clock : 56; /* RW */ 1867 unsigned long real_time_clock:56; /* RW */
1541 unsigned long rsvd_56_63 : 8; /* */ 1868 unsigned long rsvd_56_63:8;
1542 } s; 1869 } s;
1543}; 1870};
1544 1871
1545/* ========================================================================= */ 1872/* ========================================================================= */
1546/* UVH_RTC1_INT_CONFIG */ 1873/* UVH_RTC1_INT_CONFIG */
1547/* ========================================================================= */ 1874/* ========================================================================= */
1548#define UVH_RTC1_INT_CONFIG 0x615c0UL 1875#define UVH_RTC1_INT_CONFIG 0x615c0UL
1549 1876
1550#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 1877#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1551#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1878#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1552#define UVH_RTC1_INT_CONFIG_DM_SHFT 8 1879#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1553#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 1880#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1554#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 1881#define UVH_RTC1_INT_CONFIG_P_SHFT 13
1555#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1882#define UVH_RTC1_INT_CONFIG_T_SHFT 15
1556#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 1883#define UVH_RTC1_INT_CONFIG_M_SHFT 16
1557#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 1884#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1558#define UVH_RTC1_INT_CONFIG_P_SHFT 13 1885#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1559#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 1886#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1560#define UVH_RTC1_INT_CONFIG_T_SHFT 15 1887#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1561#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 1888#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1562#define UVH_RTC1_INT_CONFIG_M_SHFT 16 1889#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1563#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 1890#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1564#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 1891#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1565#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1892#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1566 1893
1567union uvh_rtc1_int_config_u { 1894union uvh_rtc1_int_config_u {
1568 unsigned long v; 1895 unsigned long v;
1569 struct uvh_rtc1_int_config_s { 1896 struct uvh_rtc1_int_config_s {
1570 unsigned long vector_ : 8; /* RW */ 1897 unsigned long vector_:8; /* RW */
1571 unsigned long dm : 3; /* RW */ 1898 unsigned long dm:3; /* RW */
1572 unsigned long destmode : 1; /* RW */ 1899 unsigned long destmode:1; /* RW */
1573 unsigned long status : 1; /* RO */ 1900 unsigned long status:1; /* RO */
1574 unsigned long p : 1; /* RO */ 1901 unsigned long p:1; /* RO */
1575 unsigned long rsvd_14 : 1; /* */ 1902 unsigned long rsvd_14:1;
1576 unsigned long t : 1; /* RO */ 1903 unsigned long t:1; /* RO */
1577 unsigned long m : 1; /* RW */ 1904 unsigned long m:1; /* RW */
1578 unsigned long rsvd_17_31: 15; /* */ 1905 unsigned long rsvd_17_31:15;
1579 unsigned long apic_id : 32; /* RW */ 1906 unsigned long apic_id:32; /* RW */
1580 } s; 1907 } s;
1581}; 1908};
1582 1909
1583/* ========================================================================= */ 1910/* ========================================================================= */
1584/* UVH_SCRATCH5 */ 1911/* UVH_SCRATCH5 */
1585/* ========================================================================= */ 1912/* ========================================================================= */
1586#define UVH_SCRATCH5 0x2d0200UL 1913#define UVH_SCRATCH5 0x2d0200UL
1587#define UVH_SCRATCH5_32 0x778 1914#define UVH_SCRATCH5_32 0x778
1588 1915
1589#define UVH_SCRATCH5_SCRATCH5_SHFT 0 1916#define UVH_SCRATCH5_SCRATCH5_SHFT 0
1590#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 1917#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
1591 1918
1592union uvh_scratch5_u { 1919union uvh_scratch5_u {
1593 unsigned long v; 1920 unsigned long v;
1594 struct uvh_scratch5_s { 1921 struct uvh_scratch5_s {
1595 unsigned long scratch5 : 64; /* RW, W1CS */ 1922 unsigned long scratch5:64; /* RW, W1CS */
1596 } s; 1923 } s;
1597}; 1924};
1598 1925
1599/* ========================================================================= */ 1926/* ========================================================================= */
1600/* UV2H_EVENT_OCCURRED2 */ 1927/* UV2H_EVENT_OCCURRED2 */
1601/* ========================================================================= */ 1928/* ========================================================================= */
1602#define UV2H_EVENT_OCCURRED2 0x70100UL 1929#define UV2H_EVENT_OCCURRED2 0x70100UL
1603#define UV2H_EVENT_OCCURRED2_32 0xb68 1930#define UV2H_EVENT_OCCURRED2_32 0xb68
1604 1931
1605#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 1932#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1606#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 1933#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
1607#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 1934#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
1608#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 1935#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
1609#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 1936#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
1610#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 1937#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
1611#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 1938#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
1612#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 1939#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
1613#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 1940#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
1614#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 1941#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
1615#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 1942#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
1616#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 1943#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
1617#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 1944#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
1618#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 1945#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
1619#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 1946#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
1620#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 1947#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
1621#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 1948#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
1622#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 1949#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
1623#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 1950#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
1624#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 1951#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
1625#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 1952#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
1626#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 1953#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
1627#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 1954#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
1628#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 1955#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
1629#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 1956#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
1630#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 1957#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
1631#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 1958#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
1632#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 1959#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
1633#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 1960#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
1634#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 1961#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
1635#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 1962#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
1636#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 1963#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
1637#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 1964#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1638#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 1965#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1639#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 1966#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1640#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 1967#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1641#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 1968#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1642#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 1969#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1643#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 1970#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1644#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 1971#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1645#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 1972#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1646#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 1973#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1647#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 1974#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1648#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 1975#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1649#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 1976#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1650#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 1977#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1651#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 1978#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1652#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 1979#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1653#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 1980#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1654#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 1981#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1655#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 1982#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1656#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 1983#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1657#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 1984#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1658#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 1985#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1659#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 1986#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1660#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 1987#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1661#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 1988#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1662#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 1989#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1663#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 1990#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1664#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 1991#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1665#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 1992#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1666#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 1993#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1667#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 1994#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1668#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 1995#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1669 1996
1670union uv2h_event_occurred2_u { 1997union uv2h_event_occurred2_u {
1671 unsigned long v; 1998 unsigned long v;
1672 struct uv2h_event_occurred2_s { 1999 struct uv2h_event_occurred2_s {
1673 unsigned long rtc_0 : 1; /* RW */ 2000 unsigned long rtc_0:1; /* RW */
1674 unsigned long rtc_1 : 1; /* RW */ 2001 unsigned long rtc_1:1; /* RW */
1675 unsigned long rtc_2 : 1; /* RW */ 2002 unsigned long rtc_2:1; /* RW */
1676 unsigned long rtc_3 : 1; /* RW */ 2003 unsigned long rtc_3:1; /* RW */
1677 unsigned long rtc_4 : 1; /* RW */ 2004 unsigned long rtc_4:1; /* RW */
1678 unsigned long rtc_5 : 1; /* RW */ 2005 unsigned long rtc_5:1; /* RW */
1679 unsigned long rtc_6 : 1; /* RW */ 2006 unsigned long rtc_6:1; /* RW */
1680 unsigned long rtc_7 : 1; /* RW */ 2007 unsigned long rtc_7:1; /* RW */
1681 unsigned long rtc_8 : 1; /* RW */ 2008 unsigned long rtc_8:1; /* RW */
1682 unsigned long rtc_9 : 1; /* RW */ 2009 unsigned long rtc_9:1; /* RW */
1683 unsigned long rtc_10 : 1; /* RW */ 2010 unsigned long rtc_10:1; /* RW */
1684 unsigned long rtc_11 : 1; /* RW */ 2011 unsigned long rtc_11:1; /* RW */
1685 unsigned long rtc_12 : 1; /* RW */ 2012 unsigned long rtc_12:1; /* RW */
1686 unsigned long rtc_13 : 1; /* RW */ 2013 unsigned long rtc_13:1; /* RW */
1687 unsigned long rtc_14 : 1; /* RW */ 2014 unsigned long rtc_14:1; /* RW */
1688 unsigned long rtc_15 : 1; /* RW */ 2015 unsigned long rtc_15:1; /* RW */
1689 unsigned long rtc_16 : 1; /* RW */ 2016 unsigned long rtc_16:1; /* RW */
1690 unsigned long rtc_17 : 1; /* RW */ 2017 unsigned long rtc_17:1; /* RW */
1691 unsigned long rtc_18 : 1; /* RW */ 2018 unsigned long rtc_18:1; /* RW */
1692 unsigned long rtc_19 : 1; /* RW */ 2019 unsigned long rtc_19:1; /* RW */
1693 unsigned long rtc_20 : 1; /* RW */ 2020 unsigned long rtc_20:1; /* RW */
1694 unsigned long rtc_21 : 1; /* RW */ 2021 unsigned long rtc_21:1; /* RW */
1695 unsigned long rtc_22 : 1; /* RW */ 2022 unsigned long rtc_22:1; /* RW */
1696 unsigned long rtc_23 : 1; /* RW */ 2023 unsigned long rtc_23:1; /* RW */
1697 unsigned long rtc_24 : 1; /* RW */ 2024 unsigned long rtc_24:1; /* RW */
1698 unsigned long rtc_25 : 1; /* RW */ 2025 unsigned long rtc_25:1; /* RW */
1699 unsigned long rtc_26 : 1; /* RW */ 2026 unsigned long rtc_26:1; /* RW */
1700 unsigned long rtc_27 : 1; /* RW */ 2027 unsigned long rtc_27:1; /* RW */
1701 unsigned long rtc_28 : 1; /* RW */ 2028 unsigned long rtc_28:1; /* RW */
1702 unsigned long rtc_29 : 1; /* RW */ 2029 unsigned long rtc_29:1; /* RW */
1703 unsigned long rtc_30 : 1; /* RW */ 2030 unsigned long rtc_30:1; /* RW */
1704 unsigned long rtc_31 : 1; /* RW */ 2031 unsigned long rtc_31:1; /* RW */
1705 unsigned long rsvd_32_63: 32; /* */ 2032 unsigned long rsvd_32_63:32;
1706 } s1; 2033 } s1;
1707}; 2034};
1708 2035
1709/* ========================================================================= */ 2036/* ========================================================================= */
1710/* UV2H_EVENT_OCCURRED2_ALIAS */ 2037/* UV2H_EVENT_OCCURRED2_ALIAS */
1711/* ========================================================================= */ 2038/* ========================================================================= */
1712#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL 2039#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
1713#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 2040#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
1714 2041
1715/* ========================================================================= */ 2042/* ========================================================================= */
1716/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */ 2043/* UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 */
1717/* ========================================================================= */ 2044/* ========================================================================= */
1718#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 2045#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
1719#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 2046#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
1720 2047
1721#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2048#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
1722#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2049#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
1723 2050
1724union uv2h_lb_bau_sb_activation_status_2_u { 2051union uv2h_lb_bau_sb_activation_status_2_u {
1725 unsigned long v; 2052 unsigned long v;
1726 struct uv2h_lb_bau_sb_activation_status_2_s { 2053 struct uv2h_lb_bau_sb_activation_status_2_s {
1727 unsigned long aux_error : 64; /* RW */ 2054 unsigned long aux_error:64; /* RW */
1728 } s1; 2055 } s1;
1729}; 2056};
1730 2057
1731/* ========================================================================= */ 2058/* ========================================================================= */
1732/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 2059/* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */
1733/* ========================================================================= */ 2060/* ========================================================================= */
1734#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 2061#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
1735#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 2062#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
1736 2063
1737#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 2064#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
1738#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 2065#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
1739 2066
1740union uv1h_lb_target_physical_apic_id_mask_u { 2067union uv1h_lb_target_physical_apic_id_mask_u {
1741 unsigned long v; 2068 unsigned long v;
1742 struct uv1h_lb_target_physical_apic_id_mask_s { 2069 struct uv1h_lb_target_physical_apic_id_mask_s {
1743 unsigned long bit_enables : 32; /* RW */ 2070 unsigned long bit_enables:32; /* RW */
1744 unsigned long rsvd_32_63 : 32; /* */ 2071 unsigned long rsvd_32_63:32;
1745 } s1; 2072 } s1;
1746}; 2073};
1747 2074
1748 2075
1749#endif /* __ASM_UV_MMRS_X86_H__ */ 2076#endif /* _ASM_X86_UV_UV_MMRS_H */
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 646b4c1ca695..815285bcaceb 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -11,10 +11,9 @@ struct vsyscall_gtod_data {
11 time_t wall_time_sec; 11 time_t wall_time_sec;
12 u32 wall_time_nsec; 12 u32 wall_time_nsec;
13 13
14 int sysctl_enabled;
15 struct timezone sys_tz; 14 struct timezone sys_tz;
16 struct { /* extract of a clocksource struct */ 15 struct { /* extract of a clocksource struct */
17 cycle_t (*vread)(void); 16 int vclock_mode;
18 cycle_t cycle_last; 17 cycle_t cycle_last;
19 cycle_t mask; 18 cycle_t mask;
20 u32 mult; 19 u32 mult;
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 84471b810460..2caf290e9895 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -132,6 +132,8 @@ enum vmcs_field {
132 GUEST_IA32_PAT_HIGH = 0x00002805, 132 GUEST_IA32_PAT_HIGH = 0x00002805,
133 GUEST_IA32_EFER = 0x00002806, 133 GUEST_IA32_EFER = 0x00002806,
134 GUEST_IA32_EFER_HIGH = 0x00002807, 134 GUEST_IA32_EFER_HIGH = 0x00002807,
135 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
136 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
135 GUEST_PDPTR0 = 0x0000280a, 137 GUEST_PDPTR0 = 0x0000280a,
136 GUEST_PDPTR0_HIGH = 0x0000280b, 138 GUEST_PDPTR0_HIGH = 0x0000280b,
137 GUEST_PDPTR1 = 0x0000280c, 139 GUEST_PDPTR1 = 0x0000280c,
@@ -144,6 +146,8 @@ enum vmcs_field {
144 HOST_IA32_PAT_HIGH = 0x00002c01, 146 HOST_IA32_PAT_HIGH = 0x00002c01,
145 HOST_IA32_EFER = 0x00002c02, 147 HOST_IA32_EFER = 0x00002c02,
146 HOST_IA32_EFER_HIGH = 0x00002c03, 148 HOST_IA32_EFER_HIGH = 0x00002c03,
149 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
150 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
147 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 151 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
148 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 152 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
149 EXCEPTION_BITMAP = 0x00004004, 153 EXCEPTION_BITMAP = 0x00004004,
@@ -426,4 +430,43 @@ struct vmx_msr_entry {
426 u64 value; 430 u64 value;
427} __aligned(16); 431} __aligned(16);
428 432
433/*
434 * Exit Qualifications for entry failure during or after loading guest state
435 */
436#define ENTRY_FAIL_DEFAULT 0
437#define ENTRY_FAIL_PDPTE 2
438#define ENTRY_FAIL_NMI 3
439#define ENTRY_FAIL_VMCS_LINK_PTR 4
440
441/*
442 * VM-instruction error numbers
443 */
444enum vm_instruction_error_number {
445 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
446 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
447 VMXERR_VMCLEAR_VMXON_POINTER = 3,
448 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
449 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
450 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
451 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
452 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
453 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
454 VMXERR_VMPTRLD_VMXON_POINTER = 10,
455 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
456 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
457 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
458 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
459 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
460 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
461 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
462 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
463 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
464 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
465 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
466 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
467 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
468 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
469 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
470};
471
429#endif 472#endif
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index d55597351f6a..eaea1d31f753 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -16,10 +16,6 @@ enum vsyscall_num {
16#ifdef __KERNEL__ 16#ifdef __KERNEL__
17#include <linux/seqlock.h> 17#include <linux/seqlock.h>
18 18
19/* Definitions for CONFIG_GENERIC_TIME definitions */
20#define __vsyscall_fn \
21 __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
22
23#define VGETCPU_RDTSCP 1 19#define VGETCPU_RDTSCP 1
24#define VGETCPU_LSL 2 20#define VGETCPU_LSL 2
25 21
@@ -31,6 +27,12 @@ extern struct timezone sys_tz;
31 27
32extern void map_vsyscall(void); 28extern void map_vsyscall(void);
33 29
30/*
31 * Called on instruction fetch fault in vsyscall page.
32 * Returns true if handled.
33 */
34extern bool emulate_vsyscall(struct pt_regs *regs, unsigned long address);
35
34#endif /* __KERNEL__ */ 36#endif /* __KERNEL__ */
35 37
36#endif /* _ASM_X86_VSYSCALL_H */ 38#endif /* _ASM_X86_VSYSCALL_H */
diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h
index 341b3559452b..de656ac2af41 100644
--- a/arch/x86/include/asm/vvar.h
+++ b/arch/x86/include/asm/vvar.h
@@ -10,15 +10,14 @@
10 * In normal kernel code, they are used like any other variable. 10 * In normal kernel code, they are used like any other variable.
11 * In user code, they are accessed through the VVAR macro. 11 * In user code, they are accessed through the VVAR macro.
12 * 12 *
13 * Each of these variables lives in the vsyscall page, and each 13 * These variables live in a page of kernel data that has an extra RO
14 * one needs a unique offset within the little piece of the page 14 * mapping for userspace. Each variable needs a unique offset within
15 * reserved for vvars. Specify that offset in DECLARE_VVAR. 15 * that page; specify that offset with the DECLARE_VVAR macro. (If
16 * (There are 896 bytes available. If you mess up, the linker will 16 * you mess up, the linker will catch it.)
17 * catch it.)
18 */ 17 */
19 18
20/* Offset of vars within vsyscall page */ 19/* Base address of vvars. This is not ABI. */
21#define VSYSCALL_VARS_OFFSET (3072 + 128) 20#define VVAR_ADDRESS (-10*1024*1024 - 4096)
22 21
23#if defined(__VVAR_KERNEL_LDS) 22#if defined(__VVAR_KERNEL_LDS)
24 23
@@ -26,17 +25,17 @@
26 * right place. 25 * right place.
27 */ 26 */
28#define DECLARE_VVAR(offset, type, name) \ 27#define DECLARE_VVAR(offset, type, name) \
29 EMIT_VVAR(name, VSYSCALL_VARS_OFFSET + offset) 28 EMIT_VVAR(name, offset)
30 29
31#else 30#else
32 31
33#define DECLARE_VVAR(offset, type, name) \ 32#define DECLARE_VVAR(offset, type, name) \
34 static type const * const vvaraddr_ ## name = \ 33 static type const * const vvaraddr_ ## name = \
35 (void *)(VSYSCALL_START + VSYSCALL_VARS_OFFSET + (offset)); 34 (void *)(VVAR_ADDRESS + (offset));
36 35
37#define DEFINE_VVAR(type, name) \ 36#define DEFINE_VVAR(type, name) \
38 type __vvar_ ## name \ 37 type name \
39 __attribute__((section(".vsyscall_var_" #name), aligned(16))) 38 __attribute__((section(".vvar_" #name), aligned(16)))
40 39
41#define VVAR(name) (*vvaraddr_ ## name) 40#define VVAR(name) (*vvaraddr_ ## name)
42 41
@@ -45,8 +44,7 @@
45/* DECLARE_VVAR(offset, type, name) */ 44/* DECLARE_VVAR(offset, type, name) */
46 45
47DECLARE_VVAR(0, volatile unsigned long, jiffies) 46DECLARE_VVAR(0, volatile unsigned long, jiffies)
48DECLARE_VVAR(8, int, vgetcpu_mode) 47DECLARE_VVAR(16, int, vgetcpu_mode)
49DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data) 48DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data)
50 49
51#undef DECLARE_VVAR 50#undef DECLARE_VVAR
52#undef VSYSCALL_VARS_OFFSET
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index d240ea950519..417777de5a40 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -39,6 +39,8 @@
39#include <linux/string.h> 39#include <linux/string.h>
40#include <linux/types.h> 40#include <linux/types.h>
41 41
42#include <trace/events/xen.h>
43
42#include <asm/page.h> 44#include <asm/page.h>
43#include <asm/pgtable.h> 45#include <asm/pgtable.h>
44 46
@@ -459,6 +461,8 @@ MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
459{ 461{
460 mcl->op = __HYPERVISOR_fpu_taskswitch; 462 mcl->op = __HYPERVISOR_fpu_taskswitch;
461 mcl->args[0] = set; 463 mcl->args[0] = set;
464
465 trace_xen_mc_entry(mcl, 1);
462} 466}
463 467
464static inline void 468static inline void
@@ -475,6 +479,8 @@ MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
475 mcl->args[2] = new_val.pte >> 32; 479 mcl->args[2] = new_val.pte >> 32;
476 mcl->args[3] = flags; 480 mcl->args[3] = flags;
477 } 481 }
482
483 trace_xen_mc_entry(mcl, sizeof(new_val) == sizeof(long) ? 3 : 4);
478} 484}
479 485
480static inline void 486static inline void
@@ -485,6 +491,8 @@ MULTI_grant_table_op(struct multicall_entry *mcl, unsigned int cmd,
485 mcl->args[0] = cmd; 491 mcl->args[0] = cmd;
486 mcl->args[1] = (unsigned long)uop; 492 mcl->args[1] = (unsigned long)uop;
487 mcl->args[2] = count; 493 mcl->args[2] = count;
494
495 trace_xen_mc_entry(mcl, 3);
488} 496}
489 497
490static inline void 498static inline void
@@ -504,6 +512,8 @@ MULTI_update_va_mapping_otherdomain(struct multicall_entry *mcl, unsigned long v
504 mcl->args[3] = flags; 512 mcl->args[3] = flags;
505 mcl->args[4] = domid; 513 mcl->args[4] = domid;
506 } 514 }
515
516 trace_xen_mc_entry(mcl, sizeof(new_val) == sizeof(long) ? 4 : 5);
507} 517}
508 518
509static inline void 519static inline void
@@ -520,6 +530,8 @@ MULTI_update_descriptor(struct multicall_entry *mcl, u64 maddr,
520 mcl->args[2] = desc.a; 530 mcl->args[2] = desc.a;
521 mcl->args[3] = desc.b; 531 mcl->args[3] = desc.b;
522 } 532 }
533
534 trace_xen_mc_entry(mcl, sizeof(maddr) == sizeof(long) ? 2 : 4);
523} 535}
524 536
525static inline void 537static inline void
@@ -528,6 +540,8 @@ MULTI_memory_op(struct multicall_entry *mcl, unsigned int cmd, void *arg)
528 mcl->op = __HYPERVISOR_memory_op; 540 mcl->op = __HYPERVISOR_memory_op;
529 mcl->args[0] = cmd; 541 mcl->args[0] = cmd;
530 mcl->args[1] = (unsigned long)arg; 542 mcl->args[1] = (unsigned long)arg;
543
544 trace_xen_mc_entry(mcl, 2);
531} 545}
532 546
533static inline void 547static inline void
@@ -539,6 +553,8 @@ MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
539 mcl->args[1] = count; 553 mcl->args[1] = count;
540 mcl->args[2] = (unsigned long)success_count; 554 mcl->args[2] = (unsigned long)success_count;
541 mcl->args[3] = domid; 555 mcl->args[3] = domid;
556
557 trace_xen_mc_entry(mcl, 4);
542} 558}
543 559
544static inline void 560static inline void
@@ -550,6 +566,8 @@ MULTI_mmuext_op(struct multicall_entry *mcl, struct mmuext_op *op, int count,
550 mcl->args[1] = count; 566 mcl->args[1] = count;
551 mcl->args[2] = (unsigned long)success_count; 567 mcl->args[2] = (unsigned long)success_count;
552 mcl->args[3] = domid; 568 mcl->args[3] = domid;
569
570 trace_xen_mc_entry(mcl, 4);
553} 571}
554 572
555static inline void 573static inline void
@@ -558,6 +576,8 @@ MULTI_set_gdt(struct multicall_entry *mcl, unsigned long *frames, int entries)
558 mcl->op = __HYPERVISOR_set_gdt; 576 mcl->op = __HYPERVISOR_set_gdt;
559 mcl->args[0] = (unsigned long)frames; 577 mcl->args[0] = (unsigned long)frames;
560 mcl->args[1] = entries; 578 mcl->args[1] = entries;
579
580 trace_xen_mc_entry(mcl, 2);
561} 581}
562 582
563static inline void 583static inline void
@@ -567,6 +587,8 @@ MULTI_stack_switch(struct multicall_entry *mcl,
567 mcl->op = __HYPERVISOR_stack_switch; 587 mcl->op = __HYPERVISOR_stack_switch;
568 mcl->args[0] = ss; 588 mcl->args[0] = ss;
569 mcl->args[1] = esp; 589 mcl->args[1] = esp;
590
591 trace_xen_mc_entry(mcl, 2);
570} 592}
571 593
572#endif /* _ASM_X86_XEN_HYPERCALL_H */ 594#endif /* _ASM_X86_XEN_HYPERCALL_H */
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 64a619d47d34..c34f96c2f7a0 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -12,6 +12,7 @@
12#include <asm/pgtable.h> 12#include <asm/pgtable.h>
13 13
14#include <xen/interface/xen.h> 14#include <xen/interface/xen.h>
15#include <xen/grant_table.h>
15#include <xen/features.h> 16#include <xen/features.h>
16 17
17/* Xen machine address */ 18/* Xen machine address */
@@ -39,7 +40,7 @@ typedef struct xpaddr {
39 ((unsigned long)((u64)CONFIG_XEN_MAX_DOMAIN_MEMORY * 1024 * 1024 * 1024 / PAGE_SIZE)) 40 ((unsigned long)((u64)CONFIG_XEN_MAX_DOMAIN_MEMORY * 1024 * 1024 * 1024 / PAGE_SIZE))
40 41
41extern unsigned long *machine_to_phys_mapping; 42extern unsigned long *machine_to_phys_mapping;
42extern unsigned int machine_to_phys_order; 43extern unsigned long machine_to_phys_nr;
43 44
44extern unsigned long get_phys_to_machine(unsigned long pfn); 45extern unsigned long get_phys_to_machine(unsigned long pfn);
45extern bool set_phys_to_machine(unsigned long pfn, unsigned long mfn); 46extern bool set_phys_to_machine(unsigned long pfn, unsigned long mfn);
@@ -48,14 +49,11 @@ extern unsigned long set_phys_range_identity(unsigned long pfn_s,
48 unsigned long pfn_e); 49 unsigned long pfn_e);
49 50
50extern int m2p_add_override(unsigned long mfn, struct page *page, 51extern int m2p_add_override(unsigned long mfn, struct page *page,
51 bool clear_pte); 52 struct gnttab_map_grant_ref *kmap_op);
52extern int m2p_remove_override(struct page *page, bool clear_pte); 53extern int m2p_remove_override(struct page *page, bool clear_pte);
53extern struct page *m2p_find_override(unsigned long mfn); 54extern struct page *m2p_find_override(unsigned long mfn);
54extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn); 55extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn);
55 56
56#ifdef CONFIG_XEN_DEBUG_FS
57extern int p2m_dump_show(struct seq_file *m, void *v);
58#endif
59static inline unsigned long pfn_to_mfn(unsigned long pfn) 57static inline unsigned long pfn_to_mfn(unsigned long pfn)
60{ 58{
61 unsigned long mfn; 59 unsigned long mfn;
@@ -87,7 +85,7 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
87 if (xen_feature(XENFEAT_auto_translated_physmap)) 85 if (xen_feature(XENFEAT_auto_translated_physmap))
88 return mfn; 86 return mfn;
89 87
90 if (unlikely((mfn >> machine_to_phys_order) != 0)) { 88 if (unlikely(mfn >= machine_to_phys_nr)) {
91 pfn = ~0; 89 pfn = ~0;
92 goto try_override; 90 goto try_override;
93 } 91 }
diff --git a/arch/x86/include/asm/xen/pci.h b/arch/x86/include/asm/xen/pci.h
index 4fbda9a3f339..968d57dd54c9 100644
--- a/arch/x86/include/asm/xen/pci.h
+++ b/arch/x86/include/asm/xen/pci.h
@@ -14,13 +14,14 @@ static inline int pci_xen_hvm_init(void)
14} 14}
15#endif 15#endif
16#if defined(CONFIG_XEN_DOM0) 16#if defined(CONFIG_XEN_DOM0)
17void __init xen_setup_pirqs(void); 17int __init pci_xen_initial_domain(void);
18int xen_find_device_domain_owner(struct pci_dev *dev); 18int xen_find_device_domain_owner(struct pci_dev *dev);
19int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain); 19int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain);
20int xen_unregister_device_domain_owner(struct pci_dev *dev); 20int xen_unregister_device_domain_owner(struct pci_dev *dev);
21#else 21#else
22static inline void __init xen_setup_pirqs(void) 22static inline int __init pci_xen_initial_domain(void)
23{ 23{
24 return -1;
24} 25}
25static inline int xen_find_device_domain_owner(struct pci_dev *dev) 26static inline int xen_find_device_domain_owner(struct pci_dev *dev)
26{ 27{
diff --git a/arch/x86/include/asm/xen/trace_types.h b/arch/x86/include/asm/xen/trace_types.h
new file mode 100644
index 000000000000..21e1874c0a0b
--- /dev/null
+++ b/arch/x86/include/asm/xen/trace_types.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_XEN_TRACE_TYPES_H
2#define _ASM_XEN_TRACE_TYPES_H
3
4enum xen_mc_flush_reason {
5 XEN_MC_FL_NONE, /* explicit flush */
6 XEN_MC_FL_BATCH, /* out of hypercall space */
7 XEN_MC_FL_ARGS, /* out of argument space */
8 XEN_MC_FL_CALLBACK, /* out of callback space */
9};
10
11enum xen_mc_extend_args {
12 XEN_MC_XE_OK,
13 XEN_MC_XE_BAD_OP,
14 XEN_MC_XE_NO_SPACE
15};
16typedef void (*xen_mc_callback_fn_t)(void *);
17
18#endif /* _ASM_XEN_TRACE_TYPES_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 23:12:41 -0400