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-rw-r--r--arch/x86/include/asm/Kbuild3
-rw-r--r--arch/x86/include/asm/acenv.h4
-rw-r--r--arch/x86/include/asm/acpi.h5
-rw-r--r--arch/x86/include/asm/alternative.h14
-rw-r--r--arch/x86/include/asm/apic.h46
-rw-r--r--arch/x86/include/asm/crash.h9
-rw-r--r--arch/x86/include/asm/fpu-internal.h9
-rw-r--r--arch/x86/include/asm/hardirq.h3
-rw-r--r--arch/x86/include/asm/i8259.h5
-rw-r--r--arch/x86/include/asm/io_apic.h56
-rw-r--r--arch/x86/include/asm/kexec-bzimage64.h6
-rw-r--r--arch/x86/include/asm/kexec.h45
-rw-r--r--arch/x86/include/asm/mpspec.h15
-rw-r--r--arch/x86/include/asm/page.h1
-rw-r--r--arch/x86/include/asm/page_64.h2
-rw-r--r--arch/x86/include/asm/platform_sst_audio.h78
-rw-r--r--arch/x86/include/asm/processor.h4
-rw-r--r--arch/x86/include/asm/prom.h2
-rw-r--r--arch/x86/include/asm/scatterlist.h8
-rw-r--r--arch/x86/include/asm/smpboot_hooks.h10
-rw-r--r--arch/x86/include/asm/xsave.h223
-rw-r--r--arch/x86/include/uapi/asm/msr-index.h3
22 files changed, 388 insertions, 163 deletions
diff --git a/arch/x86/include/asm/Kbuild b/arch/x86/include/asm/Kbuild
index 3ca9762e1649..3bf000fab0ae 100644
--- a/arch/x86/include/asm/Kbuild
+++ b/arch/x86/include/asm/Kbuild
@@ -5,6 +5,7 @@ genhdr-y += unistd_64.h
5genhdr-y += unistd_x32.h 5genhdr-y += unistd_x32.h
6 6
7generic-y += clkdev.h 7generic-y += clkdev.h
8generic-y += early_ioremap.h
9generic-y += cputime.h 8generic-y += cputime.h
9generic-y += early_ioremap.h
10generic-y += mcs_spinlock.h 10generic-y += mcs_spinlock.h
11generic-y += scatterlist.h
diff --git a/arch/x86/include/asm/acenv.h b/arch/x86/include/asm/acenv.h
index 66873297e9f5..1b010a859b8b 100644
--- a/arch/x86/include/asm/acenv.h
+++ b/arch/x86/include/asm/acenv.h
@@ -18,8 +18,6 @@
18 18
19#define ACPI_FLUSH_CPU_CACHE() wbinvd() 19#define ACPI_FLUSH_CPU_CACHE() wbinvd()
20 20
21#ifdef CONFIG_ACPI
22
23int __acpi_acquire_global_lock(unsigned int *lock); 21int __acpi_acquire_global_lock(unsigned int *lock);
24int __acpi_release_global_lock(unsigned int *lock); 22int __acpi_release_global_lock(unsigned int *lock);
25 23
@@ -44,6 +42,4 @@ int __acpi_release_global_lock(unsigned int *lock);
44 : "=r"(n_hi), "=r"(n_lo) \ 42 : "=r"(n_hi), "=r"(n_lo) \
45 : "0"(n_hi), "1"(n_lo)) 43 : "0"(n_hi), "1"(n_lo))
46 44
47#endif
48
49#endif /* _ASM_X86_ACENV_H */ 45#endif /* _ASM_X86_ACENV_H */
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index e06225eda635..0ab4f9fd2687 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -121,6 +121,11 @@ static inline void arch_acpi_set_pdc_bits(u32 *buf)
121 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); 121 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
122} 122}
123 123
124static inline bool acpi_has_cpu_in_madt(void)
125{
126 return !!acpi_lapic;
127}
128
124#else /* !CONFIG_ACPI */ 129#else /* !CONFIG_ACPI */
125 130
126#define acpi_lapic 0 131#define acpi_lapic 0
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 0a3f9c9f98d5..473bdbee378a 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -161,6 +161,20 @@ static inline int alternatives_text_reserved(void *start, void *end)
161 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \ 161 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
162 : : "i" (0), ## input) 162 : : "i" (0), ## input)
163 163
164/*
165 * This is similar to alternative_input. But it has two features and
166 * respective instructions.
167 *
168 * If CPU has feature2, newinstr2 is used.
169 * Otherwise, if CPU has feature1, newinstr1 is used.
170 * Otherwise, oldinstr is used.
171 */
172#define alternative_input_2(oldinstr, newinstr1, feature1, newinstr2, \
173 feature2, input...) \
174 asm volatile(ALTERNATIVE_2(oldinstr, newinstr1, feature1, \
175 newinstr2, feature2) \
176 : : "i" (0), ## input)
177
164/* Like alternative_input, but with a single output argument */ 178/* Like alternative_input, but with a single output argument */
165#define alternative_io(oldinstr, newinstr, feature, output, input...) \ 179#define alternative_io(oldinstr, newinstr, feature, output, input...) \
166 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \ 180 asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 79752f2bdec5..465b309af254 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -85,14 +85,6 @@ static inline bool apic_from_smp_config(void)
85#include <asm/paravirt.h> 85#include <asm/paravirt.h>
86#endif 86#endif
87 87
88#ifdef CONFIG_X86_64
89extern int is_vsmp_box(void);
90#else
91static inline int is_vsmp_box(void)
92{
93 return 0;
94}
95#endif
96extern int setup_profiling_timer(unsigned int); 88extern int setup_profiling_timer(unsigned int);
97 89
98static inline void native_apic_mem_write(u32 reg, u32 v) 90static inline void native_apic_mem_write(u32 reg, u32 v)
@@ -300,7 +292,6 @@ struct apic {
300 292
301 int dest_logical; 293 int dest_logical;
302 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 294 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
303 unsigned long (*check_apicid_present)(int apicid);
304 295
305 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 296 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
306 const struct cpumask *mask); 297 const struct cpumask *mask);
@@ -309,21 +300,11 @@ struct apic {
309 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 300 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
310 301
311 void (*setup_apic_routing)(void); 302 void (*setup_apic_routing)(void);
312 int (*multi_timer_check)(int apic, int irq);
313 int (*cpu_present_to_apicid)(int mps_cpu); 303 int (*cpu_present_to_apicid)(int mps_cpu);
314 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 304 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
315 void (*setup_portio_remap)(void);
316 int (*check_phys_apicid_present)(int phys_apicid); 305 int (*check_phys_apicid_present)(int phys_apicid);
317 void (*enable_apic_mode)(void);
318 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 306 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
319 307
320 /*
321 * When one of the next two hooks returns 1 the apic
322 * is switched to this. Essentially they are additional
323 * probe functions:
324 */
325 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
326
327 unsigned int (*get_apic_id)(unsigned long x); 308 unsigned int (*get_apic_id)(unsigned long x);
328 unsigned long (*set_apic_id)(unsigned int id); 309 unsigned long (*set_apic_id)(unsigned int id);
329 unsigned long apic_id_mask; 310 unsigned long apic_id_mask;
@@ -343,11 +324,7 @@ struct apic {
343 /* wakeup_secondary_cpu */ 324 /* wakeup_secondary_cpu */
344 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 325 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
345 326
346 int trampoline_phys_low;
347 int trampoline_phys_high;
348
349 bool wait_for_init_deassert; 327 bool wait_for_init_deassert;
350 void (*smp_callin_clear_local_apic)(void);
351 void (*inquire_remote_apic)(int apicid); 328 void (*inquire_remote_apic)(int apicid);
352 329
353 /* apic ops */ 330 /* apic ops */
@@ -378,14 +355,6 @@ struct apic {
378 * won't be applied properly during early boot in this case. 355 * won't be applied properly during early boot in this case.
379 */ 356 */
380 int (*x86_32_early_logical_apicid)(int cpu); 357 int (*x86_32_early_logical_apicid)(int cpu);
381
382 /*
383 * Optional method called from setup_local_APIC() after logical
384 * apicid is guaranteed to be known to initialize apicid -> node
385 * mapping if NUMA initialization hasn't done so already. Don't
386 * add new users.
387 */
388 int (*x86_32_numa_cpu_node)(int cpu);
389#endif 358#endif
390}; 359};
391 360
@@ -496,14 +465,12 @@ static inline unsigned default_get_apic_id(unsigned long x)
496} 465}
497 466
498/* 467/*
499 * Warm reset vector default position: 468 * Warm reset vector position:
500 */ 469 */
501#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 470#define TRAMPOLINE_PHYS_LOW 0x467
502#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 471#define TRAMPOLINE_PHYS_HIGH 0x469
503 472
504#ifdef CONFIG_X86_64 473#ifdef CONFIG_X86_64
505extern int default_acpi_madt_oem_check(char *, char *);
506
507extern void apic_send_IPI_self(int vector); 474extern void apic_send_IPI_self(int vector);
508 475
509DECLARE_PER_CPU(int, x2apic_extra_bits); 476DECLARE_PER_CPU(int, x2apic_extra_bits);
@@ -552,6 +519,8 @@ static inline int default_apic_id_valid(int apicid)
552 return (apicid < 255); 519 return (apicid < 255);
553} 520}
554 521
522extern int default_acpi_madt_oem_check(char *, char *);
523
555extern void default_setup_apic_routing(void); 524extern void default_setup_apic_routing(void);
556 525
557extern struct apic apic_noop; 526extern struct apic apic_noop;
@@ -635,11 +604,6 @@ static inline unsigned long default_check_apicid_used(physid_mask_t *map, int ap
635 return physid_isset(apicid, *map); 604 return physid_isset(apicid, *map);
636} 605}
637 606
638static inline unsigned long default_check_apicid_present(int bit)
639{
640 return physid_isset(bit, phys_cpu_present_map);
641}
642
643static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 607static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
644{ 608{
645 *retmap = *phys_map; 609 *retmap = *phys_map;
diff --git a/arch/x86/include/asm/crash.h b/arch/x86/include/asm/crash.h
new file mode 100644
index 000000000000..f498411f2500
--- /dev/null
+++ b/arch/x86/include/asm/crash.h
@@ -0,0 +1,9 @@
1#ifndef _ASM_X86_CRASH_H
2#define _ASM_X86_CRASH_H
3
4int crash_load_segments(struct kimage *image);
5int crash_copy_backup_region(struct kimage *image);
6int crash_setup_memmap_entries(struct kimage *image,
7 struct boot_params *params);
8
9#endif /* _ASM_X86_CRASH_H */
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
index e3b85422cf12..412ececa00b9 100644
--- a/arch/x86/include/asm/fpu-internal.h
+++ b/arch/x86/include/asm/fpu-internal.h
@@ -508,9 +508,12 @@ static inline void user_fpu_begin(void)
508 508
509static inline void __save_fpu(struct task_struct *tsk) 509static inline void __save_fpu(struct task_struct *tsk)
510{ 510{
511 if (use_xsave()) 511 if (use_xsave()) {
512 xsave_state(&tsk->thread.fpu.state->xsave, -1); 512 if (unlikely(system_state == SYSTEM_BOOTING))
513 else 513 xsave_state_booting(&tsk->thread.fpu.state->xsave, -1);
514 else
515 xsave_state(&tsk->thread.fpu.state->xsave, -1);
516 } else
514 fpu_fxsave(&tsk->thread.fpu); 517 fpu_fxsave(&tsk->thread.fpu);
515} 518}
516 519
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 230853da4ec0..0f5fb6b6567e 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -40,9 +40,6 @@ typedef struct {
40 40
41DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); 41DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
42 42
43/* We can have at most NR_VECTORS irqs routed to a cpu at a time */
44#define MAX_HARDIRQS_PER_CPU NR_VECTORS
45
46#define __ARCH_IRQ_STAT 43#define __ARCH_IRQ_STAT
47 44
48#define inc_irq_stat(member) this_cpu_inc(irq_stat.member) 45#define inc_irq_stat(member) this_cpu_inc(irq_stat.member)
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
index a20365953bf8..ccffa53750a8 100644
--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -67,4 +67,9 @@ struct legacy_pic {
67extern struct legacy_pic *legacy_pic; 67extern struct legacy_pic *legacy_pic;
68extern struct legacy_pic null_legacy_pic; 68extern struct legacy_pic null_legacy_pic;
69 69
70static inline int nr_legacy_irqs(void)
71{
72 return legacy_pic->nr_legacy_irqs;
73}
74
70#endif /* _ASM_X86_I8259_H */ 75#endif /* _ASM_X86_I8259_H */
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 90f97b4b9347..0aeed5ca356e 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -98,6 +98,8 @@ struct IR_IO_APIC_route_entry {
98#define IOAPIC_AUTO -1 98#define IOAPIC_AUTO -1
99#define IOAPIC_EDGE 0 99#define IOAPIC_EDGE 0
100#define IOAPIC_LEVEL 1 100#define IOAPIC_LEVEL 1
101#define IOAPIC_MAP_ALLOC 0x1
102#define IOAPIC_MAP_CHECK 0x2
101 103
102#ifdef CONFIG_X86_IO_APIC 104#ifdef CONFIG_X86_IO_APIC
103 105
@@ -118,9 +120,6 @@ extern int mp_irq_entries;
118/* MP IRQ source entries */ 120/* MP IRQ source entries */
119extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 121extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
120 122
121/* non-0 if default (table-less) MP configuration */
122extern int mpc_default_type;
123
124/* Older SiS APIC requires we rewrite the index register */ 123/* Older SiS APIC requires we rewrite the index register */
125extern int sis_apic_bug; 124extern int sis_apic_bug;
126 125
@@ -133,9 +132,6 @@ extern int noioapicquirk;
133/* -1 if "noapic" boot option passed */ 132/* -1 if "noapic" boot option passed */
134extern int noioapicreroute; 133extern int noioapicreroute;
135 134
136/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
137extern int timer_through_8259;
138
139/* 135/*
140 * If we use the IO-APIC for IRQ routing, disable automatic 136 * If we use the IO-APIC for IRQ routing, disable automatic
141 * assignment of PCI IRQ's. 137 * assignment of PCI IRQ's.
@@ -145,24 +141,17 @@ extern int timer_through_8259;
145 141
146struct io_apic_irq_attr; 142struct io_apic_irq_attr;
147struct irq_cfg; 143struct irq_cfg;
148extern int io_apic_set_pci_routing(struct device *dev, int irq,
149 struct io_apic_irq_attr *irq_attr);
150void setup_IO_APIC_irq_extra(u32 gsi);
151extern void ioapic_insert_resources(void); 144extern void ioapic_insert_resources(void);
152 145
153extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, 146extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
154 unsigned int, int, 147 unsigned int, int,
155 struct io_apic_irq_attr *); 148 struct io_apic_irq_attr *);
156extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
157 unsigned int, int,
158 struct io_apic_irq_attr *);
159extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); 149extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
160 150
161extern void native_compose_msi_msg(struct pci_dev *pdev, 151extern void native_compose_msi_msg(struct pci_dev *pdev,
162 unsigned int irq, unsigned int dest, 152 unsigned int irq, unsigned int dest,
163 struct msi_msg *msg, u8 hpet_id); 153 struct msi_msg *msg, u8 hpet_id);
164extern void native_eoi_ioapic_pin(int apic, int pin, int vector); 154extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
165int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
166 155
167extern int save_ioapic_entries(void); 156extern int save_ioapic_entries(void);
168extern void mask_ioapic_entries(void); 157extern void mask_ioapic_entries(void);
@@ -171,15 +160,40 @@ extern int restore_ioapic_entries(void);
171extern void setup_ioapic_ids_from_mpc(void); 160extern void setup_ioapic_ids_from_mpc(void);
172extern void setup_ioapic_ids_from_mpc_nocheck(void); 161extern void setup_ioapic_ids_from_mpc_nocheck(void);
173 162
163enum ioapic_domain_type {
164 IOAPIC_DOMAIN_INVALID,
165 IOAPIC_DOMAIN_LEGACY,
166 IOAPIC_DOMAIN_STRICT,
167 IOAPIC_DOMAIN_DYNAMIC,
168};
169
170struct device_node;
171struct irq_domain;
172struct irq_domain_ops;
173
174struct ioapic_domain_cfg {
175 enum ioapic_domain_type type;
176 const struct irq_domain_ops *ops;
177 struct device_node *dev;
178};
179
174struct mp_ioapic_gsi{ 180struct mp_ioapic_gsi{
175 u32 gsi_base; 181 u32 gsi_base;
176 u32 gsi_end; 182 u32 gsi_end;
177}; 183};
178extern struct mp_ioapic_gsi mp_gsi_routing[];
179extern u32 gsi_top; 184extern u32 gsi_top;
180int mp_find_ioapic(u32 gsi); 185
181int mp_find_ioapic_pin(int ioapic, u32 gsi); 186extern int mp_find_ioapic(u32 gsi);
182void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); 187extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
188extern u32 mp_pin_to_gsi(int ioapic, int pin);
189extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags);
190extern void mp_unmap_irq(int irq);
191extern void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
192 struct ioapic_domain_cfg *cfg);
193extern int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
194 irq_hw_number_t hwirq);
195extern void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq);
196extern int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node);
183extern void __init pre_init_apic_IRQ0(void); 197extern void __init pre_init_apic_IRQ0(void);
184 198
185extern void mp_save_irq(struct mpc_intsrc *m); 199extern void mp_save_irq(struct mpc_intsrc *m);
@@ -217,14 +231,12 @@ extern void io_apic_eoi(unsigned int apic, unsigned int vector);
217 231
218#define io_apic_assign_pci_irqs 0 232#define io_apic_assign_pci_irqs 0
219#define setup_ioapic_ids_from_mpc x86_init_noop 233#define setup_ioapic_ids_from_mpc x86_init_noop
220static const int timer_through_8259 = 0;
221static inline void ioapic_insert_resources(void) { } 234static inline void ioapic_insert_resources(void) { }
222#define gsi_top (NR_IRQS_LEGACY) 235#define gsi_top (NR_IRQS_LEGACY)
223static inline int mp_find_ioapic(u32 gsi) { return 0; } 236static inline int mp_find_ioapic(u32 gsi) { return 0; }
224 237static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; }
225struct io_apic_irq_attr; 238static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags) { return gsi; }
226static inline int io_apic_set_pci_routing(struct device *dev, int irq, 239static inline void mp_unmap_irq(int irq) { }
227 struct io_apic_irq_attr *irq_attr) { return 0; }
228 240
229static inline int save_ioapic_entries(void) 241static inline int save_ioapic_entries(void)
230{ 242{
diff --git a/arch/x86/include/asm/kexec-bzimage64.h b/arch/x86/include/asm/kexec-bzimage64.h
new file mode 100644
index 000000000000..d1b5d194e31d
--- /dev/null
+++ b/arch/x86/include/asm/kexec-bzimage64.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_KEXEC_BZIMAGE64_H
2#define _ASM_KEXEC_BZIMAGE64_H
3
4extern struct kexec_file_ops kexec_bzImage64_ops;
5
6#endif /* _ASM_KEXE_BZIMAGE64_H */
diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h
index 17483a492f18..d2434c1cad05 100644
--- a/arch/x86/include/asm/kexec.h
+++ b/arch/x86/include/asm/kexec.h
@@ -23,6 +23,9 @@
23 23
24#include <asm/page.h> 24#include <asm/page.h>
25#include <asm/ptrace.h> 25#include <asm/ptrace.h>
26#include <asm/bootparam.h>
27
28struct kimage;
26 29
27/* 30/*
28 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return. 31 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
@@ -61,6 +64,10 @@
61# define KEXEC_ARCH KEXEC_ARCH_X86_64 64# define KEXEC_ARCH KEXEC_ARCH_X86_64
62#endif 65#endif
63 66
67/* Memory to backup during crash kdump */
68#define KEXEC_BACKUP_SRC_START (0UL)
69#define KEXEC_BACKUP_SRC_END (640 * 1024UL) /* 640K */
70
64/* 71/*
65 * CPU does not save ss and sp on stack if execution is already 72 * CPU does not save ss and sp on stack if execution is already
66 * running in kernel mode at the time of NMI occurrence. This code 73 * running in kernel mode at the time of NMI occurrence. This code
@@ -160,6 +167,44 @@ struct kimage_arch {
160 pud_t *pud; 167 pud_t *pud;
161 pmd_t *pmd; 168 pmd_t *pmd;
162 pte_t *pte; 169 pte_t *pte;
170 /* Details of backup region */
171 unsigned long backup_src_start;
172 unsigned long backup_src_sz;
173
174 /* Physical address of backup segment */
175 unsigned long backup_load_addr;
176
177 /* Core ELF header buffer */
178 void *elf_headers;
179 unsigned long elf_headers_sz;
180 unsigned long elf_load_addr;
181};
182#endif /* CONFIG_X86_32 */
183
184#ifdef CONFIG_X86_64
185/*
186 * Number of elements and order of elements in this structure should match
187 * with the ones in arch/x86/purgatory/entry64.S. If you make a change here
188 * make an appropriate change in purgatory too.
189 */
190struct kexec_entry64_regs {
191 uint64_t rax;
192 uint64_t rcx;
193 uint64_t rdx;
194 uint64_t rbx;
195 uint64_t rsp;
196 uint64_t rbp;
197 uint64_t rsi;
198 uint64_t rdi;
199 uint64_t r8;
200 uint64_t r9;
201 uint64_t r10;
202 uint64_t r11;
203 uint64_t r12;
204 uint64_t r13;
205 uint64_t r14;
206 uint64_t r15;
207 uint64_t rip;
163}; 208};
164#endif 209#endif
165 210
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index f5a617956735..b07233b64578 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -40,8 +40,6 @@ extern int mp_bus_id_to_type[MAX_MP_BUSSES];
40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
41 41
42extern unsigned int boot_cpu_physical_apicid; 42extern unsigned int boot_cpu_physical_apicid;
43extern unsigned int max_physical_apicid;
44extern int mpc_default_type;
45extern unsigned long mp_lapic_addr; 43extern unsigned long mp_lapic_addr;
46 44
47#ifdef CONFIG_X86_LOCAL_APIC 45#ifdef CONFIG_X86_LOCAL_APIC
@@ -88,15 +86,6 @@ static inline void early_reserve_e820_mpc_new(void) { }
88#endif 86#endif
89 87
90int generic_processor_info(int apicid, int version); 88int generic_processor_info(int apicid, int version);
91#ifdef CONFIG_ACPI
92extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
93extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
94 u32 gsi);
95extern void mp_config_acpi_legacy_irqs(void);
96struct device;
97extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
98 int active_high_low);
99#endif /* CONFIG_ACPI */
100 89
101#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) 90#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
102 91
@@ -161,8 +150,4 @@ static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
161 150
162extern physid_mask_t phys_cpu_present_map; 151extern physid_mask_t phys_cpu_present_map;
163 152
164extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
165
166extern int default_acpi_madt_oem_check(char *, char *);
167
168#endif /* _ASM_X86_MPSPEC_H */ 153#endif /* _ASM_X86_MPSPEC_H */
diff --git a/arch/x86/include/asm/page.h b/arch/x86/include/asm/page.h
index 775873d3be55..802dde30c928 100644
--- a/arch/x86/include/asm/page.h
+++ b/arch/x86/include/asm/page.h
@@ -70,7 +70,6 @@ extern bool __virt_addr_valid(unsigned long kaddr);
70#include <asm-generic/memory_model.h> 70#include <asm-generic/memory_model.h>
71#include <asm-generic/getorder.h> 71#include <asm-generic/getorder.h>
72 72
73#define __HAVE_ARCH_GATE_AREA 1
74#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA 73#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
75 74
76#endif /* __KERNEL__ */ 75#endif /* __KERNEL__ */
diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
index 0f1ddee6a0ce..f408caf73430 100644
--- a/arch/x86/include/asm/page_64.h
+++ b/arch/x86/include/asm/page_64.h
@@ -39,4 +39,6 @@ void copy_page(void *to, void *from);
39 39
40#endif /* !__ASSEMBLY__ */ 40#endif /* !__ASSEMBLY__ */
41 41
42#define __HAVE_ARCH_GATE_AREA 1
43
42#endif /* _ASM_X86_PAGE_64_H */ 44#endif /* _ASM_X86_PAGE_64_H */
diff --git a/arch/x86/include/asm/platform_sst_audio.h b/arch/x86/include/asm/platform_sst_audio.h
new file mode 100644
index 000000000000..0a4e140315b6
--- /dev/null
+++ b/arch/x86/include/asm/platform_sst_audio.h
@@ -0,0 +1,78 @@
1/*
2 * platform_sst_audio.h: sst audio platform data header file
3 *
4 * Copyright (C) 2012-14 Intel Corporation
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
7 * Vinod Koul ,vinod.koul@intel.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2
12 * of the License.
13 */
14#ifndef _PLATFORM_SST_AUDIO_H_
15#define _PLATFORM_SST_AUDIO_H_
16
17#include <linux/sfi.h>
18
19enum sst_audio_task_id_mrfld {
20 SST_TASK_ID_NONE = 0,
21 SST_TASK_ID_SBA = 1,
22 SST_TASK_ID_MEDIA = 3,
23 SST_TASK_ID_MAX = SST_TASK_ID_MEDIA,
24};
25
26/* Device IDs for Merrifield are Pipe IDs,
27 * ref: DSP spec v0.75 */
28enum sst_audio_device_id_mrfld {
29 /* Output pipeline IDs */
30 PIPE_ID_OUT_START = 0x0,
31 PIPE_CODEC_OUT0 = 0x2,
32 PIPE_CODEC_OUT1 = 0x3,
33 PIPE_SPROT_LOOP_OUT = 0x4,
34 PIPE_MEDIA_LOOP1_OUT = 0x5,
35 PIPE_MEDIA_LOOP2_OUT = 0x6,
36 PIPE_VOIP_OUT = 0xC,
37 PIPE_PCM0_OUT = 0xD,
38 PIPE_PCM1_OUT = 0xE,
39 PIPE_PCM2_OUT = 0xF,
40 PIPE_MEDIA0_OUT = 0x12,
41 PIPE_MEDIA1_OUT = 0x13,
42/* Input Pipeline IDs */
43 PIPE_ID_IN_START = 0x80,
44 PIPE_CODEC_IN0 = 0x82,
45 PIPE_CODEC_IN1 = 0x83,
46 PIPE_SPROT_LOOP_IN = 0x84,
47 PIPE_MEDIA_LOOP1_IN = 0x85,
48 PIPE_MEDIA_LOOP2_IN = 0x86,
49 PIPE_VOIP_IN = 0x8C,
50 PIPE_PCM0_IN = 0x8D,
51 PIPE_PCM1_IN = 0x8E,
52 PIPE_MEDIA0_IN = 0x8F,
53 PIPE_MEDIA1_IN = 0x90,
54 PIPE_MEDIA2_IN = 0x91,
55 PIPE_RSVD = 0xFF,
56};
57
58/* The stream map for each platform consists of an array of the below
59 * stream map structure.
60 */
61struct sst_dev_stream_map {
62 u8 dev_num; /* device id */
63 u8 subdev_num; /* substream */
64 u8 direction;
65 u8 device_id; /* fw id */
66 u8 task_id; /* fw task */
67 u8 status;
68};
69
70struct sst_platform_data {
71 /* Intel software platform id*/
72 struct sst_dev_stream_map *pdev_strm_map;
73 unsigned int strm_map_size;
74};
75
76int add_sst_platform_device(void);
77#endif
78
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index ee30b9f0b91c..eb71ec794732 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -385,8 +385,8 @@ struct bndcsr_struct {
385 385
386struct xsave_hdr_struct { 386struct xsave_hdr_struct {
387 u64 xstate_bv; 387 u64 xstate_bv;
388 u64 reserved1[2]; 388 u64 xcomp_bv;
389 u64 reserved2[5]; 389 u64 reserved[6];
390} __attribute__((packed)); 390} __attribute__((packed));
391 391
392struct xsave_struct { 392struct xsave_struct {
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index fbeb06ed0eaa..1d081ac1cd69 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -26,12 +26,10 @@
26extern int of_ioapic; 26extern int of_ioapic;
27extern u64 initial_dtb; 27extern u64 initial_dtb;
28extern void add_dtb(u64 data); 28extern void add_dtb(u64 data);
29extern void x86_add_irq_domains(void);
30void x86_of_pci_init(void); 29void x86_of_pci_init(void);
31void x86_dtb_init(void); 30void x86_dtb_init(void);
32#else 31#else
33static inline void add_dtb(u64 data) { } 32static inline void add_dtb(u64 data) { }
34static inline void x86_add_irq_domains(void) { }
35static inline void x86_of_pci_init(void) { } 33static inline void x86_of_pci_init(void) { }
36static inline void x86_dtb_init(void) { } 34static inline void x86_dtb_init(void) { }
37#define of_ioapic 0 35#define of_ioapic 0
diff --git a/arch/x86/include/asm/scatterlist.h b/arch/x86/include/asm/scatterlist.h
deleted file mode 100644
index 4240878b9d76..000000000000
--- a/arch/x86/include/asm/scatterlist.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _ASM_X86_SCATTERLIST_H
2#define _ASM_X86_SCATTERLIST_H
3
4#include <asm-generic/scatterlist.h>
5
6#define ARCH_HAS_SG_CHAIN
7
8#endif /* _ASM_X86_SCATTERLIST_H */
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 49adfd7bb4a4..0da7409f0bec 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -17,11 +17,11 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
17 spin_unlock_irqrestore(&rtc_lock, flags); 17 spin_unlock_irqrestore(&rtc_lock, flags);
18 local_flush_tlb(); 18 local_flush_tlb();
19 pr_debug("1.\n"); 19 pr_debug("1.\n");
20 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) = 20 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
21 start_eip >> 4; 21 start_eip >> 4;
22 pr_debug("2.\n"); 22 pr_debug("2.\n");
23 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_low)) = 23 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
24 start_eip & 0xf; 24 start_eip & 0xf;
25 pr_debug("3.\n"); 25 pr_debug("3.\n");
26} 26}
27 27
@@ -42,7 +42,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
42 CMOS_WRITE(0, 0xf); 42 CMOS_WRITE(0, 0xf);
43 spin_unlock_irqrestore(&rtc_lock, flags); 43 spin_unlock_irqrestore(&rtc_lock, flags);
44 44
45 *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0; 45 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
46} 46}
47 47
48static inline void __init smpboot_setup_io_apic(void) 48static inline void __init smpboot_setup_io_apic(void)
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index d949ef28c48b..7e7a79ada658 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -52,24 +52,170 @@ extern void xsave_init(void);
52extern void update_regset_xstate_info(unsigned int size, u64 xstate_mask); 52extern void update_regset_xstate_info(unsigned int size, u64 xstate_mask);
53extern int init_fpu(struct task_struct *child); 53extern int init_fpu(struct task_struct *child);
54 54
55static inline int fpu_xrstor_checking(struct xsave_struct *fx) 55/* These macros all use (%edi)/(%rdi) as the single memory argument. */
56#define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
57#define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
58#define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
59#define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
60#define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
61
62#define xstate_fault ".section .fixup,\"ax\"\n" \
63 "3: movl $-1,%[err]\n" \
64 " jmp 2b\n" \
65 ".previous\n" \
66 _ASM_EXTABLE(1b, 3b) \
67 : [err] "=r" (err)
68
69/*
70 * This function is called only during boot time when x86 caps are not set
71 * up and alternative can not be used yet.
72 */
73static inline int xsave_state_booting(struct xsave_struct *fx, u64 mask)
56{ 74{
57 int err; 75 u32 lmask = mask;
76 u32 hmask = mask >> 32;
77 int err = 0;
78
79 WARN_ON(system_state != SYSTEM_BOOTING);
80
81 if (boot_cpu_has(X86_FEATURE_XSAVES))
82 asm volatile("1:"XSAVES"\n\t"
83 "2:\n\t"
84 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
85 : "memory");
86 else
87 asm volatile("1:"XSAVE"\n\t"
88 "2:\n\t"
89 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
90 : "memory");
91
92 asm volatile(xstate_fault
93 : "0" (0)
94 : "memory");
95
96 return err;
97}
98
99/*
100 * This function is called only during boot time when x86 caps are not set
101 * up and alternative can not be used yet.
102 */
103static inline int xrstor_state_booting(struct xsave_struct *fx, u64 mask)
104{
105 u32 lmask = mask;
106 u32 hmask = mask >> 32;
107 int err = 0;
108
109 WARN_ON(system_state != SYSTEM_BOOTING);
58 110
59 asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t" 111 if (boot_cpu_has(X86_FEATURE_XSAVES))
60 "2:\n" 112 asm volatile("1:"XRSTORS"\n\t"
61 ".section .fixup,\"ax\"\n" 113 "2:\n\t"
62 "3: movl $-1,%[err]\n" 114 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
63 " jmp 2b\n" 115 : "memory");
64 ".previous\n" 116 else
65 _ASM_EXTABLE(1b, 3b) 117 asm volatile("1:"XRSTOR"\n\t"
66 : [err] "=r" (err) 118 "2:\n\t"
67 : "D" (fx), "m" (*fx), "a" (-1), "d" (-1), "0" (0) 119 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
120 : "memory");
121
122 asm volatile(xstate_fault
123 : "0" (0)
124 : "memory");
125
126 return err;
127}
128
129/*
130 * Save processor xstate to xsave area.
131 */
132static inline int xsave_state(struct xsave_struct *fx, u64 mask)
133{
134 u32 lmask = mask;
135 u32 hmask = mask >> 32;
136 int err = 0;
137
138 /*
139 * If xsaves is enabled, xsaves replaces xsaveopt because
140 * it supports compact format and supervisor states in addition to
141 * modified optimization in xsaveopt.
142 *
143 * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave
144 * because xsaveopt supports modified optimization which is not
145 * supported by xsave.
146 *
147 * If none of xsaves and xsaveopt is enabled, use xsave.
148 */
149 alternative_input_2(
150 "1:"XSAVE,
151 "1:"XSAVEOPT,
152 X86_FEATURE_XSAVEOPT,
153 "1:"XSAVES,
154 X86_FEATURE_XSAVES,
155 [fx] "D" (fx), "a" (lmask), "d" (hmask) :
156 "memory");
157 asm volatile("2:\n\t"
158 xstate_fault
159 : "0" (0)
68 : "memory"); 160 : "memory");
69 161
70 return err; 162 return err;
71} 163}
72 164
165/*
166 * Restore processor xstate from xsave area.
167 */
168static inline int xrstor_state(struct xsave_struct *fx, u64 mask)
169{
170 int err = 0;
171 u32 lmask = mask;
172 u32 hmask = mask >> 32;
173
174 /*
175 * Use xrstors to restore context if it is enabled. xrstors supports
176 * compacted format of xsave area which is not supported by xrstor.
177 */
178 alternative_input(
179 "1: " XRSTOR,
180 "1: " XRSTORS,
181 X86_FEATURE_XSAVES,
182 "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
183 : "memory");
184
185 asm volatile("2:\n"
186 xstate_fault
187 : "0" (0)
188 : "memory");
189
190 return err;
191}
192
193/*
194 * Save xstate context for old process during context switch.
195 */
196static inline void fpu_xsave(struct fpu *fpu)
197{
198 xsave_state(&fpu->state->xsave, -1);
199}
200
201/*
202 * Restore xstate context for new process during context switch.
203 */
204static inline int fpu_xrstor_checking(struct xsave_struct *fx)
205{
206 return xrstor_state(fx, -1);
207}
208
209/*
210 * Save xstate to user space xsave area.
211 *
212 * We don't use modified optimization because xrstor/xrstors might track
213 * a different application.
214 *
215 * We don't use compacted format xsave area for
216 * backward compatibility for old applications which don't understand
217 * compacted format of xsave area.
218 */
73static inline int xsave_user(struct xsave_struct __user *buf) 219static inline int xsave_user(struct xsave_struct __user *buf)
74{ 220{
75 int err; 221 int err;
@@ -83,69 +229,34 @@ static inline int xsave_user(struct xsave_struct __user *buf)
83 return -EFAULT; 229 return -EFAULT;
84 230
85 __asm__ __volatile__(ASM_STAC "\n" 231 __asm__ __volatile__(ASM_STAC "\n"
86 "1: .byte " REX_PREFIX "0x0f,0xae,0x27\n" 232 "1:"XSAVE"\n"
87 "2: " ASM_CLAC "\n" 233 "2: " ASM_CLAC "\n"
88 ".section .fixup,\"ax\"\n" 234 xstate_fault
89 "3: movl $-1,%[err]\n"
90 " jmp 2b\n"
91 ".previous\n"
92 _ASM_EXTABLE(1b,3b)
93 : [err] "=r" (err)
94 : "D" (buf), "a" (-1), "d" (-1), "0" (0) 235 : "D" (buf), "a" (-1), "d" (-1), "0" (0)
95 : "memory"); 236 : "memory");
96 return err; 237 return err;
97} 238}
98 239
240/*
241 * Restore xstate from user space xsave area.
242 */
99static inline int xrestore_user(struct xsave_struct __user *buf, u64 mask) 243static inline int xrestore_user(struct xsave_struct __user *buf, u64 mask)
100{ 244{
101 int err; 245 int err = 0;
102 struct xsave_struct *xstate = ((__force struct xsave_struct *)buf); 246 struct xsave_struct *xstate = ((__force struct xsave_struct *)buf);
103 u32 lmask = mask; 247 u32 lmask = mask;
104 u32 hmask = mask >> 32; 248 u32 hmask = mask >> 32;
105 249
106 __asm__ __volatile__(ASM_STAC "\n" 250 __asm__ __volatile__(ASM_STAC "\n"
107 "1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n" 251 "1:"XRSTOR"\n"
108 "2: " ASM_CLAC "\n" 252 "2: " ASM_CLAC "\n"
109 ".section .fixup,\"ax\"\n" 253 xstate_fault
110 "3: movl $-1,%[err]\n"
111 " jmp 2b\n"
112 ".previous\n"
113 _ASM_EXTABLE(1b,3b)
114 : [err] "=r" (err)
115 : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0) 254 : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0)
116 : "memory"); /* memory required? */ 255 : "memory"); /* memory required? */
117 return err; 256 return err;
118} 257}
119 258
120static inline void xrstor_state(struct xsave_struct *fx, u64 mask) 259void *get_xsave_addr(struct xsave_struct *xsave, int xstate);
121{ 260void setup_xstate_comp(void);
122 u32 lmask = mask;
123 u32 hmask = mask >> 32;
124
125 asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
126 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
127 : "memory");
128}
129
130static inline void xsave_state(struct xsave_struct *fx, u64 mask)
131{
132 u32 lmask = mask;
133 u32 hmask = mask >> 32;
134 261
135 asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x27\n\t"
136 : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
137 : "memory");
138}
139
140static inline void fpu_xsave(struct fpu *fpu)
141{
142 /* This, however, we can work around by forcing the compiler to select
143 an addressing mode that doesn't require extended registers. */
144 alternative_input(
145 ".byte " REX_PREFIX "0x0f,0xae,0x27",
146 ".byte " REX_PREFIX "0x0f,0xae,0x37",
147 X86_FEATURE_XSAVEOPT,
148 [fx] "D" (&fpu->state->xsave), "a" (-1), "d" (-1) :
149 "memory");
150}
151#endif 262#endif
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index eac9e92fe181..e21331ce368f 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -149,6 +149,9 @@
149 149
150#define MSR_CORE_C1_RES 0x00000660 150#define MSR_CORE_C1_RES 0x00000660
151 151
152#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
153#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
154
152#define MSR_AMD64_MC0_MASK 0xc0010044 155#define MSR_AMD64_MC0_MASK 0xc0010044
153 156
154#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 157#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 13:19:12 -0500