2 files changed, 36 insertions, 0 deletions

diff --git a/arch/x86/include/asm/insn.h b/arch/x86/include/asm/insn.h
index 88c765e16410..74df3f1eddfd 100644
--- a/arch/x86/include/asm/insn.h
+++ b/arch/x86/include/asm/insn.h
@@ -137,6 +137,13 @@ static inline int insn_is_avx(struct insn *insn)
         return (insn->vex_prefix.value != 0);
 }
 
+/* Ensure this instruction is decoded completely */
+static inline int insn_complete(struct insn *insn)
+{
+        return insn->opcode.got && insn->modrm.got && insn->sib.got &&
+                insn->displacement.got && insn->immediate.got;
+}
+
 static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
 {
         if (insn->vex_prefix.nbytes == 2)       /* 2 bytes VEX */
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index f61c62f7d5d8..b50e9d15aae0 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -57,6 +57,7 @@
                 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
 
 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED              6
+#define ARCH_PERFMON_EVENTS_COUNT                       7
 
 /*
  * Intel "Architectural Performance Monitoring" CPUID
@@ -72,6 +73,19 @@ union cpuid10_eax {
         unsigned int full;
 };
 
+union cpuid10_ebx {
+        struct {
+                unsigned int no_unhalted_core_cycles:1;
+                unsigned int no_instructions_retired:1;
+                unsigned int no_unhalted_reference_cycles:1;
+                unsigned int no_llc_reference:1;
+                unsigned int no_llc_misses:1;
+                unsigned int no_branch_instruction_retired:1;
+                unsigned int no_branch_misses_retired:1;
+        } split;
+        unsigned int full;
+};
+
 union cpuid10_edx {
         struct {
                 unsigned int num_counters_fixed:5;
@@ -81,6 +95,15 @@ union cpuid10_edx {
         unsigned int full;
 };
 
+struct x86_pmu_capability {
+        int             version;
+        int             num_counters_gp;
+        int             num_counters_fixed;
+        int             bit_width_gp;
+        int             bit_width_fixed;
+        unsigned int    events_mask;
+        int             events_mask_len;
+};
 
 /*
  * Fixed-purpose performance events:
@@ -202,6 +225,7 @@ struct perf_guest_switch_msr {
 };
 
 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
+extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
 #else
 static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
 {
@@ -209,6 +233,11 @@ static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
         return NULL;
 }
 
+static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
+{
+        memset(cap, 0, sizeof(*cap));
+}
+
 static inline void perf_events_lapic_init(void) { }
 #endif