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-rw-r--r--arch/x86/include/asm/mce.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index ba1f8890cf51..afd3cdf6f8ad 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -15,6 +15,7 @@
15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ 15#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
16#define MCG_EXT_CNT_SHIFT 16 16#define MCG_EXT_CNT_SHIFT 16
17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) 17#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
18 19
19#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ 20#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
20#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ 21#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
@@ -27,6 +28,15 @@
27#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ 28#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
28#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ 29#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
29#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ 30#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
31#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
32#define MCI_STATUS_AR (1ULL<<55) /* Action required */
33
34/* MISC register defines */
35#define MCM_ADDR_SEGOFF 0 /* segment offset */
36#define MCM_ADDR_LINEAR 1 /* linear address */
37#define MCM_ADDR_PHYS 2 /* physical address */
38#define MCM_ADDR_MEM 3 /* memory address */
39#define MCM_ADDR_GENERIC 7 /* generic */
30 40
31/* Fields are zero when not available */ 41/* Fields are zero when not available */
32struct mce { 42struct mce {