8 files changed, 66 insertions, 15 deletions

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 394d177d721b..00f5962d82d0 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -108,6 +108,16 @@ extern void native_apic_icr_write(u32 low, u32 id);
 extern u64 native_apic_icr_read(void);
 
 #ifdef CONFIG_X86_X2APIC
+/*
+ * Make previous memory operations globally visible before
+ * sending the IPI through x2apic wrmsr. We need a serializing instruction or
+ * mfence for this.
+ */
+static inline void x2apic_wrmsr_fence(void)
+{
+        asm volatile("mfence" : : : "memory");
+}
+
 static inline void native_apic_msr_write(u32 reg, u32 v)
 {
         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
@@ -184,6 +194,9 @@ static inline int x2apic_enabled(void)
 {
         return 0;
 }
+
+#define x2apic  0
+
 #endif
 
 extern int get_physical_broadcast(void);
diff --git a/arch/x86/include/asm/cpu_debug.h b/arch/x86/include/asm/cpu_debug.h
index d24d64fcee04..222802029fa6 100755
--- a/arch/x86/include/asm/cpu_debug.h
+++ b/arch/x86/include/asm/cpu_debug.h
@@ -33,6 +33,8 @@ enum cpu_debug_bit {
         CPU_VMX_BIT,                            /* VMX                  */
         CPU_CALL_BIT,                           /* System Call          */
         CPU_BASE_BIT,                           /* BASE Address         */
+        CPU_VER_BIT,                            /* Version ID           */
+        CPU_CONF_BIT,                           /* Configuration        */
         CPU_SMM_BIT,                            /* System mgmt mode     */
         CPU_SVM_BIT,                            /*Secure Virtual Machine*/
         CPU_OSVM_BIT,                           /* OS-Visible Workaround*/
@@ -69,6 +71,8 @@ enum cpu_debug_bit {
 #define CPU_VMX                 (1 << CPU_VMX_BIT)
 #define CPU_CALL                (1 << CPU_CALL_BIT)
 #define CPU_BASE                (1 << CPU_BASE_BIT)
+#define CPU_VER                 (1 << CPU_VER_BIT)
+#define CPU_CONF                (1 << CPU_CONF_BIT)
 #define CPU_SMM                 (1 << CPU_SMM_BIT)
 #define CPU_SVM                 (1 << CPU_SVM_BIT)
 #define CPU_OSVM                (1 << CPU_OSVM_BIT)
@@ -123,10 +127,15 @@ enum cpu_processor_bit {
         CPU_INTEL_ATOM_BIT,
         CPU_INTEL_XEON_P4_BIT,
         CPU_INTEL_XEON_MP_BIT,
+/* AMD */
+        CPU_AMD_K6_BIT,
+        CPU_AMD_K7_BIT,
+        CPU_AMD_K8_BIT,
+        CPU_AMD_0F_BIT,
+        CPU_AMD_10_BIT,
+        CPU_AMD_11_BIT,
 };
 
-#define CPU_ALL                 (~0)            /* Select all CPUs      */
-
 #define CPU_INTEL_PENTIUM       (1 << CPU_INTEL_PENTIUM_BIT)
 #define CPU_INTEL_P6            (1 << CPU_INTEL_P6_BIT)
 #define CPU_INTEL_PENTIUM_M     (1 << CPU_INTEL_PENTIUM_M_BIT)
@@ -156,9 +165,27 @@ enum cpu_processor_bit {
 #define CPU_PX_CX_AT            (CPU_INTEL_PX | CPU_CX_AT)
 #define CPU_PX_CX_AT_XE         (CPU_INTEL_PX | CPU_CX_AT_XE)
 
-/* Select all Intel CPUs*/
+/* Select all supported Intel CPUs */
 #define CPU_INTEL_ALL           (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE)
 
+#define CPU_AMD_K6              (1 << CPU_AMD_K6_BIT)
+#define CPU_AMD_K7              (1 << CPU_AMD_K7_BIT)
+#define CPU_AMD_K8              (1 << CPU_AMD_K8_BIT)
+#define CPU_AMD_0F              (1 << CPU_AMD_0F_BIT)
+#define CPU_AMD_10              (1 << CPU_AMD_10_BIT)
+#define CPU_AMD_11              (1 << CPU_AMD_11_BIT)
+
+#define CPU_K10_PLUS            (CPU_AMD_10 | CPU_AMD_11)
+#define CPU_K0F_PLUS            (CPU_AMD_0F | CPU_K10_PLUS)
+#define CPU_K8_PLUS             (CPU_AMD_K8 | CPU_K0F_PLUS)
+#define CPU_K7_PLUS             (CPU_AMD_K7 | CPU_K8_PLUS)
+
+/* Select all supported AMD CPUs */
+#define CPU_AMD_ALL             (CPU_AMD_K6 | CPU_K7_PLUS)
+
+/* Select all supported CPUs */
+#define CPU_ALL                 (CPU_INTEL_ALL | CPU_AMD_ALL)
+
 #define MAX_CPU_FILES           512
 
 struct cpu_private {
@@ -171,16 +198,22 @@ struct cpu_private {
 struct cpu_debug_base {
         char                    *name;          /* Register name        */
         unsigned                flag;           /* Register flag        */
+        unsigned                write;          /* Register write flag  */
 };
 
-struct cpu_cpuX_base {
-        struct dentry           *dentry;        /* Register dentry      */
-        int                     init;           /* Register index file  */
-};
-
+/*
+ * Currently it looks similar to cpu_debug_base but once we add more files
+ * cpu_file_base will go in different direction
+ */
 struct cpu_file_base {
         char                    *name;          /* Register file name   */
         unsigned                flag;           /* Register file flag   */
+        unsigned                write;          /* Register write flag  */
+};
+
+struct cpu_cpuX_base {
+        struct dentry           *dentry;        /* Register dentry      */
+        int                     init;           /* Register index file  */
 };
 
 struct cpu_debug_range {
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 59cb4a1317b7..373cc2bbcad2 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -162,7 +162,8 @@ extern int (*ioapic_renumber_irq)(int ioapic, int irq);
 extern void ioapic_init_mappings(void);
 
 #ifdef CONFIG_X86_64
-extern int save_mask_IO_APIC_setup(void);
+extern int save_IO_APIC_setup(void);
+extern void mask_IO_APIC_setup(void);
 extern void restore_IO_APIC_setup(void);
 extern void reinit_intr_remapped_IO_APIC(int);
 #endif
@@ -172,7 +173,7 @@ extern void probe_nr_irqs_gsi(void);
 extern int setup_ioapic_entry(int apic, int irq,
                               struct IO_APIC_route_entry *entry,
                               unsigned int destination, int trigger,
-                              int polarity, int vector);
+                              int polarity, int vector, int pin);
 extern void ioapic_write_entry(int apic, int pin,
                                struct IO_APIC_route_entry e);
 #else  /* !CONFIG_X86_IO_APIC */
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 20e1fd588dbf..0396760fccb8 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -1,8 +1,6 @@
 #ifndef _ASM_X86_IRQ_REMAPPING_H
 #define _ASM_X86_IRQ_REMAPPING_H
 
-extern int x2apic;
-
 #define IRTE_DEST(dest) ((x2apic) ? dest : dest << 8)
 
 #endif  /* _ASM_X86_IRQ_REMAPPING_H */
diff --git a/arch/x86/include/asm/msidef.h b/arch/x86/include/asm/msidef.h
index 6706b3006f13..4cc48af23fef 100644
--- a/arch/x86/include/asm/msidef.h
+++ b/arch/x86/include/asm/msidef.h
@@ -47,6 +47,7 @@
 #define  MSI_ADDR_DEST_ID_MASK          0x00ffff0
 #define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
                                          MSI_ADDR_DEST_ID_MASK)
+#define MSI_ADDR_EXT_DEST_ID(dest)      ((dest) & 0xffffff00)
 
 #define MSI_ADDR_IR_EXT_INT             (1 << 4)
 #define MSI_ADDR_IR_SHV                 (1 << 3)
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 0617d5cc9712..31fe83b10a4f 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -389,7 +389,7 @@ extern struct pv_lock_ops pv_lock_ops;
 
 #define paravirt_type(op)                               \
         [paravirt_typenum] "i" (PARAVIRT_PATCH(op)),    \
-        [paravirt_opptr] "m" (op)
+        [paravirt_opptr] "i" (&(op))
 #define paravirt_clobber(clobber)               \
         [paravirt_clobber] "i" (clobber)
 
@@ -443,7 +443,7 @@ int paravirt_disable_iospace(void);
  * offset into the paravirt_patch_template structure, and can therefore be
  * freely converted back into a structure offset.
  */
-#define PARAVIRT_CALL   "call *%[paravirt_opptr];"
+#define PARAVIRT_CALL   "call *%c[paravirt_opptr];"
 
 /*
  * These macros are intended to wrap calls through one of the paravirt
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 76139506c3e4..ae85a8d66a30 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -75,9 +75,9 @@ struct cpuinfo_x86 {
 #else
         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
         int                     x86_tlbsize;
+#endif
         __u8                    x86_virt_bits;
         __u8                    x86_phys_bits;
-#endif
         /* CPUID returned core id bits: */
         __u8                    x86_coreid_bits;
         /* Max extended CPUID function supported: */
@@ -391,6 +391,9 @@ DECLARE_PER_CPU(union irq_stack_union, irq_stack_union);
 DECLARE_INIT_PER_CPU(irq_stack_union);
 
 DECLARE_PER_CPU(char *, irq_stack_ptr);
+DECLARE_PER_CPU(unsigned int, irq_count);
+extern unsigned long kernel_eflags;
+extern asmlinkage void ignore_sysret(void);
 #else   /* X86_64 */
 #ifdef CONFIG_CC_STACKPROTECTOR
 DECLARE_PER_CPU(unsigned long, stack_canary);
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 5e79ca694326..9c371e4a9fa6 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -296,6 +296,8 @@ HYPERVISOR_get_debugreg(int reg)
 static inline int
 HYPERVISOR_update_descriptor(u64 ma, u64 desc)
 {
+        if (sizeof(u64) == sizeof(long))
+                return _hypercall2(int, update_descriptor, ma, desc);
         return _hypercall4(int, update_descriptor, ma, ma>>32, desc, desc>>32);
 }