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-rw-r--r--arch/x86/include/asm/io.h1
-rw-r--r--arch/x86/include/asm/msr-index.h29
-rw-r--r--arch/x86/include/asm/pgalloc.h1
-rw-r--r--arch/x86/include/asm/syscalls.h2
-rw-r--r--arch/x86/include/asm/timex.h13
5 files changed, 35 insertions, 11 deletions
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 05cfed4485fa..1dbbdf4be9b4 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -99,7 +99,6 @@ extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size);
99 * A boot-time mapping is currently limited to at most 16 pages. 99 * A boot-time mapping is currently limited to at most 16 pages.
100 */ 100 */
101extern void early_ioremap_init(void); 101extern void early_ioremap_init(void);
102extern void early_ioremap_clear(void);
103extern void early_ioremap_reset(void); 102extern void early_ioremap_reset(void);
104extern void __iomem *early_ioremap(unsigned long offset, unsigned long size); 103extern void __iomem *early_ioremap(unsigned long offset, unsigned long size);
105extern void __iomem *early_memremap(unsigned long offset, unsigned long size); 104extern void __iomem *early_memremap(unsigned long offset, unsigned long size);
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index cb58643947b9..358acc59ae04 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -202,6 +202,35 @@
202#define MSR_IA32_THERM_STATUS 0x0000019c 202#define MSR_IA32_THERM_STATUS 0x0000019c
203#define MSR_IA32_MISC_ENABLE 0x000001a0 203#define MSR_IA32_MISC_ENABLE 0x000001a0
204 204
205/* MISC_ENABLE bits: architectural */
206#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
207#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
208#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
209#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
210#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
211#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
212#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
213#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
214#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
215#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
216
217/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
218#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
219#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
220#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
221#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
222#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
223#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
224#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
225#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
226#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
227#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
228#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
229#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
230#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
231#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
232#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
233
205/* Intel Model 6 */ 234/* Intel Model 6 */
206#define MSR_P6_EVNTSEL0 0x00000186 235#define MSR_P6_EVNTSEL0 0x00000186
207#define MSR_P6_EVNTSEL1 0x00000187 236#define MSR_P6_EVNTSEL1 0x00000187
diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h
index cb7c151a8bff..dd14c54ac718 100644
--- a/arch/x86/include/asm/pgalloc.h
+++ b/arch/x86/include/asm/pgalloc.h
@@ -42,6 +42,7 @@ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
42 42
43static inline void pte_free(struct mm_struct *mm, struct page *pte) 43static inline void pte_free(struct mm_struct *mm, struct page *pte)
44{ 44{
45 pgtable_page_dtor(pte);
45 __free_page(pte); 46 __free_page(pte);
46} 47}
47 48
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h
index 9c6797c3e56c..c0b0bda754ee 100644
--- a/arch/x86/include/asm/syscalls.h
+++ b/arch/x86/include/asm/syscalls.h
@@ -40,7 +40,7 @@ asmlinkage int sys_sigaction(int, const struct old_sigaction __user *,
40 struct old_sigaction __user *); 40 struct old_sigaction __user *);
41asmlinkage int sys_sigaltstack(unsigned long); 41asmlinkage int sys_sigaltstack(unsigned long);
42asmlinkage unsigned long sys_sigreturn(unsigned long); 42asmlinkage unsigned long sys_sigreturn(unsigned long);
43asmlinkage int sys_rt_sigreturn(struct pt_regs); 43asmlinkage int sys_rt_sigreturn(unsigned long);
44 44
45/* kernel/ioport.c */ 45/* kernel/ioport.c */
46asmlinkage long sys_iopl(unsigned long); 46asmlinkage long sys_iopl(unsigned long);
diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h
index 1287dc1347d6..b5c9d45c981f 100644
--- a/arch/x86/include/asm/timex.h
+++ b/arch/x86/include/asm/timex.h
@@ -1,18 +1,13 @@
1/* x86 architecture timex specifications */
2#ifndef _ASM_X86_TIMEX_H 1#ifndef _ASM_X86_TIMEX_H
3#define _ASM_X86_TIMEX_H 2#define _ASM_X86_TIMEX_H
4 3
5#include <asm/processor.h> 4#include <asm/processor.h>
6#include <asm/tsc.h> 5#include <asm/tsc.h>
7 6
8#ifdef CONFIG_X86_ELAN 7/* The PIT ticks at this frequency (in HZ): */
9# define PIT_TICK_RATE 1189200 /* AMD Elan has different frequency! */ 8#define PIT_TICK_RATE 1193182
10#elif defined(CONFIG_X86_RDC321X) 9
11# define PIT_TICK_RATE 1041667 /* Underlying HZ for R8610 */ 10#define CLOCK_TICK_RATE PIT_TICK_RATE
12#else
13# define PIT_TICK_RATE 1193182 /* Underlying HZ */
14#endif
15#define CLOCK_TICK_RATE PIT_TICK_RATE
16 11
17#define ARCH_HAS_READ_CURRENT_TIMER 12#define ARCH_HAS_READ_CURRENT_TIMER
18 13