diff options
Diffstat (limited to 'arch/x86/include/asm/uv/uv_bau.h')
-rw-r--r-- | arch/x86/include/asm/uv/uv_bau.h | 59 |
1 files changed, 34 insertions, 25 deletions
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h index a291c40efd43..37d369859c8e 100644 --- a/arch/x86/include/asm/uv/uv_bau.h +++ b/arch/x86/include/asm/uv/uv_bau.h | |||
@@ -67,7 +67,7 @@ | |||
67 | * we're using 655us, similar to UV1: 65 units of 10us | 67 | * we're using 655us, similar to UV1: 65 units of 10us |
68 | */ | 68 | */ |
69 | #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) | 69 | #define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) |
70 | #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL) | 70 | #define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL) |
71 | 71 | ||
72 | #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ | 72 | #define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ |
73 | UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ | 73 | UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ |
@@ -106,12 +106,20 @@ | |||
106 | #define DS_SOURCE_TIMEOUT 3 | 106 | #define DS_SOURCE_TIMEOUT 3 |
107 | /* | 107 | /* |
108 | * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 | 108 | * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 |
109 | * values 1 and 5 will not occur | 109 | * values 1 and 3 will not occur |
110 | * Decoded meaning ERROR BUSY AUX ERR | ||
111 | * ------------------------------- ---- ----- ------- | ||
112 | * IDLE 0 0 0 | ||
113 | * BUSY (active) 0 1 0 | ||
114 | * SW Ack Timeout (destination) 1 0 0 | ||
115 | * SW Ack INTD rejected (strong NACK) 1 0 1 | ||
116 | * Source Side Time Out Detected 1 1 0 | ||
117 | * Destination Side PUT Failed 1 1 1 | ||
110 | */ | 118 | */ |
111 | #define UV2H_DESC_IDLE 0 | 119 | #define UV2H_DESC_IDLE 0 |
112 | #define UV2H_DESC_DEST_TIMEOUT 2 | 120 | #define UV2H_DESC_BUSY 2 |
113 | #define UV2H_DESC_DEST_STRONG_NACK 3 | 121 | #define UV2H_DESC_DEST_TIMEOUT 4 |
114 | #define UV2H_DESC_BUSY 4 | 122 | #define UV2H_DESC_DEST_STRONG_NACK 5 |
115 | #define UV2H_DESC_SOURCE_TIMEOUT 6 | 123 | #define UV2H_DESC_SOURCE_TIMEOUT 6 |
116 | #define UV2H_DESC_DEST_PUT_ERR 7 | 124 | #define UV2H_DESC_DEST_PUT_ERR 7 |
117 | 125 | ||
@@ -183,7 +191,7 @@ | |||
183 | * 'base_dest_nasid' field of the header corresponds to the | 191 | * 'base_dest_nasid' field of the header corresponds to the |
184 | * destination nodeID associated with that specified bit. | 192 | * destination nodeID associated with that specified bit. |
185 | */ | 193 | */ |
186 | struct bau_targ_hubmask { | 194 | struct pnmask { |
187 | unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; | 195 | unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)]; |
188 | }; | 196 | }; |
189 | 197 | ||
@@ -314,7 +322,7 @@ struct bau_msg_header { | |||
314 | * Should be 64 bytes | 322 | * Should be 64 bytes |
315 | */ | 323 | */ |
316 | struct bau_desc { | 324 | struct bau_desc { |
317 | struct bau_targ_hubmask distribution; | 325 | struct pnmask distribution; |
318 | /* | 326 | /* |
319 | * message template, consisting of header and payload: | 327 | * message template, consisting of header and payload: |
320 | */ | 328 | */ |
@@ -488,6 +496,7 @@ struct bau_control { | |||
488 | struct bau_control *uvhub_master; | 496 | struct bau_control *uvhub_master; |
489 | struct bau_control *socket_master; | 497 | struct bau_control *socket_master; |
490 | struct ptc_stats *statp; | 498 | struct ptc_stats *statp; |
499 | cpumask_t *cpumask; | ||
491 | unsigned long timeout_interval; | 500 | unsigned long timeout_interval; |
492 | unsigned long set_bau_on_time; | 501 | unsigned long set_bau_on_time; |
493 | atomic_t active_descriptor_count; | 502 | atomic_t active_descriptor_count; |
@@ -526,90 +535,90 @@ struct bau_control { | |||
526 | struct hub_and_pnode *thp; | 535 | struct hub_and_pnode *thp; |
527 | }; | 536 | }; |
528 | 537 | ||
529 | static unsigned long read_mmr_uv2_status(void) | 538 | static inline unsigned long read_mmr_uv2_status(void) |
530 | { | 539 | { |
531 | return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2); | 540 | return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2); |
532 | } | 541 | } |
533 | 542 | ||
534 | static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) | 543 | static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image) |
535 | { | 544 | { |
536 | write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); | 545 | write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image); |
537 | } | 546 | } |
538 | 547 | ||
539 | static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) | 548 | static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image) |
540 | { | 549 | { |
541 | write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); | 550 | write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image); |
542 | } | 551 | } |
543 | 552 | ||
544 | static void write_mmr_activation(unsigned long index) | 553 | static inline void write_mmr_activation(unsigned long index) |
545 | { | 554 | { |
546 | write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); | 555 | write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index); |
547 | } | 556 | } |
548 | 557 | ||
549 | static void write_gmmr_activation(int pnode, unsigned long mmr_image) | 558 | static inline void write_gmmr_activation(int pnode, unsigned long mmr_image) |
550 | { | 559 | { |
551 | write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); | 560 | write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image); |
552 | } | 561 | } |
553 | 562 | ||
554 | static void write_mmr_payload_first(int pnode, unsigned long mmr_image) | 563 | static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image) |
555 | { | 564 | { |
556 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); | 565 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image); |
557 | } | 566 | } |
558 | 567 | ||
559 | static void write_mmr_payload_tail(int pnode, unsigned long mmr_image) | 568 | static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image) |
560 | { | 569 | { |
561 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); | 570 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image); |
562 | } | 571 | } |
563 | 572 | ||
564 | static void write_mmr_payload_last(int pnode, unsigned long mmr_image) | 573 | static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image) |
565 | { | 574 | { |
566 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); | 575 | write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image); |
567 | } | 576 | } |
568 | 577 | ||
569 | static void write_mmr_misc_control(int pnode, unsigned long mmr_image) | 578 | static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image) |
570 | { | 579 | { |
571 | write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); | 580 | write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image); |
572 | } | 581 | } |
573 | 582 | ||
574 | static unsigned long read_mmr_misc_control(int pnode) | 583 | static inline unsigned long read_mmr_misc_control(int pnode) |
575 | { | 584 | { |
576 | return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); | 585 | return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL); |
577 | } | 586 | } |
578 | 587 | ||
579 | static void write_mmr_sw_ack(unsigned long mr) | 588 | static inline void write_mmr_sw_ack(unsigned long mr) |
580 | { | 589 | { |
581 | uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); | 590 | uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr); |
582 | } | 591 | } |
583 | 592 | ||
584 | static unsigned long read_mmr_sw_ack(void) | 593 | static inline unsigned long read_mmr_sw_ack(void) |
585 | { | 594 | { |
586 | return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); | 595 | return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); |
587 | } | 596 | } |
588 | 597 | ||
589 | static unsigned long read_gmmr_sw_ack(int pnode) | 598 | static inline unsigned long read_gmmr_sw_ack(int pnode) |
590 | { | 599 | { |
591 | return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); | 600 | return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE); |
592 | } | 601 | } |
593 | 602 | ||
594 | static void write_mmr_data_config(int pnode, unsigned long mr) | 603 | static inline void write_mmr_data_config(int pnode, unsigned long mr) |
595 | { | 604 | { |
596 | uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); | 605 | uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr); |
597 | } | 606 | } |
598 | 607 | ||
599 | static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp) | 608 | static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp) |
600 | { | 609 | { |
601 | return constant_test_bit(uvhub, &dstp->bits[0]); | 610 | return constant_test_bit(uvhub, &dstp->bits[0]); |
602 | } | 611 | } |
603 | static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp) | 612 | static inline void bau_uvhub_set(int pnode, struct pnmask *dstp) |
604 | { | 613 | { |
605 | __set_bit(pnode, &dstp->bits[0]); | 614 | __set_bit(pnode, &dstp->bits[0]); |
606 | } | 615 | } |
607 | static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp, | 616 | static inline void bau_uvhubs_clear(struct pnmask *dstp, |
608 | int nbits) | 617 | int nbits) |
609 | { | 618 | { |
610 | bitmap_zero(&dstp->bits[0], nbits); | 619 | bitmap_zero(&dstp->bits[0], nbits); |
611 | } | 620 | } |
612 | static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp) | 621 | static inline int bau_uvhub_weight(struct pnmask *dstp) |
613 | { | 622 | { |
614 | return bitmap_weight((unsigned long *)&dstp->bits[0], | 623 | return bitmap_weight((unsigned long *)&dstp->bits[0], |
615 | UV_DISTRIBUTION_SIZE); | 624 | UV_DISTRIBUTION_SIZE); |