1 files changed, 12 insertions, 12 deletions

diff --git a/arch/x86/include/asm/sync_bitops.h b/arch/x86/include/asm/sync_bitops.h
index 9d09b4073b60..05af3b31d522 100644
--- a/arch/x86/include/asm/sync_bitops.h
+++ b/arch/x86/include/asm/sync_bitops.h
@@ -26,9 +26,9 @@
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
-static inline void sync_set_bit(int nr, volatile unsigned long *addr)
+static inline void sync_set_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("lock; btsl %1,%0"
+        asm volatile("lock; bts %1,%0"
                      : "+m" (ADDR)
                      : "Ir" (nr)
                      : "memory");
@@ -44,9 +44,9 @@ static inline void sync_set_bit(int nr, volatile unsigned long *addr)
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
-static inline void sync_clear_bit(int nr, volatile unsigned long *addr)
+static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("lock; btrl %1,%0"
+        asm volatile("lock; btr %1,%0"
                      : "+m" (ADDR)
                      : "Ir" (nr)
                      : "memory");
@@ -61,9 +61,9 @@ static inline void sync_clear_bit(int nr, volatile unsigned long *addr)
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
-static inline void sync_change_bit(int nr, volatile unsigned long *addr)
+static inline void sync_change_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("lock; btcl %1,%0"
+        asm volatile("lock; btc %1,%0"
                      : "+m" (ADDR)
                      : "Ir" (nr)
                      : "memory");
@@ -77,11 +77,11 @@ static inline void sync_change_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int sync_test_and_set_bit(int nr, volatile unsigned long *addr)
+static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
 {
         int oldbit;
 
-        asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0"
+        asm volatile("lock; bts %2,%1\n\tsbbl %0,%0"
                      : "=r" (oldbit), "+m" (ADDR)
                      : "Ir" (nr) : "memory");
         return oldbit;
@@ -95,11 +95,11 @@ static inline int sync_test_and_set_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int sync_test_and_clear_bit(int nr, volatile unsigned long *addr)
+static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
         int oldbit;
 
-        asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0"
+        asm volatile("lock; btr %2,%1\n\tsbbl %0,%0"
                      : "=r" (oldbit), "+m" (ADDR)
                      : "Ir" (nr) : "memory");
         return oldbit;
@@ -113,11 +113,11 @@ static inline int sync_test_and_clear_bit(int nr, volatile unsigned long *addr)
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
-static inline int sync_test_and_change_bit(int nr, volatile unsigned long *addr)
+static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr)
 {
         int oldbit;
 
-        asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0"
+        asm volatile("lock; btc %2,%1\n\tsbbl %0,%0"
                      : "=r" (oldbit), "+m" (ADDR)
                      : "Ir" (nr) : "memory");
         return oldbit;