1 files changed, 10 insertions, 5 deletions

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4604e6a54d36..bc473acfa7f9 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -71,11 +71,14 @@
 #define MSR_IA32_LASTINTTOIP            0x000001de
 
 /* DEBUGCTLMSR bits (others vary by model): */
-#define _DEBUGCTLMSR_LBR        0 /* last branch recording */
-#define _DEBUGCTLMSR_BTF        1 /* single-step on branches */
-
-#define DEBUGCTLMSR_LBR         (1UL << _DEBUGCTLMSR_LBR)
-#define DEBUGCTLMSR_BTF         (1UL << _DEBUGCTLMSR_BTF)
+#define DEBUGCTLMSR_LBR                 (1UL <<  0) /* last branch recording */
+#define DEBUGCTLMSR_BTF                 (1UL <<  1) /* single-step on branches */
+#define DEBUGCTLMSR_TR                  (1UL <<  6)
+#define DEBUGCTLMSR_BTS                 (1UL <<  7)
+#define DEBUGCTLMSR_BTINT               (1UL <<  8)
+#define DEBUGCTLMSR_BTS_OFF_OS          (1UL <<  9)
+#define DEBUGCTLMSR_BTS_OFF_USR         (1UL << 10)
+#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1UL << 11)
 
 #define MSR_IA32_MC0_CTL                0x00000400
 #define MSR_IA32_MC0_STATUS             0x00000401
@@ -359,6 +362,8 @@
 #define MSR_P4_U2L_ESCR0                0x000003b0
 #define MSR_P4_U2L_ESCR1                0x000003b1
 
+#define MSR_P4_PEBS_MATRIX_VERT         0x000003f2
+
 /* Intel Core-based CPU performance counters */
 #define MSR_CORE_PERF_FIXED_CTR0        0x00000309
 #define MSR_CORE_PERF_FIXED_CTR1        0x0000030a