diff options
Diffstat (limited to 'arch/x86/include/asm/cpufeature.h')
-rw-r--r-- | arch/x86/include/asm/cpufeature.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index cfdf8c2c5c31..ea408dcba513 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h | |||
@@ -80,7 +80,6 @@ | |||
80 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ | 80 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ |
81 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ | 81 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ |
82 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 82 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
83 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ | ||
84 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 83 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
85 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 84 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
86 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ | 85 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ |
@@ -92,6 +91,8 @@ | |||
92 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ | 91 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
93 | #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ | 92 | #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ |
94 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ | 93 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
94 | #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ | ||
95 | #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ | ||
95 | 96 | ||
96 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 97 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
97 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ | 98 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
@@ -117,6 +118,7 @@ | |||
117 | #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | 118 | #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
118 | #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ | 119 | #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ |
119 | #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ | 120 | #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ |
121 | #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ | ||
120 | 122 | ||
121 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | 123 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
122 | #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ | 124 | #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ |
@@ -237,6 +239,7 @@ extern const char * const x86_power_flags[32]; | |||
237 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) | 239 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
238 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) | 240 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
239 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) | 241 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
242 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) | ||
240 | 243 | ||
241 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) | 244 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) |
242 | # define cpu_has_invlpg 1 | 245 | # define cpu_has_invlpg 1 |