1 files changed, 4 insertions, 3 deletions

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index bb83b1c397aa..19af42138f78 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -22,7 +22,7 @@
 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
 #define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers */
 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
-#define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
+#define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Exception */
 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
 #define X86_FEATURE_APIC        (0*32+ 9) /* Onboard APIC */
 #define X86_FEATURE_SEP         (0*32+11) /* SYSENTER/SYSEXIT */
@@ -94,6 +94,7 @@
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
+#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
@@ -192,11 +193,11 @@ extern const char * const x86_power_flags[32];
 #define clear_cpu_cap(c, bit)   clear_bit(bit, (unsigned long *)((c)->x86_capability))
 #define setup_clear_cpu_cap(bit) do { \
         clear_cpu_cap(&boot_cpu_data, bit);     \
-        set_bit(bit, (unsigned long *)cleared_cpu_caps); \
+        set_bit(bit, (unsigned long *)cpu_caps_cleared); \
 } while (0)
 #define setup_force_cpu_cap(bit) do { \
         set_cpu_cap(&boot_cpu_data, bit);       \
-        clear_bit(bit, (unsigned long *)cleared_cpu_caps);      \
+        set_bit(bit, (unsigned long *)cpu_caps_set);    \
 } while (0)
 
 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)