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Diffstat (limited to 'arch/x86/include/asm/apic.h')
-rw-r--r--arch/x86/include/asm/apic.h37
1 files changed, 26 insertions, 11 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 4ef949c1972e..df8a300dfe6c 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -75,7 +75,7 @@ static inline void default_inquire_remote_apic(int apicid)
75#define setup_secondary_clock setup_secondary_APIC_clock 75#define setup_secondary_clock setup_secondary_APIC_clock
76#endif 76#endif
77 77
78#ifdef CONFIG_X86_VSMP 78#ifdef CONFIG_X86_64
79extern int is_vsmp_box(void); 79extern int is_vsmp_box(void);
80#else 80#else
81static inline int is_vsmp_box(void) 81static inline int is_vsmp_box(void)
@@ -108,6 +108,16 @@ extern void native_apic_icr_write(u32 low, u32 id);
108extern u64 native_apic_icr_read(void); 108extern u64 native_apic_icr_read(void);
109 109
110#ifdef CONFIG_X86_X2APIC 110#ifdef CONFIG_X86_X2APIC
111/*
112 * Make previous memory operations globally visible before
113 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
114 * mfence for this.
115 */
116static inline void x2apic_wrmsr_fence(void)
117{
118 asm volatile("mfence" : : : "memory");
119}
120
111static inline void native_apic_msr_write(u32 reg, u32 v) 121static inline void native_apic_msr_write(u32 reg, u32 v)
112{ 122{
113 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 123 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
@@ -184,6 +194,9 @@ static inline int x2apic_enabled(void)
184{ 194{
185 return 0; 195 return 0;
186} 196}
197
198#define x2apic 0
199
187#endif 200#endif
188 201
189extern int get_physical_broadcast(void); 202extern int get_physical_broadcast(void);
@@ -379,6 +392,7 @@ static inline u32 safe_apic_wait_icr_idle(void)
379 392
380static inline void ack_APIC_irq(void) 393static inline void ack_APIC_irq(void)
381{ 394{
395#ifdef CONFIG_X86_LOCAL_APIC
382 /* 396 /*
383 * ack_APIC_irq() actually gets compiled as a single instruction 397 * ack_APIC_irq() actually gets compiled as a single instruction
384 * ... yummie. 398 * ... yummie.
@@ -386,6 +400,7 @@ static inline void ack_APIC_irq(void)
386 400
387 /* Docs say use 0 for future compatibility */ 401 /* Docs say use 0 for future compatibility */
388 apic_write(APIC_EOI, 0); 402 apic_write(APIC_EOI, 0);
403#endif
389} 404}
390 405
391static inline unsigned default_get_apic_id(unsigned long x) 406static inline unsigned default_get_apic_id(unsigned long x)
@@ -474,10 +489,19 @@ static inline int default_apic_id_registered(void)
474 return physid_isset(read_apic_id(), phys_cpu_present_map); 489 return physid_isset(read_apic_id(), phys_cpu_present_map);
475} 490}
476 491
492static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
493{
494 return cpuid_apic >> index_msb;
495}
496
497extern int default_apicid_to_node(int logical_apicid);
498
499#endif
500
477static inline unsigned int 501static inline unsigned int
478default_cpu_mask_to_apicid(const struct cpumask *cpumask) 502default_cpu_mask_to_apicid(const struct cpumask *cpumask)
479{ 503{
480 return cpumask_bits(cpumask)[0]; 504 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
481} 505}
482 506
483static inline unsigned int 507static inline unsigned int
@@ -491,15 +515,6 @@ default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
491 return (unsigned int)(mask1 & mask2 & mask3); 515 return (unsigned int)(mask1 & mask2 & mask3);
492} 516}
493 517
494static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
495{
496 return cpuid_apic >> index_msb;
497}
498
499extern int default_apicid_to_node(int logical_apicid);
500
501#endif
502
503static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) 518static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
504{ 519{
505 return physid_isset(apicid, bitmap); 520 return physid_isset(apicid, bitmap);