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-rw-r--r--arch/tile/mm/init.c1082
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diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
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1/*
2 * Copyright (C) 1995 Linus Torvalds
3 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/module.h>
17#include <linux/signal.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/string.h>
22#include <linux/types.h>
23#include <linux/ptrace.h>
24#include <linux/mman.h>
25#include <linux/mm.h>
26#include <linux/hugetlb.h>
27#include <linux/swap.h>
28#include <linux/smp.h>
29#include <linux/init.h>
30#include <linux/highmem.h>
31#include <linux/pagemap.h>
32#include <linux/poison.h>
33#include <linux/bootmem.h>
34#include <linux/slab.h>
35#include <linux/proc_fs.h>
36#include <linux/efi.h>
37#include <linux/memory_hotplug.h>
38#include <linux/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/processor.h>
41#include <asm/system.h>
42#include <asm/pgtable.h>
43#include <asm/pgalloc.h>
44#include <asm/dma.h>
45#include <asm/fixmap.h>
46#include <asm/tlb.h>
47#include <asm/tlbflush.h>
48#include <asm/sections.h>
49#include <asm/setup.h>
50#include <asm/homecache.h>
51#include <hv/hypervisor.h>
52#include <arch/chip.h>
53
54#include "migrate.h"
55
56/*
57 * We could set FORCE_MAX_ZONEORDER to "(HPAGE_SHIFT - PAGE_SHIFT + 1)"
58 * in the Tile Kconfig, but this generates configure warnings.
59 * Do it here and force people to get it right to compile this file.
60 * The problem is that with 4KB small pages and 16MB huge pages,
61 * the default value doesn't allow us to group enough small pages
62 * together to make up a huge page.
63 */
64#if CONFIG_FORCE_MAX_ZONEORDER < HPAGE_SHIFT - PAGE_SHIFT + 1
65# error "Change FORCE_MAX_ZONEORDER in arch/tile/Kconfig to match page size"
66#endif
67
68#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
69
70unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
71
72DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
73
74/* Create an L2 page table */
75static pte_t * __init alloc_pte(void)
76{
77 return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
78}
79
80/*
81 * L2 page tables per controller. We allocate these all at once from
82 * the bootmem allocator and store them here. This saves on kernel L2
83 * page table memory, compared to allocating a full 64K page per L2
84 * page table, and also means that in cases where we use huge pages,
85 * we are guaranteed to later be able to shatter those huge pages and
86 * switch to using these page tables instead, without requiring
87 * further allocation. Each l2_ptes[] entry points to the first page
88 * table for the first hugepage-size piece of memory on the
89 * controller; other page tables are just indexed directly, i.e. the
90 * L2 page tables are contiguous in memory for each controller.
91 */
92static pte_t *l2_ptes[MAX_NUMNODES];
93static int num_l2_ptes[MAX_NUMNODES];
94
95static void init_prealloc_ptes(int node, int pages)
96{
97 BUG_ON(pages & (HV_L2_ENTRIES-1));
98 if (pages) {
99 num_l2_ptes[node] = pages;
100 l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t),
101 HV_PAGE_TABLE_ALIGN, 0);
102 }
103}
104
105pte_t *get_prealloc_pte(unsigned long pfn)
106{
107 int node = pfn_to_nid(pfn);
108 pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT));
109 BUG_ON(node >= MAX_NUMNODES);
110 BUG_ON(pfn >= num_l2_ptes[node]);
111 return &l2_ptes[node][pfn];
112}
113
114/*
115 * What caching do we expect pages from the heap to have when
116 * they are allocated during bootup? (Once we've installed the
117 * "real" swapper_pg_dir.)
118 */
119static int initial_heap_home(void)
120{
121#if CHIP_HAS_CBOX_HOME_MAP()
122 if (hash_default)
123 return PAGE_HOME_HASH;
124#endif
125 return smp_processor_id();
126}
127
128/*
129 * Place a pointer to an L2 page table in a middle page
130 * directory entry.
131 */
132static void __init assign_pte(pmd_t *pmd, pte_t *page_table)
133{
134 phys_addr_t pa = __pa(page_table);
135 unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN;
136 pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn);
137 BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0);
138 pteval = pte_set_home(pteval, initial_heap_home());
139 *(pte_t *)pmd = pteval;
140 if (page_table != (pte_t *)pmd_page_vaddr(*pmd))
141 BUG();
142}
143
144#ifdef __tilegx__
145
146#if HV_L1_SIZE != HV_L2_SIZE
147# error Rework assumption that L1 and L2 page tables are same size.
148#endif
149
150/* Since pmd_t arrays and pte_t arrays are the same size, just use casts. */
151static inline pmd_t *alloc_pmd(void)
152{
153 return (pmd_t *)alloc_pte();
154}
155
156static inline void assign_pmd(pud_t *pud, pmd_t *pmd)
157{
158 assign_pte((pmd_t *)pud, (pte_t *)pmd);
159}
160
161#endif /* __tilegx__ */
162
163/* Replace the given pmd with a full PTE table. */
164void __init shatter_pmd(pmd_t *pmd)
165{
166 pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd));
167 assign_pte(pmd, pte);
168}
169
170#ifdef CONFIG_HIGHMEM
171/*
172 * This function initializes a certain range of kernel virtual memory
173 * with new bootmem page tables, everywhere page tables are missing in
174 * the given range.
175 */
176
177/*
178 * NOTE: The pagetables are allocated contiguous on the physical space
179 * so we can cache the place of the first one and move around without
180 * checking the pgd every time.
181 */
182static void __init page_table_range_init(unsigned long start,
183 unsigned long end, pgd_t *pgd_base)
184{
185 pgd_t *pgd;
186 int pgd_idx;
187 unsigned long vaddr;
188
189 vaddr = start;
190 pgd_idx = pgd_index(vaddr);
191 pgd = pgd_base + pgd_idx;
192
193 for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
194 pmd_t *pmd = pmd_offset(pud_offset(pgd, vaddr), vaddr);
195 if (pmd_none(*pmd))
196 assign_pte(pmd, alloc_pte());
197 vaddr += PMD_SIZE;
198 }
199}
200#endif /* CONFIG_HIGHMEM */
201
202
203#if CHIP_HAS_CBOX_HOME_MAP()
204
205static int __initdata ktext_hash = 1; /* .text pages */
206static int __initdata kdata_hash = 1; /* .data and .bss pages */
207int __write_once hash_default = 1; /* kernel allocator pages */
208EXPORT_SYMBOL(hash_default);
209int __write_once kstack_hash = 1; /* if no homecaching, use h4h */
210#endif /* CHIP_HAS_CBOX_HOME_MAP */
211
212/*
213 * CPUs to use to for striping the pages of kernel data. If hash-for-home
214 * is available, this is only relevant if kcache_hash sets up the
215 * .data and .bss to be page-homed, and we don't want the default mode
216 * of using the full set of kernel cpus for the striping.
217 */
218static __initdata struct cpumask kdata_mask;
219static __initdata int kdata_arg_seen;
220
221int __write_once kdata_huge; /* if no homecaching, small pages */
222
223
224/* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
225static pgprot_t __init construct_pgprot(pgprot_t prot, int home)
226{
227 prot = pte_set_home(prot, home);
228#if CHIP_HAS_CBOX_HOME_MAP()
229 if (home == PAGE_HOME_IMMUTABLE) {
230 if (ktext_hash)
231 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3);
232 else
233 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3);
234 }
235#endif
236 return prot;
237}
238
239/*
240 * For a given kernel data VA, how should it be cached?
241 * We return the complete pgprot_t with caching bits set.
242 */
243static pgprot_t __init init_pgprot(ulong address)
244{
245 int cpu;
246 unsigned long page;
247 enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
248
249#if CHIP_HAS_CBOX_HOME_MAP()
250 /* For kdata=huge, everything is just hash-for-home. */
251 if (kdata_huge)
252 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
253#endif
254
255 /* We map the aliased pages of permanent text inaccessible. */
256 if (address < (ulong) _sinittext - CODE_DELTA)
257 return PAGE_NONE;
258
259 /*
260 * We map read-only data non-coherent for performance. We could
261 * use neighborhood caching on TILE64, but it's not clear it's a win.
262 */
263 if ((address >= (ulong) __start_rodata &&
264 address < (ulong) __end_rodata) ||
265 address == (ulong) empty_zero_page) {
266 return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE);
267 }
268
269 /* As a performance optimization, keep the boot init stack here. */
270 if (address >= (ulong)&init_thread_union &&
271 address < (ulong)&init_thread_union + THREAD_SIZE)
272 return construct_pgprot(PAGE_KERNEL, smp_processor_id());
273
274#ifndef __tilegx__
275#if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
276 /* Force the atomic_locks[] array page to be hash-for-home. */
277 if (address == (ulong) atomic_locks)
278 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
279#endif
280#endif
281
282 /*
283 * Everything else that isn't data or bss is heap, so mark it
284 * with the initial heap home (hash-for-home, or this cpu). This
285 * includes any addresses after the loaded image; any address before
286 * _einittext (since we already captured the case of text before
287 * _sinittext); and any init-data pages.
288 *
289 * All the LOWMEM pages that we mark this way will get their
290 * struct page homecache properly marked later, in set_page_homes().
291 * The HIGHMEM pages we leave with a default zero for their
292 * homes, but with a zero free_time we don't have to actually
293 * do a flush action the first time we use them, either.
294 */
295 if (address >= (ulong) _end || address < (ulong) _sdata ||
296 (address >= (ulong) _sinitdata &&
297 address < (ulong) _einitdata))
298 return construct_pgprot(PAGE_KERNEL, initial_heap_home());
299
300#if CHIP_HAS_CBOX_HOME_MAP()
301 /* Use hash-for-home if requested for data/bss. */
302 if (kdata_hash)
303 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
304#endif
305
306 /*
307 * Otherwise we just hand out consecutive cpus. To avoid
308 * requiring this function to hold state, we just walk forward from
309 * _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
310 * the requested address, while walking cpu home around kdata_mask.
311 * This is typically no more than a dozen or so iterations.
312 */
313 BUG_ON(_einitdata != __bss_start);
314 for (page = (ulong)_sdata, cpu = NR_CPUS; ; ) {
315 cpu = cpumask_next(cpu, &kdata_mask);
316 if (cpu == NR_CPUS)
317 cpu = cpumask_first(&kdata_mask);
318 if (page >= address)
319 break;
320 page += PAGE_SIZE;
321 if (page == (ulong)__start_rodata)
322 page = (ulong)__end_rodata;
323 if (page == (ulong)&init_thread_union)
324 page += THREAD_SIZE;
325 if (page == (ulong)_sinitdata)
326 page = (ulong)_einitdata;
327 if (page == (ulong)empty_zero_page)
328 page += PAGE_SIZE;
329#ifndef __tilegx__
330#if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
331 if (page == (ulong)atomic_locks)
332 page += PAGE_SIZE;
333#endif
334#endif
335
336 }
337 return construct_pgprot(PAGE_KERNEL, cpu);
338}
339
340/*
341 * This function sets up how we cache the kernel text. If we have
342 * hash-for-home support, normally that is used instead (see the
343 * kcache_hash boot flag for more information). But if we end up
344 * using a page-based caching technique, this option sets up the
345 * details of that. In addition, the "ktext=nocache" option may
346 * always be used to disable local caching of text pages, if desired.
347 */
348
349static int __initdata ktext_arg_seen;
350static int __initdata ktext_small;
351static int __initdata ktext_local;
352static int __initdata ktext_all;
353static int __initdata ktext_nondataplane;
354static int __initdata ktext_nocache;
355static struct cpumask __initdata ktext_mask;
356
357static int __init setup_ktext(char *str)
358{
359 if (str == NULL)
360 return -EINVAL;
361
362 /* If you have a leading "nocache", turn off ktext caching */
363 if (strncmp(str, "nocache", 7) == 0) {
364 ktext_nocache = 1;
365 printk("ktext: disabling local caching of kernel text\n");
366 str += 7;
367 if (*str == ',')
368 ++str;
369 if (*str == '\0')
370 return 0;
371 }
372
373 ktext_arg_seen = 1;
374
375 /* Default setting on Tile64: use a huge page */
376 if (strcmp(str, "huge") == 0)
377 printk("ktext: using one huge locally cached page\n");
378
379 /* Pay TLB cost but get no cache benefit: cache small pages locally */
380 else if (strcmp(str, "local") == 0) {
381 ktext_small = 1;
382 ktext_local = 1;
383 printk("ktext: using small pages with local caching\n");
384 }
385
386 /* Neighborhood cache ktext pages on all cpus. */
387 else if (strcmp(str, "all") == 0) {
388 ktext_small = 1;
389 ktext_all = 1;
390 printk("ktext: using maximal caching neighborhood\n");
391 }
392
393
394 /* Neighborhood ktext pages on specified mask */
395 else if (cpulist_parse(str, &ktext_mask) == 0) {
396 char buf[NR_CPUS * 5];
397 cpulist_scnprintf(buf, sizeof(buf), &ktext_mask);
398 if (cpumask_weight(&ktext_mask) > 1) {
399 ktext_small = 1;
400 printk("ktext: using caching neighborhood %s "
401 "with small pages\n", buf);
402 } else {
403 printk("ktext: caching on cpu %s with one huge page\n",
404 buf);
405 }
406 }
407
408 else if (*str)
409 return -EINVAL;
410
411 return 0;
412}
413
414early_param("ktext", setup_ktext);
415
416
417static inline pgprot_t ktext_set_nocache(pgprot_t prot)
418{
419 if (!ktext_nocache)
420 prot = hv_pte_set_nc(prot);
421#if CHIP_HAS_NC_AND_NOALLOC_BITS()
422 else
423 prot = hv_pte_set_no_alloc_l2(prot);
424#endif
425 return prot;
426}
427
428#ifndef __tilegx__
429static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
430{
431 return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
432}
433#else
434static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
435{
436 pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
437 if (pud_none(*pud))
438 assign_pmd(pud, alloc_pmd());
439 return pmd_offset(pud, va);
440}
441#endif
442
443/* Temporary page table we use for staging. */
444static pgd_t pgtables[PTRS_PER_PGD]
445 __attribute__((section(".init.page")));
446
447/*
448 * This maps the physical memory to kernel virtual address space, a total
449 * of max_low_pfn pages, by creating page tables starting from address
450 * PAGE_OFFSET.
451 *
452 * This routine transitions us from using a set of compiled-in large
453 * pages to using some more precise caching, including removing access
454 * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
455 * marking read-only data as locally cacheable, striping the remaining
456 * .data and .bss across all the available tiles, and removing access
457 * to pages above the top of RAM (thus ensuring a page fault from a bad
458 * virtual address rather than a hypervisor shoot down for accessing
459 * memory outside the assigned limits).
460 */
461static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
462{
463 unsigned long address, pfn;
464 pmd_t *pmd;
465 pte_t *pte;
466 int pte_ofs;
467 const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id());
468 struct cpumask kstripe_mask;
469 int rc, i;
470
471#if CHIP_HAS_CBOX_HOME_MAP()
472 if (ktext_arg_seen && ktext_hash) {
473 printk("warning: \"ktext\" boot argument ignored"
474 " if \"kcache_hash\" sets up text hash-for-home\n");
475 ktext_small = 0;
476 }
477
478 if (kdata_arg_seen && kdata_hash) {
479 printk("warning: \"kdata\" boot argument ignored"
480 " if \"kcache_hash\" sets up data hash-for-home\n");
481 }
482
483 if (kdata_huge && !hash_default) {
484 printk("warning: disabling \"kdata=huge\"; requires"
485 " kcache_hash=all or =allbutstack\n");
486 kdata_huge = 0;
487 }
488#endif
489
490 /*
491 * Set up a mask for cpus to use for kernel striping.
492 * This is normally all cpus, but minus dataplane cpus if any.
493 * If the dataplane covers the whole chip, we stripe over
494 * the whole chip too.
495 */
496 cpumask_copy(&kstripe_mask, cpu_possible_mask);
497 if (!kdata_arg_seen)
498 kdata_mask = kstripe_mask;
499
500 /* Allocate and fill in L2 page tables */
501 for (i = 0; i < MAX_NUMNODES; ++i) {
502#ifdef CONFIG_HIGHMEM
503 unsigned long end_pfn = node_lowmem_end_pfn[i];
504#else
505 unsigned long end_pfn = node_end_pfn[i];
506#endif
507 unsigned long end_huge_pfn = 0;
508
509 /* Pre-shatter the last huge page to allow per-cpu pages. */
510 if (kdata_huge)
511 end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT);
512
513 pfn = node_start_pfn[i];
514
515 /* Allocate enough memory to hold L2 page tables for node. */
516 init_prealloc_ptes(i, end_pfn - pfn);
517
518 address = (unsigned long) pfn_to_kaddr(pfn);
519 while (pfn < end_pfn) {
520 BUG_ON(address & (HPAGE_SIZE-1));
521 pmd = get_pmd(pgtables, address);
522 pte = get_prealloc_pte(pfn);
523 if (pfn < end_huge_pfn) {
524 pgprot_t prot = init_pgprot(address);
525 *(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot));
526 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
527 pfn++, pte_ofs++, address += PAGE_SIZE)
528 pte[pte_ofs] = pfn_pte(pfn, prot);
529 } else {
530 if (kdata_huge)
531 printk(KERN_DEBUG "pre-shattered huge"
532 " page at %#lx\n", address);
533 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
534 pfn++, pte_ofs++, address += PAGE_SIZE) {
535 pgprot_t prot = init_pgprot(address);
536 pte[pte_ofs] = pfn_pte(pfn, prot);
537 }
538 assign_pte(pmd, pte);
539 }
540 }
541 }
542
543 /*
544 * Set or check ktext_map now that we have cpu_possible_mask
545 * and kstripe_mask to work with.
546 */
547 if (ktext_all)
548 cpumask_copy(&ktext_mask, cpu_possible_mask);
549 else if (ktext_nondataplane)
550 ktext_mask = kstripe_mask;
551 else if (!cpumask_empty(&ktext_mask)) {
552 /* Sanity-check any mask that was requested */
553 struct cpumask bad;
554 cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask);
555 cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask);
556 if (!cpumask_empty(&bad)) {
557 char buf[NR_CPUS * 5];
558 cpulist_scnprintf(buf, sizeof(buf), &bad);
559 printk("ktext: not using unavailable cpus %s\n", buf);
560 }
561 if (cpumask_empty(&ktext_mask)) {
562 printk("ktext: no valid cpus; caching on %d.\n",
563 smp_processor_id());
564 cpumask_copy(&ktext_mask,
565 cpumask_of(smp_processor_id()));
566 }
567 }
568
569 address = MEM_SV_INTRPT;
570 pmd = get_pmd(pgtables, address);
571 if (ktext_small) {
572 /* Allocate an L2 PTE for the kernel text */
573 int cpu = 0;
574 pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC,
575 PAGE_HOME_IMMUTABLE);
576
577 if (ktext_local) {
578 if (ktext_nocache)
579 prot = hv_pte_set_mode(prot,
580 HV_PTE_MODE_UNCACHED);
581 else
582 prot = hv_pte_set_mode(prot,
583 HV_PTE_MODE_CACHE_NO_L3);
584 } else {
585 prot = hv_pte_set_mode(prot,
586 HV_PTE_MODE_CACHE_TILE_L3);
587 cpu = cpumask_first(&ktext_mask);
588
589 prot = ktext_set_nocache(prot);
590 }
591
592 BUG_ON(address != (unsigned long)_stext);
593 pfn = 0; /* code starts at PA 0 */
594 pte = alloc_pte();
595 for (pte_ofs = 0; address < (unsigned long)_einittext;
596 pfn++, pte_ofs++, address += PAGE_SIZE) {
597 if (!ktext_local) {
598 prot = set_remote_cache_cpu(prot, cpu);
599 cpu = cpumask_next(cpu, &ktext_mask);
600 if (cpu == NR_CPUS)
601 cpu = cpumask_first(&ktext_mask);
602 }
603 pte[pte_ofs] = pfn_pte(pfn, prot);
604 }
605 assign_pte(pmd, pte);
606 } else {
607 pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC);
608 pteval = pte_mkhuge(pteval);
609#if CHIP_HAS_CBOX_HOME_MAP()
610 if (ktext_hash) {
611 pteval = hv_pte_set_mode(pteval,
612 HV_PTE_MODE_CACHE_HASH_L3);
613 pteval = ktext_set_nocache(pteval);
614 } else
615#endif /* CHIP_HAS_CBOX_HOME_MAP() */
616 if (cpumask_weight(&ktext_mask) == 1) {
617 pteval = set_remote_cache_cpu(pteval,
618 cpumask_first(&ktext_mask));
619 pteval = hv_pte_set_mode(pteval,
620 HV_PTE_MODE_CACHE_TILE_L3);
621 pteval = ktext_set_nocache(pteval);
622 } else if (ktext_nocache)
623 pteval = hv_pte_set_mode(pteval,
624 HV_PTE_MODE_UNCACHED);
625 else
626 pteval = hv_pte_set_mode(pteval,
627 HV_PTE_MODE_CACHE_NO_L3);
628 *(pte_t *)pmd = pteval;
629 }
630
631 /* Set swapper_pgprot here so it is flushed to memory right away. */
632 swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir);
633
634 /*
635 * Since we may be changing the caching of the stack and page
636 * table itself, we invoke an assembly helper to do the
637 * following steps:
638 *
639 * - flush the cache so we start with an empty slate
640 * - install pgtables[] as the real page table
641 * - flush the TLB so the new page table takes effect
642 */
643 rc = flush_and_install_context(__pa(pgtables),
644 init_pgprot((unsigned long)pgtables),
645 __get_cpu_var(current_asid),
646 cpumask_bits(my_cpu_mask));
647 BUG_ON(rc != 0);
648
649 /* Copy the page table back to the normal swapper_pg_dir. */
650 memcpy(pgd_base, pgtables, sizeof(pgtables));
651 __install_page_table(pgd_base, __get_cpu_var(current_asid),
652 swapper_pgprot);
653}
654
655/*
656 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
657 * is valid. The argument is a physical page number.
658 *
659 * On Tile, the only valid things for which we can just hand out unchecked
660 * PTEs are the kernel code and data. Anything else might change its
661 * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
662 * Note that init_thread_union is released to heap soon after boot,
663 * so we include it in the init data.
664 *
665 * For TILE-Gx, we might want to consider allowing access to PA
666 * regions corresponding to PCI space, etc.
667 */
668int devmem_is_allowed(unsigned long pagenr)
669{
670 return pagenr < kaddr_to_pfn(_end) &&
671 !(pagenr >= kaddr_to_pfn(&init_thread_union) ||
672 pagenr < kaddr_to_pfn(_einitdata)) &&
673 !(pagenr >= kaddr_to_pfn(_sinittext) ||
674 pagenr <= kaddr_to_pfn(_einittext-1));
675}
676
677#ifdef CONFIG_HIGHMEM
678static void __init permanent_kmaps_init(pgd_t *pgd_base)
679{
680 pgd_t *pgd;
681 pud_t *pud;
682 pmd_t *pmd;
683 pte_t *pte;
684 unsigned long vaddr;
685
686 vaddr = PKMAP_BASE;
687 page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
688
689 pgd = swapper_pg_dir + pgd_index(vaddr);
690 pud = pud_offset(pgd, vaddr);
691 pmd = pmd_offset(pud, vaddr);
692 pte = pte_offset_kernel(pmd, vaddr);
693 pkmap_page_table = pte;
694}
695#endif /* CONFIG_HIGHMEM */
696
697
698static void __init init_free_pfn_range(unsigned long start, unsigned long end)
699{
700 unsigned long pfn;
701 struct page *page = pfn_to_page(start);
702
703 for (pfn = start; pfn < end; ) {
704 /* Optimize by freeing pages in large batches */
705 int order = __ffs(pfn);
706 int count, i;
707 struct page *p;
708
709 if (order >= MAX_ORDER)
710 order = MAX_ORDER-1;
711 count = 1 << order;
712 while (pfn + count > end) {
713 count >>= 1;
714 --order;
715 }
716 for (p = page, i = 0; i < count; ++i, ++p) {
717 __ClearPageReserved(p);
718 /*
719 * Hacky direct set to avoid unnecessary
720 * lock take/release for EVERY page here.
721 */
722 p->_count.counter = 0;
723 p->_mapcount.counter = -1;
724 }
725 init_page_count(page);
726 __free_pages(page, order);
727 totalram_pages += count;
728
729 page += count;
730 pfn += count;
731 }
732}
733
734static void __init set_non_bootmem_pages_init(void)
735{
736 struct zone *z;
737 for_each_zone(z) {
738 unsigned long start, end;
739 int nid = z->zone_pgdat->node_id;
740
741 start = z->zone_start_pfn;
742 if (start == 0)
743 continue; /* bootmem */
744 end = start + z->spanned_pages;
745 if (zone_idx(z) == ZONE_NORMAL) {
746 BUG_ON(start != node_start_pfn[nid]);
747 start = node_free_pfn[nid];
748 }
749#ifdef CONFIG_HIGHMEM
750 if (zone_idx(z) == ZONE_HIGHMEM)
751 totalhigh_pages += z->spanned_pages;
752#endif
753 if (kdata_huge) {
754 unsigned long percpu_pfn = node_percpu_pfn[nid];
755 if (start < percpu_pfn && end > percpu_pfn)
756 end = percpu_pfn;
757 }
758#ifdef CONFIG_PCI
759 if (start <= pci_reserve_start_pfn &&
760 end > pci_reserve_start_pfn) {
761 if (end > pci_reserve_end_pfn)
762 init_free_pfn_range(pci_reserve_end_pfn, end);
763 end = pci_reserve_start_pfn;
764 }
765#endif
766 init_free_pfn_range(start, end);
767 }
768}
769
770/*
771 * paging_init() sets up the page tables - note that all of lowmem is
772 * already mapped by head.S.
773 */
774void __init paging_init(void)
775{
776#ifdef CONFIG_HIGHMEM
777 unsigned long vaddr, end;
778#endif
779#ifdef __tilegx__
780 pud_t *pud;
781#endif
782 pgd_t *pgd_base = swapper_pg_dir;
783
784 kernel_physical_mapping_init(pgd_base);
785
786#ifdef CONFIG_HIGHMEM
787 /*
788 * Fixed mappings, only the page table structure has to be
789 * created - mappings will be set by set_fixmap():
790 */
791 vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
792 end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
793 page_table_range_init(vaddr, end, pgd_base);
794 permanent_kmaps_init(pgd_base);
795#endif
796
797#ifdef __tilegx__
798 /*
799 * Since GX allocates just one pmd_t array worth of vmalloc space,
800 * we go ahead and allocate it statically here, then share it
801 * globally. As a result we don't have to worry about any task
802 * changing init_mm once we get up and running, and there's no
803 * need for e.g. vmalloc_sync_all().
804 */
805 BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END));
806 pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START);
807 assign_pmd(pud, alloc_pmd());
808#endif
809}
810
811
812/*
813 * Walk the kernel page tables and derive the page_home() from
814 * the PTEs, so that set_pte() can properly validate the caching
815 * of all PTEs it sees.
816 */
817void __init set_page_homes(void)
818{
819}
820
821static void __init set_max_mapnr_init(void)
822{
823#ifdef CONFIG_FLATMEM
824 max_mapnr = max_low_pfn;
825#endif
826}
827
828void __init mem_init(void)
829{
830 int codesize, datasize, initsize;
831 int i;
832#ifndef __tilegx__
833 void *last;
834#endif
835
836#ifdef CONFIG_FLATMEM
837 if (!mem_map)
838 BUG();
839#endif
840
841#ifdef CONFIG_HIGHMEM
842 /* check that fixmap and pkmap do not overlap */
843 if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) {
844 printk(KERN_ERR "fixmap and kmap areas overlap"
845 " - this will crash\n");
846 printk(KERN_ERR "pkstart: %lxh pkend: %lxh fixstart %lxh\n",
847 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1),
848 FIXADDR_START);
849 BUG();
850 }
851#endif
852
853 set_max_mapnr_init();
854
855 /* this will put all bootmem onto the freelists */
856 totalram_pages += free_all_bootmem();
857
858 /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
859 set_non_bootmem_pages_init();
860
861 codesize = (unsigned long)&_etext - (unsigned long)&_text;
862 datasize = (unsigned long)&_end - (unsigned long)&_sdata;
863 initsize = (unsigned long)&_einittext - (unsigned long)&_sinittext;
864 initsize += (unsigned long)&_einitdata - (unsigned long)&_sinitdata;
865
866 printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
867 (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
868 num_physpages << (PAGE_SHIFT-10),
869 codesize >> 10,
870 datasize >> 10,
871 initsize >> 10,
872 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
873 );
874
875 /*
876 * In debug mode, dump some interesting memory mappings.
877 */
878#ifdef CONFIG_HIGHMEM
879 printk(KERN_DEBUG " KMAP %#lx - %#lx\n",
880 FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
881 printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
882 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
883#endif
884#ifdef CONFIG_HUGEVMAP
885 printk(KERN_DEBUG " HUGEMAP %#lx - %#lx\n",
886 HUGE_VMAP_BASE, HUGE_VMAP_END - 1);
887#endif
888 printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
889 _VMALLOC_START, _VMALLOC_END - 1);
890#ifdef __tilegx__
891 for (i = MAX_NUMNODES-1; i >= 0; --i) {
892 struct pglist_data *node = &node_data[i];
893 if (node->node_present_pages) {
894 unsigned long start = (unsigned long)
895 pfn_to_kaddr(node->node_start_pfn);
896 unsigned long end = start +
897 (node->node_present_pages << PAGE_SHIFT);
898 printk(KERN_DEBUG " MEM%d %#lx - %#lx\n",
899 i, start, end - 1);
900 }
901 }
902#else
903 last = high_memory;
904 for (i = MAX_NUMNODES-1; i >= 0; --i) {
905 if ((unsigned long)vbase_map[i] != -1UL) {
906 printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n",
907 i, (unsigned long) (vbase_map[i]),
908 (unsigned long) (last-1));
909 last = vbase_map[i];
910 }
911 }
912#endif
913
914#ifndef __tilegx__
915 /*
916 * Convert from using one lock for all atomic operations to
917 * one per cpu.
918 */
919 __init_atomic_per_cpu();
920#endif
921}
922
923/*
924 * this is for the non-NUMA, single node SMP system case.
925 * Specifically, in the case of x86, we will always add
926 * memory to the highmem for now.
927 */
928#ifndef CONFIG_NEED_MULTIPLE_NODES
929int arch_add_memory(u64 start, u64 size)
930{
931 struct pglist_data *pgdata = &contig_page_data;
932 struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1;
933 unsigned long start_pfn = start >> PAGE_SHIFT;
934 unsigned long nr_pages = size >> PAGE_SHIFT;
935
936 return __add_pages(zone, start_pfn, nr_pages);
937}
938
939int remove_memory(u64 start, u64 size)
940{
941 return -EINVAL;
942}
943#endif
944
945struct kmem_cache *pgd_cache;
946
947void __init pgtable_cache_init(void)
948{
949 pgd_cache = kmem_cache_create("pgd",
950 PTRS_PER_PGD*sizeof(pgd_t),
951 PTRS_PER_PGD*sizeof(pgd_t),
952 0,
953 NULL);
954 if (!pgd_cache)
955 panic("pgtable_cache_init(): Cannot create pgd cache");
956}
957
958#if !CHIP_HAS_COHERENT_LOCAL_CACHE()
959/*
960 * The __w1data area holds data that is only written during initialization,
961 * and is read-only and thus freely cacheable thereafter. Fix the page
962 * table entries that cover that region accordingly.
963 */
964static void mark_w1data_ro(void)
965{
966 /* Loop over page table entries */
967 unsigned long addr = (unsigned long)__w1data_begin;
968 BUG_ON((addr & (PAGE_SIZE-1)) != 0);
969 for (; addr <= (unsigned long)__w1data_end - 1; addr += PAGE_SIZE) {
970 unsigned long pfn = kaddr_to_pfn((void *)addr);
971 struct page *page = pfn_to_page(pfn);
972 pte_t *ptep = virt_to_pte(NULL, addr);
973 BUG_ON(pte_huge(*ptep)); /* not relevant for kdata_huge */
974 set_pte_at(&init_mm, addr, ptep, pfn_pte(pfn, PAGE_KERNEL_RO));
975 }
976}
977#endif
978
979#ifdef CONFIG_DEBUG_PAGEALLOC
980static long __write_once initfree;
981#else
982static long __write_once initfree = 1;
983#endif
984
985/* Select whether to free (1) or mark unusable (0) the __init pages. */
986static int __init set_initfree(char *str)
987{
988 strict_strtol(str, 0, &initfree);
989 printk("initfree: %s free init pages\n", initfree ? "will" : "won't");
990 return 1;
991}
992__setup("initfree=", set_initfree);
993
994static void free_init_pages(char *what, unsigned long begin, unsigned long end)
995{
996 unsigned long addr = (unsigned long) begin;
997
998 if (kdata_huge && !initfree) {
999 printk("Warning: ignoring initfree=0:"
1000 " incompatible with kdata=huge\n");
1001 initfree = 1;
1002 }
1003 end = (end + PAGE_SIZE - 1) & PAGE_MASK;
1004 local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin);
1005 for (addr = begin; addr < end; addr += PAGE_SIZE) {
1006 /*
1007 * Note we just reset the home here directly in the
1008 * page table. We know this is safe because our caller
1009 * just flushed the caches on all the other cpus,
1010 * and they won't be touching any of these pages.
1011 */
1012 int pfn = kaddr_to_pfn((void *)addr);
1013 struct page *page = pfn_to_page(pfn);
1014 pte_t *ptep = virt_to_pte(NULL, addr);
1015 if (!initfree) {
1016 /*
1017 * If debugging page accesses then do not free
1018 * this memory but mark them not present - any
1019 * buggy init-section access will create a
1020 * kernel page fault:
1021 */
1022 pte_clear(&init_mm, addr, ptep);
1023 continue;
1024 }
1025 __ClearPageReserved(page);
1026 init_page_count(page);
1027 if (pte_huge(*ptep))
1028 BUG_ON(!kdata_huge);
1029 else
1030 set_pte_at(&init_mm, addr, ptep,
1031 pfn_pte(pfn, PAGE_KERNEL));
1032 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1033 free_page(addr);
1034 totalram_pages++;
1035 }
1036 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
1037}
1038
1039void free_initmem(void)
1040{
1041 const unsigned long text_delta = MEM_SV_INTRPT - PAGE_OFFSET;
1042
1043 /*
1044 * Evict the dirty initdata on the boot cpu, evict the w1data
1045 * wherever it's homed, and evict all the init code everywhere.
1046 * We are guaranteed that no one will touch the init pages any
1047 * more, and although other cpus may be touching the w1data,
1048 * we only actually change the caching on tile64, which won't
1049 * be keeping local copies in the other tiles' caches anyway.
1050 */
1051 homecache_evict(&cpu_cacheable_map);
1052
1053 /* Free the data pages that we won't use again after init. */
1054 free_init_pages("unused kernel data",
1055 (unsigned long)_sinitdata,
1056 (unsigned long)_einitdata);
1057
1058 /*
1059 * Free the pages mapped from 0xc0000000 that correspond to code
1060 * pages from 0xfd000000 that we won't use again after init.
1061 */
1062 free_init_pages("unused kernel text",
1063 (unsigned long)_sinittext - text_delta,
1064 (unsigned long)_einittext - text_delta);
1065
1066#if !CHIP_HAS_COHERENT_LOCAL_CACHE()
1067 /*
1068 * Upgrade the .w1data section to globally cached.
1069 * We don't do this on tilepro, since the cache architecture
1070 * pretty much makes it irrelevant, and in any case we end
1071 * up having racing issues with other tiles that may touch
1072 * the data after we flush the cache but before we update
1073 * the PTEs and flush the TLBs, causing sharer shootdowns
1074 * later. Even though this is to clean data, it seems like
1075 * an unnecessary complication.
1076 */
1077 mark_w1data_ro();
1078#endif
1079
1080 /* Do a global TLB flush so everyone sees the changes. */
1081 flush_tlb_all();
1082}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 13:16:35 -0500