aboutsummaryrefslogtreecommitdiffstats
path: root/arch/tile/include/asm/irq.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/tile/include/asm/irq.h')
-rw-r--r--arch/tile/include/asm/irq.h87
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
new file mode 100644
index 000000000000..572fd3ef1d73
--- /dev/null
+++ b/arch/tile/include/asm/irq.h
@@ -0,0 +1,87 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_IRQ_H
16#define _ASM_TILE_IRQ_H
17
18#include <linux/hardirq.h>
19
20/* The hypervisor interface provides 32 IRQs. */
21#define NR_IRQS 32
22
23/* IRQ numbers used for linux IPIs. */
24#define IRQ_RESCHEDULE 1
25
26void ack_bad_irq(unsigned int irq);
27
28/*
29 * Different ways of handling interrupts. Tile interrupts are always
30 * per-cpu; there is no global interrupt controller to implement
31 * enable/disable. Most onboard devices can send their interrupts to
32 * many tiles at the same time, and Tile-specific drivers know how to
33 * deal with this.
34 *
35 * However, generic devices (usually PCIE based, sometimes GPIO)
36 * expect that interrupts will fire on a single core at a time and
37 * that the irq can be enabled or disabled from any core at any time.
38 * We implement this by directing such interrupts to a single core.
39 *
40 * One added wrinkle is that PCI interrupts can be either
41 * hardware-cleared (legacy interrupts) or software cleared (MSI).
42 * Other generic device systems (GPIO) are always software-cleared.
43 *
44 * The enums below are used by drivers for onboard devices, including
45 * the internals of PCI root complex and GPIO. They allow the driver
46 * to tell the generic irq code what kind of interrupt is mapped to a
47 * particular IRQ number.
48 */
49enum {
50 /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
51 TILE_IRQ_PERCPU,
52 /* global interrupt, hardware responsible for clearing. */
53 TILE_IRQ_HW_CLEAR,
54 /* global interrupt, software responsible for clearing. */
55 TILE_IRQ_SW_CLEAR,
56};
57
58
59/*
60 * Paravirtualized drivers should call this when they dynamically
61 * allocate a new IRQ or discover an IRQ that was pre-allocated by the
62 * hypervisor for use with their particular device. This gives the
63 * IRQ subsystem an opportunity to do interrupt-type-specific
64 * initialization.
65 *
66 * ISSUE: We should modify this API so that registering anything
67 * except percpu interrupts also requires providing callback methods
68 * for enabling and disabling the interrupt. This would allow the
69 * generic IRQ code to proxy enable/disable_irq() calls back into the
70 * PCI subsystem, which in turn could enable or disable the interrupt
71 * at the PCI shim.
72 */
73void tile_irq_activate(unsigned int irq, int tile_irq_type);
74
75/*
76 * For onboard, non-PCI (e.g. TILE_IRQ_PERCPU) devices, drivers know
77 * how to use enable/disable_percpu_irq() to manage interrupts on each
78 * core. We can't use the generic enable/disable_irq() because they
79 * use a single reference count per irq, rather than per cpu per irq.
80 */
81void enable_percpu_irq(unsigned int irq);
82void disable_percpu_irq(unsigned int irq);
83
84
85void setup_irq_regs(void);
86
87#endif /* _ASM_TILE_IRQ_H */