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-rw-r--r--arch/sparc64/kernel/smp.c11
-rw-r--r--arch/sparc64/kernel/trampoline.S4
-rw-r--r--arch/sparc64/kernel/traps.c1
-rw-r--r--arch/sparc64/kernel/tsb.S6
-rw-r--r--arch/sparc64/lib/atomic.S26
-rw-r--r--arch/sparc64/lib/bitops.S24
-rw-r--r--arch/sparc64/lib/rwsem.S7
-rw-r--r--arch/sparc64/mm/init.c2
-rw-r--r--arch/sparc64/mm/tsb.c4
-rw-r--r--arch/sparc64/mm/ultra.S2
10 files changed, 9 insertions, 78 deletions
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index f500b0618bb0..c6d06362728c 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -163,7 +163,7 @@ static inline long get_delta (long *rt, long *master)
163 for (i = 0; i < NUM_ITERS; i++) { 163 for (i = 0; i < NUM_ITERS; i++) {
164 t0 = tick_ops->get_tick(); 164 t0 = tick_ops->get_tick();
165 go[MASTER] = 1; 165 go[MASTER] = 1;
166 membar_storeload(); 166 membar_safe("#StoreLoad");
167 while (!(tm = go[SLAVE])) 167 while (!(tm = go[SLAVE]))
168 rmb(); 168 rmb();
169 go[SLAVE] = 0; 169 go[SLAVE] = 0;
@@ -257,7 +257,7 @@ static void smp_synchronize_one_tick(int cpu)
257 257
258 /* now let the client proceed into his loop */ 258 /* now let the client proceed into his loop */
259 go[MASTER] = 0; 259 go[MASTER] = 0;
260 membar_storeload(); 260 membar_safe("#StoreLoad");
261 261
262 spin_lock_irqsave(&itc_sync_lock, flags); 262 spin_lock_irqsave(&itc_sync_lock, flags);
263 { 263 {
@@ -267,7 +267,7 @@ static void smp_synchronize_one_tick(int cpu)
267 go[MASTER] = 0; 267 go[MASTER] = 0;
268 wmb(); 268 wmb();
269 go[SLAVE] = tick_ops->get_tick(); 269 go[SLAVE] = tick_ops->get_tick();
270 membar_storeload(); 270 membar_safe("#StoreLoad");
271 } 271 }
272 } 272 }
273 spin_unlock_irqrestore(&itc_sync_lock, flags); 273 spin_unlock_irqrestore(&itc_sync_lock, flags);
@@ -1122,7 +1122,6 @@ void smp_capture(void)
1122 smp_processor_id()); 1122 smp_processor_id());
1123#endif 1123#endif
1124 penguins_are_doing_time = 1; 1124 penguins_are_doing_time = 1;
1125 membar_storestore_loadstore();
1126 atomic_inc(&smp_capture_registry); 1125 atomic_inc(&smp_capture_registry);
1127 smp_cross_call(&xcall_capture, 0, 0, 0); 1126 smp_cross_call(&xcall_capture, 0, 0, 0);
1128 while (atomic_read(&smp_capture_registry) != ncpus) 1127 while (atomic_read(&smp_capture_registry) != ncpus)
@@ -1142,7 +1141,7 @@ void smp_release(void)
1142 smp_processor_id()); 1141 smp_processor_id());
1143#endif 1142#endif
1144 penguins_are_doing_time = 0; 1143 penguins_are_doing_time = 0;
1145 membar_storeload_storestore(); 1144 membar_safe("#StoreLoad");
1146 atomic_dec(&smp_capture_registry); 1145 atomic_dec(&smp_capture_registry);
1147 } 1146 }
1148} 1147}
@@ -1161,7 +1160,7 @@ void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1161 __asm__ __volatile__("flushw"); 1160 __asm__ __volatile__("flushw");
1162 prom_world(1); 1161 prom_world(1);
1163 atomic_inc(&smp_capture_registry); 1162 atomic_inc(&smp_capture_registry);
1164 membar_storeload_storestore(); 1163 membar_safe("#StoreLoad");
1165 while (penguins_are_doing_time) 1164 while (penguins_are_doing_time)
1166 rmb(); 1165 rmb();
1167 atomic_dec(&smp_capture_registry); 1166 atomic_dec(&smp_capture_registry);
diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 83abd5ae88a4..da1b781b5e65 100644
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -109,7 +109,6 @@ startup_continue:
109 */ 109 */
110 sethi %hi(prom_entry_lock), %g2 110 sethi %hi(prom_entry_lock), %g2
1111: ldstub [%g2 + %lo(prom_entry_lock)], %g1 1111: ldstub [%g2 + %lo(prom_entry_lock)], %g1
112 membar #StoreLoad | #StoreStore
113 brnz,pn %g1, 1b 112 brnz,pn %g1, 1b
114 nop 113 nop
115 114
@@ -214,7 +213,6 @@ startup_continue:
214 213
215 sethi %hi(prom_entry_lock), %g2 214 sethi %hi(prom_entry_lock), %g2
216 stb %g0, [%g2 + %lo(prom_entry_lock)] 215 stb %g0, [%g2 + %lo(prom_entry_lock)]
217 membar #StoreStore | #StoreLoad
218 216
219 ba,pt %xcc, after_lock_tlb 217 ba,pt %xcc, after_lock_tlb
220 nop 218 nop
@@ -330,7 +328,6 @@ after_lock_tlb:
330 328
331 sethi %hi(prom_entry_lock), %g2 329 sethi %hi(prom_entry_lock), %g2
3321: ldstub [%g2 + %lo(prom_entry_lock)], %g1 3301: ldstub [%g2 + %lo(prom_entry_lock)], %g1
333 membar #StoreLoad | #StoreStore
334 brnz,pn %g1, 1b 331 brnz,pn %g1, 1b
335 nop 332 nop
336 333
@@ -394,7 +391,6 @@ after_lock_tlb:
394 391
3953: sethi %hi(prom_entry_lock), %g2 3923: sethi %hi(prom_entry_lock), %g2
396 stb %g0, [%g2 + %lo(prom_entry_lock)] 393 stb %g0, [%g2 + %lo(prom_entry_lock)]
397 membar #StoreStore | #StoreLoad
398 394
399 ldx [%l0], %g6 395 ldx [%l0], %g6
400 ldx [%g6 + TI_TASK], %g4 396 ldx [%g6 + TI_TASK], %g4
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index 81ccd22e78d4..04994fc8700d 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -1371,7 +1371,6 @@ static int cheetah_fix_ce(unsigned long physaddr)
1371 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t" 1371 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1372 "ldxa [%1] %3, %%g0\n\t" 1372 "ldxa [%1] %3, %%g0\n\t"
1373 "casxa [%2] %3, %%g0, %%g0\n\t" 1373 "casxa [%2] %3, %%g0, %%g0\n\t"
1374 "membar #StoreLoad | #StoreStore\n\t"
1375 "ldxa [%0] %3, %%g0\n\t" 1374 "ldxa [%0] %3, %%g0\n\t"
1376 "ldxa [%1] %3, %%g0\n\t" 1375 "ldxa [%1] %3, %%g0\n\t"
1377 "membar #Sync" 1376 "membar #Sync"
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S
index c499214b501d..8c91d9b29a2f 100644
--- a/arch/sparc64/kernel/tsb.S
+++ b/arch/sparc64/kernel/tsb.S
@@ -317,7 +317,7 @@ tsb_flush:
317 srlx %g1, 32, %o3 317 srlx %g1, 32, %o3
318 andcc %o3, %g2, %g0 318 andcc %o3, %g2, %g0
319 bne,pn %icc, 1b 319 bne,pn %icc, 1b
320 membar #LoadLoad 320 nop
321 cmp %g1, %o1 321 cmp %g1, %o1
322 mov 1, %o3 322 mov 1, %o3
323 bne,pt %xcc, 2f 323 bne,pt %xcc, 2f
@@ -327,7 +327,7 @@ tsb_flush:
327 bne,pn %xcc, 1b 327 bne,pn %xcc, 1b
328 nop 328 nop
3292: retl 3292: retl
330 TSB_MEMBAR 330 nop
331 .size tsb_flush, .-tsb_flush 331 .size tsb_flush, .-tsb_flush
332 332
333 /* Reload MMU related context switch state at 333 /* Reload MMU related context switch state at
@@ -478,7 +478,7 @@ copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
478 nop 478 nop
479 479
480 retl 480 retl
481 TSB_MEMBAR 481 nop
482 .size copy_tsb, .-copy_tsb 482 .size copy_tsb, .-copy_tsb
483 483
484 /* Set the invalid bit in all TSB entries. */ 484 /* Set the invalid bit in all TSB entries. */
diff --git a/arch/sparc64/lib/atomic.S b/arch/sparc64/lib/atomic.S
index 70ac4186f62b..0268210ca168 100644
--- a/arch/sparc64/lib/atomic.S
+++ b/arch/sparc64/lib/atomic.S
@@ -43,29 +43,10 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
432: BACKOFF_SPIN(%o2, %o3, 1b) 432: BACKOFF_SPIN(%o2, %o3, 1b)
44 .size atomic_sub, .-atomic_sub 44 .size atomic_sub, .-atomic_sub
45 45
46 /* On SMP we need to use memory barriers to ensure
47 * correct memory operation ordering, nop these out
48 * for uniprocessor.
49 */
50#ifdef CONFIG_SMP
51
52#define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad;
53#define ATOMIC_POST_BARRIER \
54 ba,pt %xcc, 80b; \
55 membar #StoreLoad | #StoreStore
56
5780: retl
58 nop
59#else
60#define ATOMIC_PRE_BARRIER
61#define ATOMIC_POST_BARRIER
62#endif
63
64 .globl atomic_add_ret 46 .globl atomic_add_ret
65 .type atomic_add_ret,#function 47 .type atomic_add_ret,#function
66atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ 48atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
67 BACKOFF_SETUP(%o2) 49 BACKOFF_SETUP(%o2)
68 ATOMIC_PRE_BARRIER
691: lduw [%o1], %g1 501: lduw [%o1], %g1
70 add %g1, %o0, %g7 51 add %g1, %o0, %g7
71 cas [%o1], %g1, %g7 52 cas [%o1], %g1, %g7
@@ -73,7 +54,6 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
73 bne,pn %icc, 2f 54 bne,pn %icc, 2f
74 add %g7, %o0, %g7 55 add %g7, %o0, %g7
75 sra %g7, 0, %o0 56 sra %g7, 0, %o0
76 ATOMIC_POST_BARRIER
77 retl 57 retl
78 nop 58 nop
792: BACKOFF_SPIN(%o2, %o3, 1b) 592: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -83,7 +63,6 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
83 .type atomic_sub_ret,#function 63 .type atomic_sub_ret,#function
84atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ 64atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
85 BACKOFF_SETUP(%o2) 65 BACKOFF_SETUP(%o2)
86 ATOMIC_PRE_BARRIER
871: lduw [%o1], %g1 661: lduw [%o1], %g1
88 sub %g1, %o0, %g7 67 sub %g1, %o0, %g7
89 cas [%o1], %g1, %g7 68 cas [%o1], %g1, %g7
@@ -91,7 +70,6 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
91 bne,pn %icc, 2f 70 bne,pn %icc, 2f
92 sub %g7, %o0, %g7 71 sub %g7, %o0, %g7
93 sra %g7, 0, %o0 72 sra %g7, 0, %o0
94 ATOMIC_POST_BARRIER
95 retl 73 retl
96 nop 74 nop
972: BACKOFF_SPIN(%o2, %o3, 1b) 752: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -131,7 +109,6 @@ atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
131 .type atomic64_add_ret,#function 109 .type atomic64_add_ret,#function
132atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ 110atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
133 BACKOFF_SETUP(%o2) 111 BACKOFF_SETUP(%o2)
134 ATOMIC_PRE_BARRIER
1351: ldx [%o1], %g1 1121: ldx [%o1], %g1
136 add %g1, %o0, %g7 113 add %g1, %o0, %g7
137 casx [%o1], %g1, %g7 114 casx [%o1], %g1, %g7
@@ -139,7 +116,6 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
139 bne,pn %xcc, 2f 116 bne,pn %xcc, 2f
140 add %g7, %o0, %g7 117 add %g7, %o0, %g7
141 mov %g7, %o0 118 mov %g7, %o0
142 ATOMIC_POST_BARRIER
143 retl 119 retl
144 nop 120 nop
1452: BACKOFF_SPIN(%o2, %o3, 1b) 1212: BACKOFF_SPIN(%o2, %o3, 1b)
@@ -149,7 +125,6 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
149 .type atomic64_sub_ret,#function 125 .type atomic64_sub_ret,#function
150atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ 126atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
151 BACKOFF_SETUP(%o2) 127 BACKOFF_SETUP(%o2)
152 ATOMIC_PRE_BARRIER
1531: ldx [%o1], %g1 1281: ldx [%o1], %g1
154 sub %g1, %o0, %g7 129 sub %g1, %o0, %g7
155 casx [%o1], %g1, %g7 130 casx [%o1], %g1, %g7
@@ -157,7 +132,6 @@ atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
157 bne,pn %xcc, 2f 132 bne,pn %xcc, 2f
158 sub %g7, %o0, %g7 133 sub %g7, %o0, %g7
159 mov %g7, %o0 134 mov %g7, %o0
160 ATOMIC_POST_BARRIER
161 retl 135 retl
162 nop 136 nop
1632: BACKOFF_SPIN(%o2, %o3, 1b) 1372: BACKOFF_SPIN(%o2, %o3, 1b)
diff --git a/arch/sparc64/lib/bitops.S b/arch/sparc64/lib/bitops.S
index 6b015a6eefb5..2b7228cb8c22 100644
--- a/arch/sparc64/lib/bitops.S
+++ b/arch/sparc64/lib/bitops.S
@@ -8,29 +8,10 @@
8 8
9 .text 9 .text
10 10
11 /* On SMP we need to use memory barriers to ensure
12 * correct memory operation ordering, nop these out
13 * for uniprocessor.
14 */
15
16#ifdef CONFIG_SMP
17#define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad
18#define BITOP_POST_BARRIER \
19 ba,pt %xcc, 80b; \
20 membar #StoreLoad | #StoreStore
21
2280: retl
23 nop
24#else
25#define BITOP_PRE_BARRIER
26#define BITOP_POST_BARRIER
27#endif
28
29 .globl test_and_set_bit 11 .globl test_and_set_bit
30 .type test_and_set_bit,#function 12 .type test_and_set_bit,#function
31test_and_set_bit: /* %o0=nr, %o1=addr */ 13test_and_set_bit: /* %o0=nr, %o1=addr */
32 BACKOFF_SETUP(%o3) 14 BACKOFF_SETUP(%o3)
33 BITOP_PRE_BARRIER
34 srlx %o0, 6, %g1 15 srlx %o0, 6, %g1
35 mov 1, %o2 16 mov 1, %o2
36 sllx %g1, 3, %g3 17 sllx %g1, 3, %g3
@@ -45,7 +26,6 @@ test_and_set_bit: /* %o0=nr, %o1=addr */
45 and %g7, %o2, %g2 26 and %g7, %o2, %g2
46 clr %o0 27 clr %o0
47 movrne %g2, 1, %o0 28 movrne %g2, 1, %o0
48 BITOP_POST_BARRIER
49 retl 29 retl
50 nop 30 nop
512: BACKOFF_SPIN(%o3, %o4, 1b) 312: BACKOFF_SPIN(%o3, %o4, 1b)
@@ -55,7 +35,6 @@ test_and_set_bit: /* %o0=nr, %o1=addr */
55 .type test_and_clear_bit,#function 35 .type test_and_clear_bit,#function
56test_and_clear_bit: /* %o0=nr, %o1=addr */ 36test_and_clear_bit: /* %o0=nr, %o1=addr */
57 BACKOFF_SETUP(%o3) 37 BACKOFF_SETUP(%o3)
58 BITOP_PRE_BARRIER
59 srlx %o0, 6, %g1 38 srlx %o0, 6, %g1
60 mov 1, %o2 39 mov 1, %o2
61 sllx %g1, 3, %g3 40 sllx %g1, 3, %g3
@@ -70,7 +49,6 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */
70 and %g7, %o2, %g2 49 and %g7, %o2, %g2
71 clr %o0 50 clr %o0
72 movrne %g2, 1, %o0 51 movrne %g2, 1, %o0
73 BITOP_POST_BARRIER
74 retl 52 retl
75 nop 53 nop
762: BACKOFF_SPIN(%o3, %o4, 1b) 542: BACKOFF_SPIN(%o3, %o4, 1b)
@@ -80,7 +58,6 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */
80 .type test_and_change_bit,#function 58 .type test_and_change_bit,#function
81test_and_change_bit: /* %o0=nr, %o1=addr */ 59test_and_change_bit: /* %o0=nr, %o1=addr */
82 BACKOFF_SETUP(%o3) 60 BACKOFF_SETUP(%o3)
83 BITOP_PRE_BARRIER
84 srlx %o0, 6, %g1 61 srlx %o0, 6, %g1
85 mov 1, %o2 62 mov 1, %o2
86 sllx %g1, 3, %g3 63 sllx %g1, 3, %g3
@@ -95,7 +72,6 @@ test_and_change_bit: /* %o0=nr, %o1=addr */
95 and %g7, %o2, %g2 72 and %g7, %o2, %g2
96 clr %o0 73 clr %o0
97 movrne %g2, 1, %o0 74 movrne %g2, 1, %o0
98 BITOP_POST_BARRIER
99 retl 75 retl
100 nop 76 nop
1012: BACKOFF_SPIN(%o3, %o4, 1b) 772: BACKOFF_SPIN(%o3, %o4, 1b)
diff --git a/arch/sparc64/lib/rwsem.S b/arch/sparc64/lib/rwsem.S
index 1a4cc5654de4..91a7d29a79d5 100644
--- a/arch/sparc64/lib/rwsem.S
+++ b/arch/sparc64/lib/rwsem.S
@@ -17,7 +17,6 @@ __down_read:
17 bne,pn %icc, 1b 17 bne,pn %icc, 1b
18 add %g7, 1, %g7 18 add %g7, 1, %g7
19 cmp %g7, 0 19 cmp %g7, 0
20 membar #StoreLoad | #StoreStore
21 bl,pn %icc, 3f 20 bl,pn %icc, 3f
22 nop 21 nop
232: 222:
@@ -42,7 +41,6 @@ __down_read_trylock:
42 cmp %g1, %g7 41 cmp %g1, %g7
43 bne,pn %icc, 1b 42 bne,pn %icc, 1b
44 mov 1, %o1 43 mov 1, %o1
45 membar #StoreLoad | #StoreStore
462: retl 442: retl
47 mov %o1, %o0 45 mov %o1, %o0
48 .size __down_read_trylock, .-__down_read_trylock 46 .size __down_read_trylock, .-__down_read_trylock
@@ -58,7 +56,6 @@ __down_write:
58 cmp %g3, %g7 56 cmp %g3, %g7
59 bne,pn %icc, 1b 57 bne,pn %icc, 1b
60 cmp %g7, 0 58 cmp %g7, 0
61 membar #StoreLoad | #StoreStore
62 bne,pn %icc, 3f 59 bne,pn %icc, 3f
63 nop 60 nop
642: retl 612: retl
@@ -85,7 +82,6 @@ __down_write_trylock:
85 cmp %g3, %g7 82 cmp %g3, %g7
86 bne,pn %icc, 1b 83 bne,pn %icc, 1b
87 mov 1, %o1 84 mov 1, %o1
88 membar #StoreLoad | #StoreStore
892: retl 852: retl
90 mov %o1, %o0 86 mov %o1, %o0
91 .size __down_write_trylock, .-__down_write_trylock 87 .size __down_write_trylock, .-__down_write_trylock
@@ -99,7 +95,6 @@ __up_read:
99 cmp %g1, %g7 95 cmp %g1, %g7
100 bne,pn %icc, 1b 96 bne,pn %icc, 1b
101 cmp %g7, 0 97 cmp %g7, 0
102 membar #StoreLoad | #StoreStore
103 bl,pn %icc, 3f 98 bl,pn %icc, 3f
104 nop 99 nop
1052: retl 1002: retl
@@ -129,7 +124,6 @@ __up_write:
129 bne,pn %icc, 1b 124 bne,pn %icc, 1b
130 sub %g7, %g1, %g7 125 sub %g7, %g1, %g7
131 cmp %g7, 0 126 cmp %g7, 0
132 membar #StoreLoad | #StoreStore
133 bl,pn %icc, 3f 127 bl,pn %icc, 3f
134 nop 128 nop
1352: 1292:
@@ -155,7 +149,6 @@ __downgrade_write:
155 bne,pn %icc, 1b 149 bne,pn %icc, 1b
156 sub %g7, %g1, %g7 150 sub %g7, %g1, %g7
157 cmp %g7, 0 151 cmp %g7, 0
158 membar #StoreLoad | #StoreStore
159 bl,pn %icc, 3f 152 bl,pn %icc, 3f
160 nop 153 nop
1612: 1542:
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 185f34679110..4bd63968400d 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -214,7 +214,6 @@ static inline void set_dcache_dirty(struct page *page, int this_cpu)
214 "or %%g1, %0, %%g1\n\t" 214 "or %%g1, %0, %%g1\n\t"
215 "casx [%2], %%g7, %%g1\n\t" 215 "casx [%2], %%g7, %%g1\n\t"
216 "cmp %%g7, %%g1\n\t" 216 "cmp %%g7, %%g1\n\t"
217 "membar #StoreLoad | #StoreStore\n\t"
218 "bne,pn %%xcc, 1b\n\t" 217 "bne,pn %%xcc, 1b\n\t"
219 " nop" 218 " nop"
220 : /* no outputs */ 219 : /* no outputs */
@@ -236,7 +235,6 @@ static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
236 " andn %%g7, %1, %%g1\n\t" 235 " andn %%g7, %1, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t" 236 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t" 237 "cmp %%g7, %%g1\n\t"
239 "membar #StoreLoad | #StoreStore\n\t"
240 "bne,pn %%xcc, 1b\n\t" 238 "bne,pn %%xcc, 1b\n\t"
241 " nop\n" 239 " nop\n"
242 "2:" 240 "2:"
diff --git a/arch/sparc64/mm/tsb.c b/arch/sparc64/mm/tsb.c
index 587f8efb2e05..f0282fad632a 100644
--- a/arch/sparc64/mm/tsb.c
+++ b/arch/sparc64/mm/tsb.c
@@ -41,10 +41,8 @@ void flush_tsb_kernel_range(unsigned long start, unsigned long end)
41 KERNEL_TSB_NENTRIES); 41 KERNEL_TSB_NENTRIES);
42 struct tsb *ent = &swapper_tsb[hash]; 42 struct tsb *ent = &swapper_tsb[hash];
43 43
44 if (tag_compare(ent->tag, v)) { 44 if (tag_compare(ent->tag, v))
45 ent->tag = (1UL << TSB_TAG_INVALID_BIT); 45 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
46 membar_storeload_storestore();
47 }
48 } 46 }
49} 47}
50 48
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 86773e89dc1b..e4c146f7c7e9 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -125,7 +125,6 @@ __spitfire_flush_tlb_mm_slow:
125 .align 32 125 .align 32
126 .globl __flush_icache_page 126 .globl __flush_icache_page
127__flush_icache_page: /* %o0 = phys_page */ 127__flush_icache_page: /* %o0 = phys_page */
128 membar #StoreStore
129 srlx %o0, PAGE_SHIFT, %o0 128 srlx %o0, PAGE_SHIFT, %o0
130 sethi %uhi(PAGE_OFFSET), %g1 129 sethi %uhi(PAGE_OFFSET), %g1
131 sllx %o0, PAGE_SHIFT, %o0 130 sllx %o0, PAGE_SHIFT, %o0
@@ -507,7 +506,6 @@ xcall_fetch_glob_regs:
507 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2 506 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
508 add %g7, %g2, %g7 507 add %g7, %g2, %g7
509 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3 508 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
510 membar #StoreStore
511 stx %g3, [%g1 + GR_SNAP_THREAD] 509 stx %g3, [%g1 + GR_SNAP_THREAD]
512 retry 510 retry
513 511
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 22:39:02 -0500