2 files changed, 0 insertions, 35 deletions

diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index 8d72f8a1268e..9f6ca624892d 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -171,8 +171,6 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
                              : "g1", "g7");
 }
 
-extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
-
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 {
         struct page *page;
@@ -199,10 +197,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p
 
                 put_cpu();
         }
-
-        if (get_thread_fault_code())
-                __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
-                                   address, pte, get_thread_fault_code());
 }
 
 void flush_dcache_page(struct page *page)
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
index 5ff5e42fb9d4..058b8126c1a7 100644
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -180,35 +180,6 @@ __flush_dcache_page:	/* %o0=kaddr, %o1=flush_icache */
 
         .previous
 
-        .align          32
-__prefill_dtlb:
-        rdpr            %pstate, %g7
-        wrpr            %g7, PSTATE_IE, %pstate
-        mov             TLB_TAG_ACCESS, %g1
-        stxa            %o5, [%g1] ASI_DMMU
-        stxa            %o2, [%g0] ASI_DTLB_DATA_IN
-        flush           %g6
-        retl
-         wrpr           %g7, %pstate
-__prefill_itlb:
-        rdpr            %pstate, %g7
-        wrpr            %g7, PSTATE_IE, %pstate
-        mov             TLB_TAG_ACCESS, %g1
-        stxa            %o5, [%g1] ASI_IMMU
-        stxa            %o2, [%g0] ASI_ITLB_DATA_IN
-        flush           %g6
-        retl
-         wrpr           %g7, %pstate
-
-        .globl          __update_mmu_cache
-__update_mmu_cache:     /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
-        srlx            %o1, PAGE_SHIFT, %o1
-        andcc           %o3, FAULT_CODE_DTLB, %g0
-        sllx            %o1, PAGE_SHIFT, %o5
-        bne,pt          %xcc, __prefill_dtlb
-         or             %o5, %o0, %o5
-        ba,a,pt         %xcc, __prefill_itlb
-
         /* Cheetah specific versions, patched at boot time. */
 __cheetah_flush_tlb_mm: /* 18 insns */
         rdpr            %pstate, %g7