1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sparc64/kernel/chmc.c b/arch/sparc64/kernel/chmc.c
index 2ed401087cab..967b04886822 100644
--- a/arch/sparc64/kernel/chmc.c
+++ b/arch/sparc64/kernel/chmc.c
@@ -104,20 +104,20 @@ struct chmc {
 #define JBUSMC_REGS_SIZE                8
-#define JB_MC_REG1_DIMM2_BANK3          0x8000000000000000
+#define JB_MC_REG1_DIMM2_BANK3          0x8000000000000000UL
-#define JB_MC_REG1_DIMM1_BANK1          0x4000000000000000
+#define JB_MC_REG1_DIMM1_BANK1          0x4000000000000000UL
-#define JB_MC_REG1_DIMM2_BANK2          0x2000000000000000
+#define JB_MC_REG1_DIMM2_BANK2          0x2000000000000000UL
-#define JB_MC_REG1_DIMM1_BANK0          0x1000000000000000
+#define JB_MC_REG1_DIMM1_BANK0          0x1000000000000000UL
-#define JB_MC_REG1_XOR                  0x0000010000000000
+#define JB_MC_REG1_XOR                  0x0000010000000000UL
-#define JB_MC_REG1_ADDR_GEN_2           0x000000e000000000
+#define JB_MC_REG1_ADDR_GEN_2           0x000000e000000000UL
 #define JB_MC_REG1_ADDR_GEN_2_SHIFT     37
-#define JB_MC_REG1_ADDR_GEN_1           0x0000001c00000000
+#define JB_MC_REG1_ADDR_GEN_1           0x0000001c00000000UL
 #define JB_MC_REG1_ADDR_GEN_1_SHIFT     34
-#define JB_MC_REG1_INTERLEAVE           0x0000000001800000
+#define JB_MC_REG1_INTERLEAVE           0x0000000001800000UL
 #define JB_MC_REG1_INTERLEAVE_SHIFT     23
-#define JB_MC_REG1_DIMM2_PTYPE          0x0000000000200000
+#define JB_MC_REG1_DIMM2_PTYPE          0x0000000000200000UL
 #define JB_MC_REG1_DIMM2_PTYPE_SHIFT    21
-#define JB_MC_REG1_DIMM1_PTYPE          0x0000000000100000
+#define JB_MC_REG1_DIMM1_PTYPE          0x0000000000100000UL
 #define JB_MC_REG1_DIMM1_PTYPE_SHIFT    20
 #define PART_TYPE_X8            0

diff --git a/arch/sparc64/kernel/chmc.c b/arch/sparc64/kernel/chmc.c index 2ed401087cab..967b04886822 100644 --- a/arch/sparc64/kernel/chmc.c +++ b/arch/sparc64/kernel/chmc.c
@@ -104,20 +104,20 @@ struct chmc {
104		104
105	#define JBUSMC_REGS_SIZE 8	105	#define JBUSMC_REGS_SIZE 8
106		106
107	#define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000	107	#define JB_MC_REG1_DIMM2_BANK3 0x8000000000000000UL
108	#define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000	108	#define JB_MC_REG1_DIMM1_BANK1 0x4000000000000000UL
109	#define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000	109	#define JB_MC_REG1_DIMM2_BANK2 0x2000000000000000UL
110	#define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000	110	#define JB_MC_REG1_DIMM1_BANK0 0x1000000000000000UL
111	#define JB_MC_REG1_XOR 0x0000010000000000	111	#define JB_MC_REG1_XOR 0x0000010000000000UL
112	#define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000	112	#define JB_MC_REG1_ADDR_GEN_2 0x000000e000000000UL
113	#define JB_MC_REG1_ADDR_GEN_2_SHIFT 37	113	#define JB_MC_REG1_ADDR_GEN_2_SHIFT 37
114	#define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000	114	#define JB_MC_REG1_ADDR_GEN_1 0x0000001c00000000UL
115	#define JB_MC_REG1_ADDR_GEN_1_SHIFT 34	115	#define JB_MC_REG1_ADDR_GEN_1_SHIFT 34
116	#define JB_MC_REG1_INTERLEAVE 0x0000000001800000	116	#define JB_MC_REG1_INTERLEAVE 0x0000000001800000UL
117	#define JB_MC_REG1_INTERLEAVE_SHIFT 23	117	#define JB_MC_REG1_INTERLEAVE_SHIFT 23
118	#define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000	118	#define JB_MC_REG1_DIMM2_PTYPE 0x0000000000200000UL
119	#define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21	119	#define JB_MC_REG1_DIMM2_PTYPE_SHIFT 21
120	#define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000	120	#define JB_MC_REG1_DIMM1_PTYPE 0x0000000000100000UL
121	#define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20	121	#define JB_MC_REG1_DIMM1_PTYPE_SHIFT 20
122		122
123	#define PART_TYPE_X8 0	123	#define PART_TYPE_X8 0