2 files changed, 12 insertions, 1 deletions

diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c
index 0db2f7d9fab5..6e002aacb961 100644
--- a/arch/sparc64/mm/fault.c
+++ b/arch/sparc64/mm/fault.c
@@ -327,8 +327,12 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
                 insn = get_fault_insn(regs, 0);
                 if (!insn)
                         goto continue_fault;
+                /* All loads, stores and atomics have bits 30 and 31 both set
+                 * in the instruction.  Bit 21 is set in all stores, but we
+                 * have to avoid prefetches which also have bit 21 set.
+                 */
                 if ((insn & 0xc0200000) == 0xc0200000 &&
-                    (insn & 0x1780000) != 0x1680000) {
+                    (insn & 0x01780000) != 0x01680000) {
                         /* Don't bother updating thread struct value,
                          * because update_mmu_cache only cares which tlb
                          * the access came from.
diff --git a/arch/sparc64/mm/hugetlbpage.c b/arch/sparc64/mm/hugetlbpage.c
index 074620d413d4..fbbbebbad8a4 100644
--- a/arch/sparc64/mm/hugetlbpage.c
+++ b/arch/sparc64/mm/hugetlbpage.c
@@ -198,6 +198,13 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr)
         pmd_t *pmd;
         pte_t *pte = NULL;
 
+        /* We must align the address, because our caller will run
+         * set_huge_pte_at() on whatever we return, which writes out
+         * all of the sub-ptes for the hugepage range.  So we have
+         * to give it the first such sub-pte.
+         */
+        addr &= HPAGE_MASK;
+
         pgd = pgd_offset(mm, addr);
         pud = pud_alloc(mm, pgd, addr);
         if (pud) {